SCN2681T PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 SCN2681T Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook
1998 Sep 04
Philips Semiconductors Product specification SCN2681TDual asynchronous receiver/transmitter (DUART)
21998 Sep 04 853–1002 19970
DESCRIPTION
The Philips Semiconductors SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. The SCN2681T features a faster bus cycle time than the standard SCN2681. The quick bus cycle eliminates or reduces the need for wait states with fast CPUs and permits high throughput in I/O intensive systems. Higher external clock rates may be used with the transmitter, receiver and counter timer which in turn provide greater versatility in baud rate generation. The SCN2681T interfaces directly with microprocessors and may be used in a polled or interrupt driven system. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver is quadruple buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full. Also provided on the SCN2681T are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. For a complete functional description and programming information for the SCN2681T, refer to the SCN2681 product specification.
FEATURES
- Fast bus cycle times reduce or eliminate CPU wait states
- Dual full-duplex asynchronous receiver/transmitters
- Quadruple buffered receiver data registers
- Programmable data format – 5 to 8 data bits plus parity – Odd, even, no parity or force parity – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
- 16-bit programmable Counter/Timer
- Programmable baud rate for each receiver and transmitter selectable from: – 22 fixed rates: 50 to 115.2k baud – Non-standard rates to 115.2 – Non-standard user-defined rate derived from programmable counter/timer – External 1X or 16X clock
- Parity, framing, and overrun error detection
- False start bit detection
- Line break detection and generation
- Programmable channel mode – Normal (full-duplex) – Automatic echo – Local loopback – Remote loopback
- Multi-function programmable 16-bit counter/timer
- Multi-function 7-bit input port – Can serve as clock or control inputs – Change of state detection on four inputs – 100kΩ typical pull-up resistors
- Multi-function 8-bit output port – Individual bit set/reset capability – Outputs can be programmed to be status/interrupt signals
- Versatile interrupt system – Single interrupt output with eight maskable interrupting conditions – Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
- Maximum data transfer rates: 1X – 1MB/sec transmitter and receiver; 16X – 500kB/sec receiver and 250kB/sec transmitter
- Automatic wake-up mode for multidrop applications
- Start-end break interrupt/status
- Detects break which originates in the middle of a character
- On-chip crystal oscillator
- Single +5V power supply
- Commercial and industrial temperature ranges available
ORDERING INFORMATION
DESCRIPTION VCC = +5V +10%, TA = 0°C to +70°C DWG # 40-Pin Plastic Dual In-Line Package (600mil-wide DIP) SCN2681TC1N40 SOT129-1 44-Pin Plastic Lead Chip Carrier (PLCC) SCN2681TC1A44 SOT187-2 NOTE: For a full register description and programming information see the SCN2681.
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2 A0 24 INTRN
3 IP3 25 D6
5 IP1 27 D2
7 A3 29 OP6
8 IP0 30 OP4
9 WRN 31 OP2
10 RDN 32 OP0
11 RxDB 33 TxDA
12 NC 34 NC
13 TxDB 35 RxDA
14 OP1 36 X1/CLK
15 OP3 37 X2
16 OP5 38 RESET
17 OP7 39 CEN
18 D1 40 IP2
19 D3 41 IP6
20 D5 42 IP5
21 D7 43 IP4
22 GND 44 V
Figure 1. Pin Configurations Refer to SCN2681 for functional description.
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Figure 2. Block Diagram
Philips Semiconductors Product specification SCN2681TDual asynchronous receiver/transmitter (DUART)
1998 Sep 04 5
MNEMONIC TYPE NAME AND FUNCTION D0–D7 I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. CEN I Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is high, the DUART places the D0–D7 lines in the three-state condition. WRN I Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. RDN I Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. A0–A3 I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESET I Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the high state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high) state. Clears Test modes, sets MR pointer to MR1. INTRN O Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true. X1/CLK I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. X2 I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it. RxDA I Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low. RxDB I Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low. TxDA O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high, ‘space’ is low. TxDB O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high, ‘space’ is low. OP0 O Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated automatically on receive or transmit. OP1 O Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated automatically on receive or transmit. OP2 O Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output. OP3 O Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. OP4 O Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output. OP5 O Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output. OP6 O Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output. OP7 O Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output. IP0 I Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP1 I Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP2 I Input 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP3 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP4 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP5 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP6 I Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. VCC I Power Supply: +5V supply input. GND I Ground
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- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
- For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
- This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
- Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
- All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
- Typical values are at +25°C, typical supply voltages, and typical processing parameters.
- Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC .
- For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle. Figure 3. Reset Timing
- Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
- All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
- Typical values are at +25°C, typical supply voltages, and typical processing parameters.
- Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC .
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Figure 4. Bus Timing
- For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
- If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
RDN input even if the CEN is used as the strobing signal for bus operations.
- Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
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Figure 5. Port Timing
- For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
- INTRN or OP3-OP7 when used as interrupt outputs.
- The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
test environment are pronounced and can greatly affect the resultant measurement. Figure 6. Interrupt Timing
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When using an external clock it is preferred to drive X2 and leave X1 open. X2 is the input to the internal driver, while X1 is the output. R1 is only required if U1 will not drive to X2 high level. the amplifier input than to overdrive its output. Figure 7. Clock Timing
- Minimum frequencies are not tested but are guaranteed by design.
1 BIT TIME
Figure 8. Transmit
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Figure 9. Receive
- Timing shown for MR2(4) = 1.
- Timing shown for MR2(5) = 1. SD00094
Figure 10. Transmitter Timing
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- Timing shown for MR1(7) = 1.
Figure 11. Receiver Timing Figure 12. Wake-Up Mode
Philips Semiconductors Product specification SCN2681TDual asynchronous receiver/transmitter (DUART)
1998 Sep 04 12
DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1
Philips Semiconductors Product specification SCN2681TDual asynchronous receiver/transmitter (DUART)
1998 Sep 04 13
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Philips Semiconductors Product specification SCN2681TDual asynchronous receiver/transmitter (DUART)
1998 Sep 04 14
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 09-98 Document order number: 9397 750 04363 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.