SCN2681

SCN2681 PHILIPS

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/C0109 /C0110 /C0114 SCN2681 Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook

1998 Sep 04

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

21998 Sep 04 853–1077 19970

DESCRIPTION

The Philips Semiconductors SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver is quadruply buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full. Also provided on the SCN2681 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. The SCN2681 is available in three package versions: 40-pin and 28–pin, both 0.6” wide DIPs; a compact 24-pin 0.4” wide DIP; and a 44-pin PLCC.

FEATURES

• Dual full-duplex asynchronous receiver/transmitter
• Quadruple buffered receiver data registers
• Programmable data format – 5 to 8 data bits plus parity – Odd, even, no parity or force parity – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• Programmable baud rate for each receiver and transmitter selectable from: – 22 fixed rates: 50 to 115.2k baud
• 16-bit programmable Counter/Timer – Non-standard rates to 115.2Kb – One user-defined rate derived from programmable timer/counter – External 1X or 16X clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode – Normal (full-duplex) – Automatic echo – Local loopback – Remote loopback
• Multi-function programmable 16-bit counter/timer
• Multi-function 7-bit input port – Can serve as clock or control inputs – Change of state detection on four inputs – 100kΩ typical pull-up resistor
• Multi-function 8-bit output port – Individual bit set/reset capability – Outputs can be programmed to be status/interrupt signals
• Versatile interrupt system – Single interrupt output with eight maskable interrupting conditions – Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
• Maximum data transfer: 1X – 1MB/sec, 16X – 125kB/sec
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Detects break which originates in the middle of a character
• On-chip crystal oscillator
• Single +5V power supply
• Commercial and industrial temperature ranges available
• DIP and PLCC packages

ORDERING INFORMATION

DESCRIPTION VCC = +5V +5%, TA = 0°C to +70°C VCC = +5V +10%, TA = -40°C to +85°C Plastic DIP Plastic LCC Plastic DIP Plastic LCC 24-Pin1 SCN2681AC1N24 Not available SCN2681AE1N24 Not available 28-Pin2 SCN2681AC1N28 Not available SCN2681AE1N28 Not available 40-Pin2 SCN2681AC1N40 Not available SCN2681AE1N40 Not available 44-Pin Not available SCN2681AC1A44 Not available SCN2681AE1A44 NOTES: 1. 400mil-wide Dual In-Line Package 2. 600mil-wide Dual In-Line Package

1998 Sep 04 3

2 A0 24 INTRN

3 IP3 25 D6

5 IP1 27 D2

7 A3 29 OP6

8 IP0 30 OP4

9 WRN 31 OP2

10 RDN 32 OP0

11 RXDB 33 TXDA

12 NC 34 NC

13 TXDB 35 RXDA

14 OP1 36 X1/CLK

15 OP3 37 X2

16 OP5 38 RESET

17 OP7 39 CEN

18 D1 40 IP2

19 D3 41 IP6

20 D5 42 IP5

21 D7 43 IP4

22 GND 44 V

Figure 1. Pin Configurations

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 4

TYPE NAME AND FUNCTIONSYMBOL 40/44 28 24 TYPE NAME AND FUNCTION D0–D7 X X X I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status be- tween the DUART and the CPU. D0 is the least significant bit. CEN X X X I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines in the 3-State condition. WRN X X X I Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. RDN X X X I Read Strobe: When Low and CEN is also Low, causes the contents of the addressed regis- ter to be presented on the data bus. The read cycle begins on the falling edge of RDN. A0–A3 X X X I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESET X X X I Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inac- tive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MR1. INTRN X X X O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. X1/CLK X X X I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. X2 X X I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it. RxDA X X X I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low. RxDB X X X I Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low. TxDA X X X O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition when the transmitter is disabled, idle or when oper- ating in local loopback mode. “Mark” is High, “space” is Low. TxDB X X X O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition when the transmitter is disabled, idle or when oper- ating in local loopback mode. “Mark” is High, “space” is Low. OP0 X X O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit. OP1 X X O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated automatically on receive or transmit. OP2 X O Output 2: General purpose output or Channel A transmitter 1X or 16X clock output, or Chan- nel A receiver 1X clock output. OP3 X O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock output, or Channel B receiver 1X clock output. OP4 X O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output. OP5 X O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output. OP6 X O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output. OP7 X O Output 7: General purpose output or Channel B open-drain, active-Low, TxRDYB output. IP0 X I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP1 X I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP2 X X I Input 2: General purpose input or counter/timer external clock input. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP3 X I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP4 X I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 5

PIN DESCRIPTION (Continued) SYMBOL APPLICABLE TYPE NAME AND FUNCTIONSYMBOL 40/44 28 24 TYPE NAME AND FUNCTION IP5 X I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. IP6 X I Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current. VCC X X I Power Supply: +5V supply input. GND X X I Ground ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER RATING UNIT TA Operating ambient temperature range2 See Note 4 °C TSTG Storage temperature range -65 to +150 °C All voltages with respect to ground3 -0.5 to +6.0 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150oC maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC supply range. DC ELECTRICAL CHARACTERISTICS 1, 2, 3 TA = -40°C to +85°C, VCC = +5.0V 10% SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT VIL VIH VIH VIH VOL VOH VOH Input low voltage Input high voltage (except X1/CLK)5 Input high voltage (except X1/CLK)4 Input high voltage (X1/CLK) Output low voltage Output high voltage (except o.d. outputs)5 Output high voltage (except o.d. outputs)4 IOL = 2.4mA IOH = -400µA IOH = -400µA 2.5 2.4 2.9 0.8 0.4 V V V V V V V IIL ILL IX1L IX1H IX2L IX2H IOC IOCC Input leakage current Data bus 3-stage leakage current X1/CLK low input current X1/CLK high input current X2 low input current X2 high input current Open-collector output leakage current Power supply current VIN = 0 to VCC VO = 0.4 to VCC VIN = 0, X2 grounded VIN = 0, X2 floated VIN = VCC , X2 grounded VIN = VCC , X2 floated VIN = 0, X1/CLK floated VIN = VCC , X1/CLK floated VO = 0.4 to VCC 0°C to +70°C version -40°C to +85°C version -10 -10 -100 -10 -1.5 0.2 3.5 -30 +30 100 150 175 µA µA mA mA mA mA µA µA µA mA mA NOTES: 1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. 3. Typical values are at +25°C, typical supply voltages, and typical processing parameters. 4. TA < 0°C 5. TA > 0°C

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 6

AC CHARACTERISTICS TA = -40°C to +85°C 1, VCC = +5.0V 10%2, 3, 4, 5 SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER Min Typ Max UNIT Reset Timing (Figure 3) tRES RESET pulse width 200 ns Bus Timing (Figure 4)6 tAS A0-A3 setup time to RDN, WRN Low 10 ns tAH A0-A3 hold time from RDN, WRN Low 100 ns tCS CEN setup time to RDN, WRN Low 0 ns tCH CEN hold time from RDN, WRN High 0 ns tRW WRN, RDN pulse width 225 ns tDD Data valid after RDN Low 175 ns tDF Data bus floating after RDN High 100 ns tDS Data setup time before WRN High 100 ns tDH Data hold time after WRN High 20 ns tRWD High time between READs and/or WRITE7, 8 200 ns Port Timing (Figure 5)6 tPS Port input setup time before RDN Low 0 ns tPH Port input hold time after RDN High 0 ns tPD Port output valid after WRN High 400 ns Interrupt Timing (Figure 6) tIR INTRN (or OP3-OP7 when used as interrupts) negated from: Read RHR (RxRDY/FFULL interrupt) 300 ns Write THR (TxRDY interrupt) 300 ns Reset command (delta break interrupt) 300 ns Stop C/T command (counter interrupt) 300 ns Read IPCR (input port change interrupt) 300 ns Write IMR (clear of interrupt mask bit) 300 ns Clock Timing (Figure 7)10 tCLK X1/CLK High or Low time 100 ns fCLK X1/CLK frequency 2.0 3.6864 4.0 MHz tCTC CTCLK (IP2) High or Low time 100 ns fCTC CTCLK (IP2) frequency 0 4.0 MHz tRX 9 RxC High or Low time 220 ns fRX 9 RxC frequency (16X) (1X) 2.0 1.0 MHz MHz tTX 9 TxC High or Low time 220 ns fTX 9 TxC frequency (16X) (1X) 2.0 1.0 MHz MHz Transmitter Timing (Figure 8) tTXD 9 TxD output delay from TxC external clock input on IP pin 350 ns tTCS 9 Output delay from TxC low at OP pin to TxD data output 0 150 ns Receiver Timing (Figure 10) tRXS 9 RxD data setup time before RxC high at external clock input on IP pin240 ns tRXH 9 RxD data hold time after RxC high at external clock input on IP pin200 ns NOTES: 1. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 2. Parameters are valid over specified temperature range. 3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a and 2.0V as appropriate. 4. Typical values are at +25°C, typical supply voltages, and typical processing parameters. 5. Test condition for outputs: CL = 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC . 6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. 8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 9. This parameter is not applicable to the 28-pin device. 10. Operation to 0MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.

1998 Sep 04 7

Figure 2. Block Diagram communications Channels A and B, input port and output port. activated upon the occurrence of any of eight internal events.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 8

(IMR) and the Interrupt Status Register (ISR). The IMR may be programmed to select only certain conditions to cause INTRN to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. Outputs OP3-OP7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer. Timing Circuits The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from a 3.6864MHz crystal connected across the X1/CLK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART. If an external clock is used instead of a crystal, both X1 and X2 should use a configuration similar to the one in Figure 7. The baud rate generator operates from the oscillator or external clock input and is capable of generating 18 commonly used data communications baud rates ranging from 50 to 38.4k baud. The clock outputs from the BRG are at 16X the actual baud rate. The counter/timer can be used as a timer to produce a 16X clock for any other baud rate by counting down the crystal clock or an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or external timing signal. Counter/Timer (C/T) The counter timer is a 16 bit programmable divider that operates one of three modes: Counter, Timer or Time Out mode. In all three modes it uses the 16-bit value loaded to the CTUR and CTLR registers. (Counter timer upper and lower preset registers).

• In the timer mode it generates a square wave.
• In the counter mode it generates a time delay.
• In the time out mode it monitors the receiver data flow and signals data flow has paused. In the time out mode the receiver controls the starting/stopping of the C/T. The counter operates as a down counter and sets its output bit in the ISR (Interrupt Status Register) each time it passes through 0. The output of the counter/timer may be seen on one of the OP pins or as an Rx or Tx clock. The Timer/Counter is controlled with six (6) “commands”; Start C/T, Stop C/T, write C/T, preset registers, read C/T value, set or reset time out mode. Please see the detail of the commands under the Counter/Timer register descriptions. Communications Channels A and B Each communications channel of the SCN2681 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter can be selected independently from the baud rate generator, the counter timer, or from an external input. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition and sends an assembled character to the CPU. The input port pulse detection circuitry uses a 38.4kHz sampling clock derived from one of the baud rate generator taps. This results in a sampling period of slightly more than 25µs (this assumes that the clock input is 3.6864MHz). The detection circuitry, in order to guarantee that a true change in level has occurred, requires two successive samples at the new logic level be observed. As a consequence, the minimum duration of the signal change is 25µs if the transition occurs “coincident with the first sample pulse”. The 50µs time refers to the situation in which the change-of-state is “just missed” and the first change-of-state is not detected until 25µs later. Input Port The inputs to this unlatched 7-bit port can be read by the CPU by performing a read operation at address D16. A High input results in a logic 1 while a Low input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic. Four change-of-state detectors are provided which are associated with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High transition of these inputs lasting longer than 25 – 50µs, will set the corresponding bit in the input port change register. The bits are cleared when the register is read by the CPU. Any change-of-state can also be programmed to generate an interrupt to the CPU. All the IP pins have a small pull-up device that will source 1 to 4 A of current from V CC . These pins do not require pull-up devices or VCC connections if they are not used. Output Port The output port pins may be controlled by the OPR, OPCR, MR and CR registers. Via appropriate programming they may be just another parallel port to external circuits, or they may represent many internal conditions of the UART. When this 8-bit port is used as a general purpose output port, the output port pins drive a state which is the complement of the Output Port Register (OPR). OPR(n) = 1 results in OP(n) = Low and vice versa. Bits of the OPR can be individually set and reset. A bit is set by performing a write operation at address E16 with the accompanying data specifying the bits to be set (1 = set, 0 = no change). Likewise, a bit is reset by a write at address F16 with the accompanying data specifying the bits to be reset (1 = reset, 0 = no change). Outputs can be also individually assigned specific functions by appropriate programming of the Channel A mode registers (MR1A, MR2A), the Channel B mode registers (MR1B, MR2B), and the Output Port Configuration Register (OPCR). Please note that these pins drive both high and low. HOWEVER when they are programmed to represent interrupt type functions (such as receiver ready, transmitter ready or counter/timer ready) they will be switched to an open drain configuration in which case an external pull-up device would be required. TRANSMITTER OPERATION The SCN2681 is conditioned to transmit data when the transmitter is enabled through the command register. The SCN2681 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 9

generate an interrupt request at OP6 or OP7 and INTRN. When a character is loaded into the Transmit Holding Register (THR), the above conditions are negated. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again which means one full character time of buffering is provided. Characters cannot be loaded into the THR while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the THR, the TxD output remains High and the TxEMT bit in the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character into the THR. If the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. The transmitter can be forced to send a continuous Low condition by issuing a send break command. The transmitter can be reset through a software command. If it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. If CTS operation is enable, the CTSN input must be Low in order for the character to be transmitted. If it goes High in the middle of a transmission, the character in the shift register is transmitted and TxDA then remains in the marking state until CTSN goes Low. The transmitter can also control the deactivation of the RTSN output. If programmed, the RTSN output will be reset one bit time after the character in the transmit shift register and transmit holding register (if any) are completely transmitted, if the transmitter has been disabled. Receiver The SCN2681 is conditioned to receive data when enabled through the command register. The receiver looks for a High-to-Low (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16X clock for 7 1/2 clocks (16X clock mode) or at the next rising edge of the bit time clock (1X clock mode). If RxD is sampled High, the start bit is invalid and the search for a valid start bit begins again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and parity bit (if any) have been assembled, and one stop bit has been detected. The least significant bit is received first. The data is then transferred to the Receive Holding Register (RHR) and the RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character length is less than eight bits, the most significant unused bits in the RHR are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and RxD remains Low for one half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point (one-half bit time after the stop bit was sampled). The parity error, framing error, overrun error and received break state (if any) are strobed into the SR at the received character boundary, before the RxRDY status bit is set. If a break condition is detected (RxD is Low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the RHR and the received break bit in the SR is set to 1. The RxD input must return to high for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. Receiver FIFO The RHR consists of a First-In-First-Out (FIFO) stack with a capacity of three characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all three stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the RHR outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits (see below) are ‘popped’ thus emptying a FIFO position for new data. Receiver Status Bits In addition to the data word, three status bits (parity error, framing error, and received break) are also appended to each data character in the FIFO (overrun is not). Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the ‘character’ mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the ‘block’ mode, the status provided in the SR for these three bits is the logical-OR of the status for all characters coming to the top of the FIFO since the last ‘reset error’ command was issued. In either mode reading the SR does not affect the FIFO. The FIFO is ‘popped’ only when the RHR is read. Therefore the status register should be read prior to reading the FIFO. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4] will be set-upon receipt of the start bit of the new (overrunning) character). The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output will be negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output will be re-asserted automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device. Receiver Reset and Disable Receiver disable stops the receiver immediately – data being assembled if the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. A receiver reset will discard the present shift register data, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and re-align the FIFO read/write pointers. This has the appearance of “clearing or flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared! The data in the FIFO remains valid until overwritten by another received character. Because of this, erroneous reading or extra reads of the receiver FIFO will miss-align

1998 Sep 04 10

the FIFO pointers and result in the reading of previously read data. A receiver reset will re-align the pointers. corresponding data bits into the THR. break detect operate normally whether or not the receive is enabled. the registers is described in Table 1. should only be made while the C/T is stopped. register while the pointer is at MR1x, switches the pointer to MR2x. for each channel to provide total independent operation and control. normal operation since they are reserved for internal diagnostics. Table 1. SCN2681 Register Addressing SCC68681 and SCC2698B” in application notes elsewhere in this publication.

1998 Sep 04 11

Table 2. Register Bit Formats *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset. *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char. SCC68681 and SCC2698B” in application notes elsewhere in this publication. reset command (command 4x) or a receiver reset. The level at the OP pin is the inverse of the bit in the OPR register.

1998 Sep 04 12

Table 2. Register Bit Formats (Continued) MR1A is accessed when the Channel A MR pointer points to MR1. negated upon receipt of a valid start bit if the Channel A FIFO is full. programmed as an interrupt output via the OPCR. special multidrop mode described in the Operation section. selects the polarity of the A/D bit. start, parity, and stop bits.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 13

MR2A – Channel A Mode Register 2 MR2A is accessed when the Channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change the pointer. MR2A[7:6] – Channel A Mode Select Each channel of the DUART can operate in one of four modes. MR2A[7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. MR2A[7:6] = 01 places the channel in the automatic echo mode, which automatically re-transmits the received data. The following conditions are true while in automatic echo mode: 1. Received data is re-clocked and retransmitted on the TxDA out- put. 2. The receive clock is used for the transmitter. 3. The receiver must be enabled, but the transmitter need not be enabled. 4. The Channel A TxRDY and TxEMT status bits are inactive. 5. The received parity is checked, but is not regenerated for trans- mission, i.e. transmitted parity bit is as received. 6. Character framing is checked, but the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. 8. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled. Two diagnostic modes can also be configured. MR2A[7:6] = 10 selects local loopback mode. In this mode: 1. The transmitter output is internally connected to the receiver input. 2. The transmit clock is used for the receiver. 3. The TxDA output is held High. 4. The RxDA input is ignored. 5. The transmitter must be enabled, but the receiver need not be enabled. 6. CPU to transmitter and receiver communications continue nor- mally. The second diagnostic mode is the remote loopback mode, selected by MR2A[7:6] = 11. In this mode: 1. Received data is re-clocked and re-transmitted on the TxDA output. 2. The receive clock is used for the transmitter. 3. Received data is not sent to the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received. 5. The receiver must be enabled. 6. Character framing is not checked and the stop bits are retrans- mitted as received. 7. A received break is echoed as received until the next valid start bit is detected. The user must exercise care when switching into and out of the various modes. The selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the deselection occurs just after the receiver has sampled the stop bit (indicated in autoecho by assertion of RxRDY), and the transmitter is enabled, the transmitter will remain in autoecho mode until the entire stop has been retransmitted. MR2A[5] – Channel A Transmitter Request-to-Send Control CAUTION: When the transmitter controls the OP pin (usually used for the RTSN signal) the meaning of the pin is not RTSN at all! Rather, it signals that the transmitter has finished the transmission (i.e., end of block). This bit allows deactivation of the RTSN output by the transmitter. This output is manually asserted and negated by the appropriate commands issued via the command register. MR2[5] set to 1 caused the RTSN to be reset automatically one bit time after the character(s) in the transmit shift register and in the THR (if any) are completely transmitted (including the programmed number of stop bits) if a previously issued transmitter disable is pending. This feature can be used to automatically terminate the transmission as follows: 1. Program the auto-reset mode: MR2[5]=1 2. Enable transmitter, if not already enabled 3. Assert RTSN via command 4. Send message 5. After the last character of the message is loaded to the THR, disable the transmitter. (If the transmitter is underrun, a special case exists. See note below.) 6. The last character will be transmitted and the RTSN will be reset one bit time after the last stop bit is sent. NOTE: The transmitter is in an underrun condition when both the TxRDY and the TxEMT bits are set. This condition also exists immediately after the transmitter is enabled from the disabled or reset state. When using the above procedure with the transmitter in the underrun condition, the issuing of the transmitter disable must be delayed from the loading of a single, or last, character until the TxRDY becomes active again after the character is loaded. MR2A[4] – Channel A Clear-to-Send Control If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a 1, the transmitter checks the state of CTSAN (IPO) each time it is ready to send a character. If IPO is asserted (Low), the character is transmitted. If it is negated (High), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes Low. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character.. MR2A[3:0] – Channel A Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of .563 TO 1 AND .563 to 2 bits. In increments of 0.625 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1.0625 to 2 stop bits can be programmed in increments of .0625 bit. The receiver only checks for a ‘mark’ condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit is enabled) in all cases. If an external 1X clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and MR2A[3] = 1 selects two stop bits to be transmitted.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 14

MR1B – Channel B Mode Register 1 MR1B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR1 by RESET or by a ‘set pointer’ command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B. MR2B – Channel B Mode Register 2 MR2B is accessed when the Channel B MR pointer points to MR2, which occurs after any access to MR1B. Accesses to MR2B do not change the pointer. The bit definitions for mode registers 1 and 2 are identical to the bit definitions for MRA and MR2A except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. CSRA – Channel A Clock Select Register CSRA[7:4] – Channel A Receiver Clock Select This field selects the baud rate clock for the Channel A receiver as follows: CSRA[7:4] ACR[7] = 0 Baud Rate ACR[7] = 1 0000 50 75 0001 110 110 0010 134.5 134.5 0011 200 150 0100 300 300 0101 600 600 0110 1,200 1,200 0111 1,050 2,000 1000 2,400 2,400 1001 4,800 4,800 1010 7,200 1,800 1011 9,600 9,600 1100 38.4k 19.2k

1101 Timer Timer

1110 IP4–16X IP4–16X

1111 IP4–1X IP4–1X

(See also Table 5) The receiver clock is always a 16X clock except for CSRA[7] = 1111. CSRA[3:0] – Channel A Transmitter Clock Select This field selects the baud rate clock for the Channel A transmitter. The field definition is as per CSR[7:4] except as follows: CSRA[3:0] ACR[7] = 0 Baud Rate ACR[7] = 1 1110 1111 IP3–16X IP3–1X IP3–16X IP3–1X The transmitter clock is always a 16X clock except for CSR[3:0] = 1111. CSRB – Channel B Clock Select Register CSRB[7:4] – Channel B Receiver Clock Select This field selects the baud rate clock for the Channel B receiver. The field definition is as per CSRA[7:4] except as follows: CSRB[7:4] ACR[7] = 0 Baud Rate ACR[7] = 1 1110 1111 IP6–16X IP6–1X IP6–16X IP6–1X The receiver clock is always a 16X clock except for CSRB[7:4] = 1111. CSRB[3:0] – Channel B Transmitter Clock Select This field selects the baud rate clock for the Channel B transmitter. The field definition is as per CSRA[7:4] except as follows: CSRB[3:0] ACR[7] = 0 Baud Rate ACR[7] = 1 1110 1111 IP5–16X IP5–1X IP5–16X IP5–1X The transmitter clock is always a 16X clock except for CSRB[3:0] = 1111. CRA – Channel A Command Register CRA is a register used to supply commands to Channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word. CRA[7] – Not Used Should be set to zero for upward compatibility with newer parts. CRA[6:4] – Channel A Miscellaneous Command The encoded value of this field may be used to specify a single command as follows: CRA[6:4] – COMMAND 000 No command. 001 Reset MR pointer. Causes the Channel A MR pointer to point to MR1. 010 Reset receiver. Resets the Channel A receiver as if a hard- ware reset had been applied. The receiver is disabled and the FIFO is flushed. 011 Reset transmitter. Resets the Channel A transmitter as if a hardware reset had been applied. 100 Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status (al- though RB, PE and FE bits will also be cleared) and in block mode to clear all error status after a block of data has been received. 101 Reset Channel A break change interrupt. Causes the Chan- nel A break detect change bit in the interrupt status register (ISR[2]) to be cleared to zero.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 15

110 Start break. Forces the TxDA output Low (spacing). If the transmitter is empty the start of the break condition will be delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is com- pleted. If a character is in the THR, the start of the break will be delayed until that character, or any other loaded subse- quently are transmitted. The transmitter must be enabled for this command to be accepted. 111 Stop break. The TxDA line will go High (marking) within two bit times. TxDA will remain High for one bit time before the next character, if any, is transmitted. CRA[3] – Disable Channel A Transmitter This command terminates transmitter operation and reset the TxDRY and TxEMT status bits. However, if a character is being transmitted or if a character is in the THR when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. A disable transmitter cannot be loaded. CRA[2] – Enable Channel A Transmitter Enables operation of the Channel A transmitter. The TxRDY status bit will be asserted. CRA[1] – Disable Channel A Receiver This command terminates operation of the receiver immediately – a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special multidrop mode is programmed, the receiver operates even if it is disabled. See Operation section. CRA[0] – Enable Channel A Receiver Enables operation of the Channel A receiver. If not in the special wake up mode, this also forces the receiver into the search for start-bit state. CRB – Channel B Command Register CRB is a register used to supply commands to Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word. The bit definitions for this register are identical to the bit definitions for CRA, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. SRA – Channel A Status Register SRA[7] – Channel A Received Break This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received: further entries to the FIFO are inhibited until the RxDA line to the marking state for at least one-half a bit time two successive edges of the internal or external 1X clock. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the Channel A ‘change in break’ bit in the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. SRA[6] – Channel A Framing Error This bit, when set, indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first bit position. SRA[5] – Channel A Parity Error This bit is set when the ‘with parity’ or ‘force parity’ mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special multidrop mode the parity error bit stores the receive A/D bit. SRA[4] – Channel A Overrun Error This bit, when set indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a ‘reset error status’ command. SRA[3] – Channel A Transmitter Empty (TxEMTA) This bit will be set when the transmitter underruns, i.e., both the TxEMT and TxRDY bits are set. This bit and TxRDY are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. It is always set after transmission of the last stop bit of a character if no character is in the THR awaiting transmission. It is reset when the THR is loaded by the CPU, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the underrun condition. SRA[2] – Channel A Transmitter Ready (TxRDYA) This bit, when set, indicates that the THR is empty and ready to be loaded with a character. This bit is cleared when the THR is loaded by the CPU and is set when the character is transferred to the transmit shift register. TxRDY is reset when the transmitter is disabled or reset, and is set when the transmitter is first enabled, viz., characters loaded into the THR while the transmitter is disabled will not be transmitted. SRA[1] – Channel A FIFO Full (FFULLA) This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If a character is waiting in the receive shift register because the FIFO is full, FFULL will not be reset when the CPU reads the RHR. SRA[0] – Channel A Receiver Ready (RxRDYA) This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift to the FIFO and reset when the CPU reads the RHR, if after this read there are not more characters still in the FIFO. SRB – Channel B Status Register The bit definitions for this register are identical to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 16

OPCR – Output Port Configuration Register OPCR[7] – OP7 Output Select This bit programs the OP7 output to provide one of the following: – The complement of OPR[7]. – The Channel B transmitter interrupt output which is the comple- ment of TxRDYB. When in this mode OP7 acts as an Open- Col- lector output. Note that this output is not masked by the contents of the IMR. OPCR[6] – OP6 Output Select This bit programs the OP6 output to provide one of the following: – The complement of OPR[6]. – The Channel A transmitter interrupt output which is the comple- ment of TxRDYA. When in this mode OP6 acts as an Open-Col- lector output. Note that this output is not masked by the contents of the IMR. OPCR[5] – OP5 Output Select This bit programs the OP5 output to provide one of the following: – The complement of OPR[5]. – The Channel B transmitter interrupt output which is the comple- ment of ISR[5]. When in this mode OP5 acts as an Open-Collector output. Note that this output is not masked by the contents of the IMR. OPCR[4] – OP4 Output Select This field programs the OP4 output to provide one of the following: – The complement of OPR[4]. – The Channel B transmitter interrupt output which is the comple- ment of ISR[1]. When in this mode OP4 acts as an Open-Collec- tor output. Note that this output is not masked by the contents of the IMR. OPCR[3:2] – OP3 Output Select This bit programs the OP3 output to provide one of the following: – The complement of OPR[3]. – The counter/timer output, in which case OP3 acts as an Open- Collector output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR. – The 1X clock for the Channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. – The 1X clock for the Channel B receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. OPCR[1:0] – OP2 Output Select This field programs the OP2 output to provide one of the following: – The complement of OPR[2]. – The 16X clock for the Channel A transmitter. This is the clock selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] = 1111. – The 1X clock for the Channel A transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. – The 1X clock for the Channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. ACR – Auxiliary Control Register ACR[7] – Baud Rate Generator Set Select This bit selects one of two sets of baud rates to be generated by the BRG: 7.2k, 9.6k, and 38.4k baud. 9.6k, and 19.2k baud. The selected set of rates is available for use by the Channel A and B receivers and transmitters as described in CSRA and CSRB. Baud rate generator characteristics are given in Table 3. ACR[6:4] – Counter/Timer Mode And Clock Source Select This field selects the operating mode of the counter/timer and its clock source as shown in Table 4. ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR[7]) to be set. If a bit is in the ‘on’ state the setting of the corresponding bit in the IPCR will also result in the setting of ISR[7], which results in the generation of an interrupt output if IMR[7] = 1. If a bit is in the ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7]. IPCR – Input Port Change Register IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State These bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. IPCR[3:0] – IP3, IP2, IP1, IP0 Current State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. ISR – Interrupt Status Register This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’, the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 00 16 when the DUART is reset. ISR[7] – Input Port Change Status This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 17

ISR[6] – Channel B Change In Break This bit, when set, indicates that the Channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel B ‘reset break change interrupt’ command. ISR[5] – Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B[6]. If programmed as receiver ready, it indicates that a character has been received in Channel B and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the RHR. If after this read there are more characters still in the FIFO the bit will be set again after the FIFO is ‘popped’. If programmed as FIFO full, it is set when a character is transferred from the receive holding register to the receive FIFO and the transfer caused the Channel B FIFO to become full; i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If a character is waiting in the receive shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO. ISR[4] – Channel B Transmitter Ready This bit is a duplicate of TxRDYB (SRB[2]). ISR[3] – Counter Ready. In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero count). The bit is reset by a stop counter command. The command, however, does not stop the counter/timer. ISR[2] – Channel A Change in Break This bit, when set, indicates that the Channel A receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel A ‘reset break change interrupt’ command. ISR[1] – Channel A Receiver Ready Or FIFO Full The function of this bit is programmed by MR1A[6]. If programmed as receiver ready, it indicates that a character has been received in Channel A and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU read the RHR. IF after this read there are more characters still in the FIFO the bit will be set again after the FIFO is ‘popped’. If programmed as FIFO full, it is set when a character is transferred from the receive holding register to the receive FIFO and the transfer caused the Channel A FIFO to become full; i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If a character is waiting in the receive shift register because the FIFO is full, the bit will be set again when the ISR[0] and IMR waiting character is loaded into the FIFO. ISR[0] – Channel A Transmitter Ready This bit is a duplicate of TxRDYA (SRA[2]). IMR – Interrupt Mask Register The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’ the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3–OP7 or the reading of the ISR. CTUR and CTLR – Counter/Timer Registers The CTUR and CTLR hold the eight MSBs and eight LSBs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. The minimum value which may be loaded into the CTUR/CTLR registers is 000216. Note that these registers are write-only and cannot be read by the CPU. In the timer (programmable divider) mode, the CT generates a square wave with a period of twice the value (in clock periods) of the CTUR and CTLR. If the value in CTUR and CTLR is changed, the current half-period will not be affected, but subsequent half periods will be. In this mode the C/T runs continuously. Receipt of a start counter command (read with A3-A0 = 1110) causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTUR and CTLR. The waveform so generated is often used for a data clock. The formula for calculating the divisor n to load to the CTUR and CTLR for a particular 1X data clock is shown below: n /C0043counter clock frequency 1 6x2x baud rate desired Often this division will result in a non-integer number; 26.3, for example. One can only program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of 0.3/26.3 which is 1.14%; well within the ability asynchronous mode of operation. The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop counter command (read with A3-A0 = 1111). The command however, does not stop the C/T. The generated square wave is output on OP3 if it is programmed to be the C/T output. On power up and after reset, the timer/counter runs in timer mode and can only be restarted. Because it cannot be shut off or stopped, and runs continuously in timer mode, it is recommended that at initialization, the output port (OP3) should be masked off through the OPCR[3:2] = 00 until the T/C is programmed to the desired operational state. In the counter mode, the C/T counts down the number of pulses loaded into CTUR and CTLR by the CPU. Counting begins upon receipt of a counter command. Upon reaching terminal count (0000 16), the counter ready interrupt bit (ISR[3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If OP3 is programmed to be the output of the C/T, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state and ISR[3] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTUR and CTLR at any time, but the new count becomes effective only on the next start counter command. If new values have not been loaded, the previous count values are preserved and used for the next count cycle. In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTUR and CTLR.

1998 Sep 04 18

Table 3. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz NOTE: Duty cycle of 16x clock is 50% ± 1%. Table 4. ACR 6:4 Field Definition

000 Counter External (IP2)

001 Counter TxCA – 1x clock of Channel A transmitter

010 Counter TxCB – 1x clock of Channel B transmitter

011 Counter Crystal or external clock (x1/CLK) divided by 16

100 Timer (square wave) External (IP2)

101 Timer (square wave) External (IP2) divided by 16

110 Timer (square wave) Crystal or external clock (x1/CLK)

111 Timer (square wave) Crystal or external clock (x1/CLK) divided by 16

NOTE: Timer mode generates a squarewave.

1998 Sep 04 19

Figure 3. Reset Timing Figure 4. Bus Timing Figure 5. Port Timing

1998 Sep 04 20

1. INTRN or OP3 – OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from themidpoint of the switching signal, VM , to a

and can greatly affect the resultant measurement. Figure 6. Interrupt Timing When using an external clock it is preferred to drive X2 and leave X1 open. X2 is the input to the internal driver, while X1 is the output. R1 is only required if U1 will not drive to X2 high level. the amplifier input than to overdrive its output. Figure 7. Clock Timing

1 BIT TIME

Figure 8. Transmit

1998 Sep 04 21

Figure 9. Receiver Timing

1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1. SD00094

Figure 10. Transmitter Timing

1998 Sep 04 22

1. Timing shown for MR1(7) = 1.

Figure 11. Receiver Timing Figure 12. Wake-Up Mode

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 23

The output ports are controlled from three places: the OPCR register, the OPR register, and the MR registers. The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the “Set Output Port Bits Command” and the “Reset Output Bits Command”. These commands are at E and F, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a one in bit location 5 of the data word used with the “Set Output Port Bits” command will result in OPR5 being set to one. The OP5 would then be set to zero (V SS ). Similarly, a one in bit position 5 of the data word associated with the “Reset Output Ports Bits” command would set OPR5 to zero and, hence, the pin OP5 to a one (VDD ). The CTS, RTS, CTS Enable Tx signals CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal is active low; thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active low and is, thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin op0 and RTSBN is on OP1. A receiver’s RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2(4) is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven high, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter’s CTS input. The receiver will set RTS high when the receiver FIFO is full AND the start bit of the fourth character is sensed. Transmission then stops with four valid characters in the receiver. When MR2(4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2(4) is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1(7) is the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be RTS. However, a point of confusion arises in that OP0 (or OP1) may also be controlled by the transmitter. When the transmitter is controlling this pin, its meaning is not RTS at all. It is, rather, that the transmitter has finished sending its last data byte. Programming the OP0 or OP1 pin to be controlled by the receiver and the transmitter at the same time is allowed, but would usually be incompatible. RTS is expressed at the OP0 or OP1 pin which is still an output port. Therefore, the state of OP0 or OP1 should be set low for the receiver to generate the proper RTS signal. The logic at the output is basically a NAND of the OPR register and the RTS signal as generated by the receiver. When the RTS flow control is selected via the MR(7) bit state of the OPR register is not changed. Terminating the use of “Flow Control” (via the MR registers) will return the OP0 or OP1 pins to the control of the OPR register. Transmitter Disable Note The sequence of instructions enable transmitter — load transmit holding register — disable transmitter will result in nothing being sent if the time between the end of loading the transmit holding register and the disable command is less that 3/16 bit time in the 16x mode or one bit time in the 1x mode. Also, if the transmitter, while in the enabled state and underrun condition, is immediately disabled after a single character is loaded to the transmit holding register, that character will not be sent. In general, when it is desired to disable the transmitter before the last character is sent AND the TxEMT bit is set in the status register (TxEMT is always set if the transmitter has underrun or has just been enabled), be sure the TxRDY bit is active immediately before issuing the transmitter disable instruction. TxRDY sets at the end of the “start bit” time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register. Non-standard baud rates are available as shown in Table 5 below, via the BRG Test function.

1998 Sep 04 24

Table 5. Baud Rates Extended

1101 Timer Timer Timer Timer

1110 I/O2 – 16X I/O2 – 16X I/O2 – 16X I/O2 – 16X

1111 I/O2 – 1X I/O2 – 1X I/O2 – 1X I/O2 – 1X

NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes. continue to function properly. programming will be preserved and available before reset. The reset will NOT affect the programming. reset. The reset will NOT affect the programming. approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10–5 at 9600 baud. SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 25

DIP24: plastic dual in-line package; 24 leads (400 mil) SOT248-1

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 26

DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 27

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 28

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 29

Philips Semiconductors Product specification SCN2681Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04 30

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 09-98 Document order number: 9397 750 04362 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.