SCN2652AC2F40

NXP Semiconductors

Multi-protocol communications controller MPCC 1995 May 01

Manufacturer: NXP Semiconductors

Document: 22 Pages / 134Kb

Request Quote Download Datasheet Read online HTML view

More from NXP Semiconductors Browse S parts

Online Datasheet

Read SCN2652AC2F40 online.

SCN2652 PHILIPS | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 28

Technical content

/C0109 /C0110 /C0114 SCN2652/SCN68652 Multi-protocol communications controller (MPCC) Product specification IC19 Data Handbook

1995 May 01

Philips Semiconductors Product specification SCN2652/SCN68652Multi-protocol communications controller (MPCC)

21995 May 01 853-1068 15179

DESCRIPTION

The SCN2652/68652 Multi-Protocol Communications Controller (MPCC) is a monolithic n-channel MOS LSI circuit that formats, transmits and receives synchronous serial data while supporting bit-oriented or byte control protocols. The chip is TTL compatible, operates from a single +5V supply, and can interface to a processor with an 8 or 16-bit bidirectional data bus.

APPLICATIONS

Intelligent terminals
Line controllers
Network processors
Front end communications
Remote data concentrators
Communication test equipment
Computer to computer links

FEATURES

DC to 2Mbps data rate
Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
Programmable operation – 8 or 16-bit tri-state data bus – Error control – CRC or VRC or none – Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP – SYNC or secondary station address comparison for BCP-BOP – Idle transmission of SYNC/FLAG or MARK for BCP-BOP
Automatic detection and generation of special BOP control sequences, i.e., FLAG, ABORT, GA
Zero insertion and deletion for BOP
Short character detection for last BOP data character
SYNC generation, detection, and stripping for BCP
Maintenance mode for self-testing
TTL compatible
Single +5V supply PIN CONFIGURATION Pin Function Pin Function 1N C 2 3 N C 2C E 2 4 A 0

3 RxC 25 BYTE

4 RxSI 26 DBEN

5 S/F 27 DB07

6 RxA 28 DB06

7 RxDA 29 DB05

8 RxSA 30 DB04

9 RxE 31 DB03

10 GND 32 DB02

11 DB08 33 DB01

12 NC 34 NC

13 DB09 35 DB00

14 DB10 36 V

15 DB11 37 RESET

16 DB12 38 TxA

17 DB13 39 TxBE

18 DB14 40 TxU

19 DB15 41 TxE

/W 42 TxSQ

21 A2 43 TxC

22 A1 44 MM

NOTE: DB00 is least significant bit, highest number (that is, DB15, A2) is most significant bit. 2120 40CE RxC RxSI S/F RxA RxDA RxSA RxE GND DB08 DB09 DB10 DB11 DB12 DB13 DB14 DB15 R /W A1 A0 BYTE DBEN DB07 DB06 DB05 DB04 DB03 DB02 DB01 DB00 VCC RESET TxA TxBE TxU TxE TxSQ TxC MM DIP TOP VIEW SD00057 Figure 1. Pin Configuration

1995 May 01 3

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
For operating at elevated temperatures the device must be derated based on +150°C maximum junction temperature.
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature

range and operating supply range.

16 BITS

8 BITS

Figure 2. Block Diagram

Philips Semiconductors Product specification SCN2652/SCN68652Multi-protocol communications controller (MPCC)

1995 May 01 4

MNEMONIC PIN NO. TYPE NAME AND FUNCTION DB15–DB00 17–10 24–31 I/O Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status information to or from the processor. Corresponding bits of the high and low order bytes can be wire OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low. A2–A0 19–21 I Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or byte basis. See Register Address section. BYTE 22 I Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies 16-bit data bus transfers. CE 1 I Chip Enable: A high input permits a data bus operation when DBEN is activated. R /W 18 I Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the addressed register. A low input causes the contents of the addressed register to be presented on the data bus. DBEN 23 I Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read, the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is loaded into the addressed register and TxBE will be reset if TDSR was addressed. RESET 33 I Reset: A high level initializes all internal registers (to zero) and timing. MM 40 I Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted. RxE 8 I Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the receiver logic and initializes all receiver registers and timing. RxA 5 O Receiver Active: RxA is asserted when the first data character of a message is ready for the processor. In the BOP mode this character is the address. The received address must match the secondary station address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR 13) is set, the first non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA is reset by a low level at RxE. RxDA* 6 O Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to be presented to the processor. This output is reset when RDSRL is read. RxC 2 I Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial data into the RxSR from RxSI. S/F 4 O SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected. RxSA* 7 O Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSRH except for RSOM. It is cleared when RDSRH is read. RxSI 3 I Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’. TxE 37 I Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG (BOP) or last character (BCP) is output on TxSO. TxA 34 O Transmitter Active: TxA is asserted after TSOM (TDSR8) is set and TxE is raised. This output will reset when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO. TxBE* 35 O Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control information or data. The processor should respond by loading theTDSR which resets TxBE. TxU* 36 O Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line fill depends on PCSAR 11. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the falling edge of TxC. TxC 39 I Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts data out of the TxSR to TxSO. TxSO 38 O Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’. VCC 32 I +5V: Power supply. GND 9 I Ground: 0V reference ground. *Indicates possible interrupt signal

1995 May 01 5

Table 1. Register Access SYNC character (BCP) or secondary station address (BOP). PCR Parameter control register 8 RDSR H contains receiver status information. RDSR Receive data/status register 16 RDSR L = RxDB contains the received assembled character. accumulation/generation (RxCRC, TxCRC). Table 2. Error Control Table 3. Special Characters

For IDLE = 0 or 1 respectively.

Refer to Register Formats for mnemonics and description. Figure 3. Short Form Register Bit Formats

1995 May 01 6

Detected in SYNC FF and 7 MS bits of CCSR.
In BOP mode, a minimum of two data characters must be received to turn the receiver active.

Figure 4. MPCC Receiver Data Path

TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR.
In BCP parity selected will be generated after each character is shifted out of TxSR.

1 BIT

Figure 5. MPCC Transmitter Data Path

Philips Semiconductors Product specification SCN2652/SCN68652Multi-protocol communications controller (MPCC)

1995 May 01 7

The MPCC can be functionally partitioned into receiver logic, transmitter logic, registers that can be read or loaded by the processor, and data bus control circuitry. The register bit formats are shown in Figure 3 while the receiver and transmitter data paths are depicted in Figures 4 and 3. RECEIVER OPERATION General After initializing the parameter control registers (PCSAR and PCR), the RxE input must be set high to enable the receiver data path. The serial data on the RxSI is synchronized and shifted into an 8-bit Control Character Shift Register (CCSR) on the rising edge of RxC. A comparison between CCSR contents and the FLAG (BOP) or SYNC (BCP) character is made until a match is found. At that time, the S/F output is asserted for one RxC time and the 16-bit Holding Shift Register (HSR) is enabled. The receiver then operates as described below. BOP Operation A flowchart of receiver operation in BOP mode appears in Figure 6. Zero deletion (after five ones are received) is implemented on the received serial data so that a data character will not be interpreted as a FLAG, ABORT, or GA. Bits following the FLAG are shifted through the CCSR, HSR, and into the Receiver Shift Register (RxSR). A character will be assembled in the RxSR and transferred to the RDSR L for presentation to the processor. At that time the RxDA output will be asserted and the processor must take the character no later than one RxC time after the next character is assembled in the RxSR. If not, an overrun (RDSR11 = 1) will occur and succeeding characters will be lost. The first character following the FLAG is the secondary station address. If the MPCC is a secondary station (PCSAR12 = 1), the contents of RxSR are compared with the address stored in PCSAR L. A match indicates the forthcoming message is intended for the station; the RxA output is asserted, the character is loaded into RDSRL, RxDA is asserted and the Receive Start of Message bit (RSOM) is set. No match indicates that another station is being addressed and the receiver searches for the next FLAG. If the MPCC is a primary station, (PCSAR12 = 0), no secondary address check is made; RxA is asserted and RSOM is set once the first non-FLAG character has been loaded into RDSRL and RxDA has been asserted. Extended address field can be supported by software if PCSAR 12 = 0. When the 8 bits following the address character have been loaded into RDSRL and RxDA has been asserted, RSOM will be cleared. The processor should read this 8-bit character and interpret it as the Control field. Received serial data that follows is read and interpreted as the information field by the processor. It will be assembled into character lengths as specified by PCR8–10. As before, RxDA is asserted each time a character has been transferred into RDSRL and is cleared when RDSR L is read by the processor. RDSRH should only be read when RxSA is asserted. This occurs on a zero to one transition of any bit in RDSR H except for RSOM. RxSA and all bits in RDSRH except RSOM are cleared when RDSRH is read. The processor should check RDSR9–15 each time RxSA is asserted. If RDSR9 is set, then RDSR12–15 should be examined. Receiver character length may be changed dynamically in response to RxDA: read the character in RxDB and write the new character length into RxCL. The character length will be changed on the next receiver character boundary. A received residual (short) character will be transferred into RxDB after the previous character in RxDB has been read, i.e. there will not be an overrun. In general the last two characters are protected from overrun. The CRC–CCITT, if specified by PCSAR 8–10, is accumulated in RxCRC on each character following the FLAG. When the closing FLAG is detected in the CCSR, the received CRC is in the 16-bit HSR. At that time, the Receive End of Message bit (REOM) will be set; RxSA and RxDA will be asserted. The processor should read the last data character in RDSRL and the receiver status in RDSR 9–15. If RDSR15 = 1, there has been a transmission error; the accumulated CRC–CCITT is incorrect. If RDSR12–14 ≠ 0, last data character is not of prescribed length. Neither the received CRC nor closing FLAG are presented to the processor. The processor may drop RxE or leave it active at the end of the received message. RxBCP Operation The operation of the receiver in BCP mode is shown in Figure 7. The receiver initially searches for two successive SYNC characters, of length specified by PCR 8–10, that match the contents of PCSARL. The next non-SYNC character or next SYNC character, if stripping is not specified (PCSAR13 = 0), causes RxA to be asserted and enables the receiver data path. Once enabled, all characters are assembled in RxSR and loaded into RDSR L. RxDA is active when a character is available in RDSRL. RxSA is active on a 0 to 1 transition of any bit in RDSRH . The signals are cleared when RDSRl or RDSRH are read respectively. If CRC–16 error control is specified by PCSAR8–10, the processor must determine the last character received prior to the CRC field. When that character is loaded into RDSRL and RxDA is asserted, the received CRC will be in CCSR and HSRL. To check for a transmission error, the processor must read the receiver status (RDSR H ) and examine RDSR15. This bit will be set for one character time if an error free message has been received. If RDSR 15 = 0, the CRC–16 is in error. The state of RDSR15 in BCP CRC mode does not set RxSA. Note that this bit should be examined only at the end of a message. The accumulated CRC will include all characters starting with the first non-SYNC character if PCSAR 13 = 1, or the character after the opening two SYNCs if PCSAR 13 = 0. This necessitates external CRC generation/checking when supporting IBM’s BISYNC. This can be accomplished using the Philips Semiconductors SCN2653 Polynomial Generator/Checker. See Typical Applications. If VRC has been selected for error control, parity (odd or even) is regenerated on each character and checked when the parity bit is received. A discrepancy causes RDSR15 to be set and RxSA to be asserted. This must be sensed by the processor. The received parity bit is stripped before the character is presented to the processor. When the processor has read the last character of the message, it should drop RxE which disables the receiver logic and initializes all receiver registers and timing.

1995 May 01 8

Figure 6. BOP Receive is raised. Then, transmitter operation depends on protocol mode.

Philips Semiconductors Product specification SCN2652/SCN68652Multi-protocol communications controller (MPCC)

1995 May 01 9

MPCC, the processor should load TDSRL with the first character of the message. TSOM should be cleared at the same time TDSRL is loaded (16-bit data bus) or immediately thereafter (8-bit data bus). FLAGS are sent as long as TSOM = 1. For counting the number of FLAGs, the processor should reassert TSOM in response to the assertion of TxBE.All succeeding characters are loaded into TDSR L by the processor when TxBE = 1. Each character is serialized in TxSR and transmitted on TxSO. Internal zero insertion logic stuffs a “0” into the serial bit stream after five successive “1s” are sent. This insures a data character will not match a FLAG, ABORT, or GA reserved control character. As each character is transmitted, the Frame Check Sequence (FCS) is generated as specified by Error Control Mode (PCSAR 8–10). The FCS should be the CRC–CCITT polynomial (X16 + X12 + X5 + 1) preset to 1s. If an underrun occurs (processor is not keeping up with the transmitter), TxU and TERR (TDSR 15) will be asserted with ABORT or FLAG used as the TxSO line fill depending on the state of IDLE (PCSAR11). The processor must set TSOM to reset the underrun condition. To retransmit the message, the processor should proceed with the normal start of message sequence. A residual character of 1 to 7 bits may be transmitted at the end of the information field. In response to TxBE, write the residual character length into TxCL and load TxDB with the residual character. Dynamic alteration of character length should be done in exactly the same sequence. The character length will be changed on the next transmit character boundary. After the last data character has been loaded into TDSR L and sent to TxSR (TxBE = 1), the processor should set TEOM (TDSR9). The MPCC will finish transmitting the last character followed by the FCS and the closing FLAG. The processor should clear TEOM and drop TxE when the next TxBE is asserted. This corresponds to the start of closing FLAG transmission. When TxE has been dropped. TxA will be low 1 1/2 bit times after the last bit of the closing FLAG has been transmitted. TxSO will be marked after the closing FLAG has been transmitted. If TxE and TEOM are high, the transmitter continues to send FLAGs. The processor may initiate the next message by resetting TEOM and setting TSOM, or by loading TDSR L with a data character and then simply resetting TSOM (without setting TSOM). TxBCP Operation Transmitter operation for BCP mode is shown in Figure 9. TxA will be asserted after TSOM = 1 and TxE is raised. At that time SYNC characters are sent from PCSARL or TDSRL (IDLE = 0 or 1) as long as TSOM = 1. TxBE is asserted at the start of transmission of the first SYNC character. For counting the number of SYNCs, the processor should reassert TSOM in response to the assertion of TxBE. When TSOM = 0 transmission is from TDSRL, which must be loaded with characters from the processor each time TxBE is asserted. If this loading is delayed for more than one character time, an underrun results: TxU and TERR are asserted and the TxSO line fill depend on IDLE (PCSAR 11). The processor must set TSOM and retransmit the message to recover. This is not compatible with IBM’s BISYNC, so that the user must not underrun when supporting that protocol. CRC–16, if specified by PCSAR8–10, is generated on each character transmitted from TDSRL when TSOM =0. The processor must set TEOM = 1 after the last data character has been sent to TxSR (TxBE = 1). The MPCC will finish transmitting the last data character and the CRC–16 field before sending SYNC characters which are transmitted as long as TEOM = 1. If SYNCs are not desired after CRC–16 transmission, the processor should clear TEOM and lower TxE when the TxBE corresponding to the start of CRC–16 transmission is asserted. When TEOM = 0, the line is marked and a new message may be initiated by setting TSOM and raising TxE. If VRC is specified, it is generated on each data character and the data character length must not exceed 7 bits. For software LRC or CRC, TEOM should be set only if SYNC’s are required at the end of the message block. SPECIAL CASE: The capability to transmit 16 spaces is provided for line turnaround in half duplex mode or for a control recovery situation. This is achieved by setting TSOM and TEOM, clearing TEOM when TxBE = 1, and proceeding as required. PROGRAMMING Prior to initiating data transmission or reception, PCSAR and PCR must be loaded with control information from the processor. The contents of these registers (see Register Format section) will configure the MPCC for the user’s specific data communication environment. These registers should be loaded during power-on initialization and after a reset operation. They can be changed at any time that the respective transmitter or receiver is disabled. The default value for all registers is zero. This corresponds to BOP, primary station mode, 8-bit character length, FCS = CRC–CCITT preset to 1s. For BOP mode the character length register (PCR) may be set to the desired values during system initialization. The address and control fields will automatically be 8-bits. If a residual character is to be transmitted, TxCL should be changed to the residual character length prior to transmission of that character. DATA BUS CONTROL The processor must set up the MPCC register address (A2–A0), chip enable (CE), byte select (BYTE), and read/write (R/W) inputs before each data bus transfer operation. During a read operation (R/W = 0), the leading edge of DBEN will initiate an MPCC read cycle. The addressed register will place its contents on the data bus. If BYTE = 1, the 8-bit byte is placed on DB15–08 or DB07–00 depending on the H/L status of the register addressed. Unused bits in RDSR L are zero. If BYTE = 0, all 16 bits (DB15–00) contain MPCC information. The trailing edge of DBEN will reset RxDA and/or RxSA if RDSRL or RDSRH is addressed respectively. DBEN acts as the enable and strobe so that the MPCC will not begin its internal read cycle until DBEN is asserted. During a write operation (R/W = 1), data must be stable on DB15–08 and/or DB07–00 prior to the leading edge of DBEN. The stable data is strobed into the addressed register by DBEN. TxBE will be cleared if the addressed register was TDSRH or TDSRL.

1995 May 01 10

Test made every RxC time.
Test made on Rx character boundary.

Figure 7. BCP Receive

1995 May 01 11

*GA will be transmitted if TGA is set together with TEOM. Figure 8. BOP Transmit

1995 May 01 12

Figure 9. BCP Transmit

1995 May 01 13

Table 4. MPCC Register Addressing

PCR lower byte does not exist. It will be all “0”s when read.

** Corresponding high and low order pins must be tied together. Table 5. Parameter Control Register (PCR)–(R/W) valid after transmission of single byte address and control fields have been received. remaining bits of PCR are not affected during loading. Always 0 when read. remaining bits of PCR are not affected during loading. Always 0 when read.

1995 May 01 14

Table 6. Parameter Control SYNC/Address Register (PCSAR)–(R/W) to determine if the message is meant for this station. transmit bit synchronization with bit length specified by RxCL and TxCL. ECM should be loaded by the processor during initialization or when both data paths are idle.

11 IDLE Determines line fill character to be used if transmitter underrun occurs (TxU asserted and

TERR set) and transmission of special characters for BOP/BCP. BOP IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1. IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1. BCP IDLE = 0 transmit initial SYNC characters and underrun line fill characters from theS/AR. IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun. load the secondary address into TxDB. receiver after the first non-FLAG character has been received. 13 SS/GA Strip SYNC/Go Ahead. Operation depends on mode. the receiver to terminate the frame upon detection of an ABORT or FLAG. SYNC’s after the initial two SYNC’s to the processor.

14 PROTO Determines MPCC Protocol mode

‘11111111’ as well as the normal secondary station address.

1995 May 01 15

Table 7. Transmit Data/Status Register (TDSR) (R/W except TDSR15) 09 TEOM Transmit end of message. Used to terminate a transmitted message. transmitted if TABORT or TGA are set when TEOM = 1. new message can be initiated. If CRC is not selected, TEOM should not be set.

15 TERR Read

before underrun is not valid.

1995 May 01 16

Table 8. Receiver Data/Status Register (RDSR)–(Read Only)

08 RSOM BOP Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and

RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA.

09 REOM BOP Receiver end of message = 1 when the closing FLAG is detected and the last data character

H , reset operation, or dropping of RxE.

10 RAB/GA BOP Received ABORT or GA character = 1 when the receiver senses an ABORT character if

operation, or dropping of RxE. A received abort does not set RxDA. H , reset operation, or dropping of RxE. residual character is right justified inRDSRL.

15 RERR BOP/BCP Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or

when RxSA is set in BCP with VRC. RERR = 1 indicates CRC–16 received correctly (CRC = 0). RERR = 0 indicates VRC is correct.

1995 May 01 17

Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature

range and operating supply range.

m = TxC low and applies to writing to TDSRH only.

Figure 10. Timing Diagrams

1995 May 01 18

Figure 11. Timing Diagrams (cont.)

8 TxC1

SYNC may be 5 to 8 bits and will contain parity bit as specified.
TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes

character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message). Figure 12. Timing Diagrams (cont.)

1995 May 01 19

TxBE goes low relative to the falling edge of DBEN corresponding to loading TDSRH/L. It goes high one TxC before character transmission begins and also when TxA has been
TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message initiated.
TxA goes low after TxE has been dropped and 1 1/2 TxC’s after the last bit of the closing FLAG has been transmitted.

Figure 13. Timing Diagrams (cont.)

When SCN2652 generated CRC is not required. TEOM should only be set if SYNCs are to follow the message block. In that case, TxE should be dropped in response to TxBE

of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages. Figure 14. Timing Diagrams (cont.)

1995 May 01 20

TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2 TxC times (where n = transmit character length). TxU is reset on the TxC falling edge follow-

ing assertion of the TSOM command.

An underrun will occur at the next character boundary if TEOM is reset and the transmitter remains enabled, unless the TSOM command is asserted or a character is loaded into

Figure 15. Timing Diagrams (cont.)

RxA goes high relative to falling edge of RxC when RxE is high and: a. A data character following two SYNC’s is in RxDB (BCP mode). b. Character following FLAG is in RxDB

(BOP primary station mode). c. Character following FLAG is in RxDB and character matches the secondary station address or all parties address (BOP secondary station mode).

RxDA goes high on RxC falling edge when a character in RxDB is ready to be read. It comes up before RxSA and goes low on the falling edge of DBEN when RxDB is read.
S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BOP) is detected.

Figure 16. Timing Diagrams (cont.)

1995 May 01 21

At the end of a BOP message, RxSA goes high when FLAG detection (S/F 1) forces REOm to be set. Processor should read the last data character (RDSRL) and status (RDSRH )

which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status.

RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).
RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped.

Figure 17. Timing Diagrams (cont.)

Possible µP interrupt requests are: RxDA RxSA TxBE TxU
Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn
Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa.
RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low.
Corresponding high and low order bits of DB must be OR tied.

Figure 18. Typical Applications

1995 May 01 22

For non-DMA operation TxBE and RxDA are set to the processor which then loads or reads data characters as required.