SCN2651 PHILIPS
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Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
11994 Apr 27 853-1067 12793
DESCRIPTION
The Philips Semiconductors SCN2651 PCI is a universal synchronous/asynchronous data communications controller chip designed for microcomputer systems. It interfaces directly to the Philips Semiconductors SCN2650 microprocessor and may be used in a polled or interrupt driven system environment. The SCN2651 accepts programmed instructions from the microprocessor and supports many serial data communication disciplines, synchronous and asynchronous, in the full or half-duplex mode. The PCI serializes parallel data characters received from the microprocessor for transmission. Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer. The SCN2651 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode. The PCI is constructed using Philips Semiconductors n-channel silicon gate depletion load technology and is packaged in a 28-pin DIP.
FEATURES
- Synchronous operation – 5- to 8-bit characters – Single or double SYN operation – Internal character synchronization – Transparent or non-transparent mode – Automatic SYN or DLE-SYN insertion – SYN or DLE stripping – Odd, even, or no parity – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps (1X clock)
- Asynchronous operation – 5- to 8-bit characters – 1, 1-1/2 or 2 stop bits – Odd, even, or no parity – Parity, overrun and framing error detection – Line break detection and generation – False start bit detection – Automatic serial echo mode – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps (1X clock) DC to 62.5kbps (16X clock) DC to 15.625kbps (64X clock) PIN CONFIGURA TIONS VCC RxC DTR RTS DSR RESET BRCLK TxD TxEMT/DSCHG CTS DCD TxRDYRxRDY R/W CE TxC GND RxD DIP TOP VIEW SD00049 OTHER FEATURES
- Internal or external baud rate clock
- 16 internal rates – 50 to 19,200 baud
- Double buffered transmitter and receiver
- Full or half duplex operation
- TTL compatible inputs and outputs
- Single 5V power supply
- No system clock required
- 28-pin dual in-line package
APPLICATIONS
- Intelligent terminals
- Network processors
- Front-end processors
- Remote data concentrators
- Computer to computer links
- Serial peripherals ORDERING CODE PACKAGES VCC = 5V +5% DWG #PACKAGES Commercial 0°C to +70°C Industrial -40°C to +85°C DWG # 0°C to +70°C -40°C to +85°C 28-Pin Plastic Dual In-Line Package (DIP) SCN2651CC1N28 Not available SOT117-2
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 2
D0–D7 RESET A 0 A 1 R /W CE DATA BUS BUFFER OPERA TION CONTROL MODE REGISTER 1 BAUD RA TE GENERATOR AND CLOCK CONTROL SYN/DLE CONTROL SYN 1 REGISTER SYN 2 REGISTER DLE REGISTER TRANSMITTER TRANSMIT DA TA TxD MODE REGISTER 2 COMMAND REGISTER STA TUS REGISTER BRCLK TxC RxC DSR MODEM CONTROL DCD CTS RTS DTR TxEMT/ * DSCHG HOLDING REGISTER TRANSMIT SHIFT REGISTER TxRDY RECEIVE RECEIVE DA TA RECEIVER RxD RxRDY SHIFT REGISTER HOLDING REGISTER (27, 28, 1, 2, 5, 6, 7, 8) (21) (12) (10) (13) (11) (20) (9) (25) (22) (16) (17) (23) (24) (18) (15) (19) (14) (3) SD00050 ABSOLUTE MAXIMUM RA TINGS 1 SYMBOL PARAMETER RATING UNIT TA Operating ambient temperature2 Note 4 °C TSTG Storage temperature -65 to +150 °C /n636861720000000000000000All voltages with respect to ground3 -0.5 to +6.0 /n636861720000000000000000V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. CAPACITANCE TA = 25°C, VCC = 0V SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT Capacitance C IN C OUT C I/O Input Output Input/Output fC = 1MHz Unmeasured pins tied to ground pF pF pF
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 3
DC ELECTRICAL CHARACTERISTICS 1, 2, 3 SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT Input voltage VIL VIH Low High 2.0 0.8 V V Output voltage VOL VOH Low High IOL = 1.6mA IOH = -100µA 2.4 0.4 V V IIL Input leakage current VIN = 0 to 5.25V -10 10 µA 3-State output leakage current ILH ILL Data bus high Data bus low VO = 4.0V VO = 0.45V -10 -10 µA µA ICC Power supply current 150 mA NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBRL ) and at 3. Typical values are at +25°C, typical supply voltages and typical processing parameters. AC ELECTRICAL CHARACTERISTICS 1, 2, 3 LIMITS SYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT Pulse width tRES tCE Reset Chip enable 1000 300 ns ns Set-up and hold time tAS tAH tCS tCH tDS tDH tRXS tRXH Address setup Address hold R /W control setup R /W control hold Data setup for write Data hold for write RX data setup RX data hold 225 300 350 ns ns ns ns ns ns ns ns tDD tDF tCED Data delay time for read Data bus floating time for read CE to CE delay C L = 100pF C L = 100pF 700 250 150 ns ns ns Input clock frequency fBRG fR/T6 Baud rate generator TxC or RxC 1.0 dc 5.0688 5.0738 1.0 MHz MHz Clock width tBRH 5 tBRL 5 tR/TH tR/TL6 Baud rate high Baud rate low TxC or RxC high TxC or RxC low 500 500 ns ns ns ns tTXD tTCS TxD delay from falling edge of TxC Skew between TxD changing and falling edge of TxC output4 C L = 100pF C L = 100pF 0 650 ns ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBRL ) and at 3. Typical values are at +25°C, typical supply voltages and typical processing parameters. 4. Parameter applies when internal transmitter clock is used. 5. Under test conditions of 5.0688MHz, fBRG , tBRH , and tBRL measured at VIH and VIL respectively. 6. tR/T and tR/TL shown for all modes except local loopback. For local loopback mode fR/T = 0.7MHz and tR/TL = 700ns min.
1994 Apr 27 4
21 RESET Reset I
13 R /W Read or write command I
11 CE Chip enable input I
22 DSR Data set ready I
24 DTR Data terminal ready O
23 RTS Request to send O
17 CTS Clear to send I
16 DCD Data carrier detected I
18 TxEMT /DSCHG Transmitter empty or data set change O
9 TxC Transmitter clock I/O
25 RxC Receiver clock I/O
19 TxD Transmitter data O
3 RxD Receiver data I
15 TxRDY Transmitter ready O
14 RxRDY Receiver ready O
20 BRCLK Baud rate generator clock I
26 VCC +5V supply I
4 GND Ground I
Table 1. Baud Rate Generator Characteristics frequency 4.9152MHz. 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X. interfaces to the microprocessor data bus via a data bus buffer. be selected for full-duplex operation. See Table 1. stream of data on the TxD output pin. indication between the CPU and a modem. storing the SYN1, SYN2, and DLE characters provided by the CPU.
1994 Apr 27 5
communications device or system. described in the PCI programming section of the data sheet. conversion of data received from a modem or equivalent device. framework specified by the control words. the high order unused bits in the holding register are set to zero. Table 2. CPU-Related Signals and remains there until initialized with the appropriate control words. A1 – A0 10, 12 I Address lines used to select internal PCI registers. R /W 13 I Read command when low, write command when high. the least significant bit, D7 the most significant bit. which can be used as an interrupt to the CPU. TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high. It is an open drain output which can be used as an interrupt to the CPU.
1994 Apr 27 6
Table 3. Device-Related Signals transmitter clocks are used.
- The transmitted data changes on the falling edge of the clock. If internal transmitter clock is
RxD 3 I Serial data input to the receiver. “Mark” is high, “Space” is low. appears as status register bit SR7. Causes a low output on TxEMT/DSCHG when its state changes. status register bit SR6. Causes a low output on TxEMT/DSCHG when its state changes. transmission, the character in the transmit shift register will be transmitted before termination. condition by setting the send break command bit high. completed sending the previous character. is programmed, the appropriate SYN/DLE registers must be loaded. The PCI can be reconfigured at any time during program execution. to address each register are shown in Table 4. write operations with the conditions A1 = 0, A0 = 1, and R/W = 1.
1994 Apr 27 7
- Mode registers 1 and 2 define the general operational
is selected by MR24 or MR25. does not include the start and stop bits in asynchronous mode. synchronization and for character fill when the transmitter is idle. detect (with MR14 = 0) are enabled. control the frequency of the internal baud rate generator (BRG). Table 4. SCN2651 Register Addressing
1 X X X 3-State data bus
NOTE: See AC Characteristics section for timing requirements. an output at 1X the baud rate. SYN2 before DLE can be written. Figure 1. SCN2651 Initialization Flowchart
1994 Apr 27 8
Table 5. Mode Register 1 (MR1) Table 6. Mode Register 2 (MR2) Table 7. Command Register (CR) (RxEN) enable or disable the transmitter and receiver respectively. Bits CR1 (DTR) and CR5 (RTS) control the DTR and RTS outputs. Data at the outputs is the logical complement of the register data. in response to the next TxRDY.
1994 Apr 27 9
Table 8. Status Register (SR) internal latch for this bit. accordance with the mode and status register instructions. is disabled. Only the first character of a break condition is echoed. The TxD output will go high until the next valid start is detected.
- Data assembled by the receiver are automatically placed in the
- The transmitter is clocked by the receive clock.
- The TxEMT/DSCHG pin will reflect only the data set change
- The TxEN command (CR0) is ignored.
- In the non-transparent, single SYN mode (MR17 – MR16 = 10),
to the receive data holding register (RHR).
- In the non-transparent, double SYN mode (MR17 – MR16 = 00),
immediately preceded by SYN1, are not transferred the RHR.
- In transparent mode (MR16 = 1), character in the data stream
DLE detect and SYN detect status bits (SR3 and SR5).
- The transmitter output is connected to the receiver input.
- DTR is connected to DCD and RTS is connected to CTS.
- The receiver is clocked by the transmit clock.
- The DTR , RTS and TxD outputs are held high.
- The CTS, DCD, DSR and RxD inputs are ignored.
that CR0 (TxEN), CR1 (DTR), and CR5 (RTS) must be set to 1. CR2 (RxEN) is ignored by the PCI.
- Data assembled by the receiver are automatically placed in the
- The transmitter is clocked by the receive clock.
- No data is sent to the local CPU, but he error status conditions
- The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held high.
- All other signals operate normally.
corresponding output, are valid only when the transmitter is enabled.
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 10
character has been loaded into the holding register from the receive shift register and is ready to be read by the CPU. If equal to zero, there is no new character in the holding register. This bit is cleared when the CPU reads the receive data holding register or when the receiver is disabled by CR2. When set, the RxRDY output is low. The TxEMT/DSCHG bit, SR2, when set, indicates either a change of state of the DSR or DCD inputs or that the transmit shift register has completed transmission of a character and no new character has been loaded into the transmit data holding register. Note that in synchronous mode this bit will be set even though the appropriate “fill” character is transmitted. TxEMT will not go active until at least one character has been transmitted. It is cleared by loading the transmit data holding register. The DSCHG condition is enabled when TxEN = 1 or RxEN = 1. If the status register is read twice and SR2 = 1 while SR6 and SR7 remain unchanged, then a TxEMT condition exists. It is cleared when the status register is read by the CPU. When SR2 is set, the TxEMT/DSCHG output is low. SR3, when set, indicates a received parity error when parity is enabled by MR14. In synchronous transparent mode (MR16 = 1), with parity disabled, it indicates that a character matching the DLE register has been received. However, only the first DLE of two successive DLEs will set SR3. This bit is cleared when the receiver is disabled and by the reset error command, CR4. The overrun error status bit, SR4, indicates that the previous character loaded into the receive holding register was not read by the CPU at the time a new received character was transferred into it. This bit is cleared when the receiver is disabled and by the reset error command, CR4. In asynchronous mode, bit SR5 signifies that the received character was not framed by the programmed number of stop bits. (If 1.5 stop bits are programmed, only the first stop bit is checked.) If RHR = 0 when SR5 = 1, a break condition is present. In synchronous non-transparent mode (MR16 = 0), it indicates receipt of the SYN1 character in single SYN mode or the SYN1 – SYN2 pair in double SYN mode. In synchronous transparent mode (MR16 = 1), this bit is set upon detection of the initial synchronizing characters (SYN1 or SYN1 – SYN2) and, after synchronization has been achieved, when a DLE–SYN1 pair is received. The bit is reset when the receiver is disabled, when the reset error command is given in asynchronous mode, and when the status register is read by the CPU in the synchronous mode. SR6 and SR7 reflect the conditions of the DCD and DSR inputs respectively. A low input sets its corresponding status bit and a high input clears it.
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 11
BRCLK, TxC , RxC 1/fBRG tR/TH tBRH tR/TL tBRL 1/fR/T CLOCK TRANSMIT RECEIVE TxC (INPUT)
1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS) TxD TxC (OUTPUT) tTxD tTCS tTxD RxD RxC (IX) tRXS tRXH tCE tCED CE A 0, A1 R /W tAS tCS tAH tCH D 0–D 7 (WRITE) tDS tDH BUS FLOATING NOT VALID BUS FLOATINGDATA VALID tDD tDF D 0–D 7 (READ) READ AND WRITE SD00052
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 12
TIMING DIAGRAMS (Continued) 1 2 3 4 5 DATA 1 1 2 3 4 5 DATA 2 1 2 3 4 5 DATA 3 1 2 3 4 5 SYN 1 1 2 3 4 5 DATA 4 1 2 3 4 5 DATA 1 A B C 1 2 3 4 5A B C DATA 2 1 2 3 4 5A B C DATA 3 1 2A DATA 4 D D DATA 1 DATA 2 DATA 3 DATA 4 DATA 1 DATA 2 DATA 3 DATA 4 TxC (1X) TxD TxEN TxRDY TxEMT CE FOR WRITE OF THR TxD TxEN TxRDY TxEMT CE FOR WRITE OF THR ASYNCHRONOUS MODE SYNCHRONOUS MODE TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode]) NOTES: A = Start bit B = Stop bit 1 C = Stop bit 2 D = TxD marking condition TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit. SD00053
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 13
TIMING DIAGRAMS (Continued) 1 2 3 4 5 SYN 1 1 2 3 4 5 DATA 1 1 2 3 4 5 DATA 2 1 2 3 4 5 DATA 3 1 2 3 4 5 DATA 4 1 2 3 4 5 DATA 1 A B C 1 2 3 4 5A B C DATA 2 1 2 3 4 5A DATA 3 D READ RHR (DATA 1) READ RHR (DATA 3) READ STATUS RxC RxD RxEN RxRDY CE FOR READ RxD RxEN RxRDY CE FOR READ ASYNCHRONOUS MODE SYNCHRONOUS MODE RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode]) NOTES: A = Start bit B = Stop bit 1 C = Stop bit 2 D = TxD marking condition 1 2 3 4 5 DATA 5 IGNORED READ RHR (DATA 1) READ RHR (DATA 2) READ RHR (DATA 3) READ RHR (DATA 3) READ STATUS SYNDET STA TUS BIT D_ _ B C 1 2 3A DATA 4 OVERRUN STA TUS BIT SD00054
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 14
(OPT) 5.0688MHz OSCILLATOR ASYNCHRONOUS INTERFACE TO CRT TERMINAL CRT TERMINAL ADDRESS BUS CONTROL BUS DATA BUS RxD TxD SCN2651 ASYNCHRONOUS INTERFACE T O TELEPHONE LINES DSR DTR CTS RTS DCD BRCLK ASYNC MODEM 5.0688MHz OSCILLATOR PHONE LINE INTERFACE TELEPHONE LINE SD00055
Philips Semiconductors Product specification SCN2651Programmable communications interface (PCI)
1994 Apr 27 15
TYPICAL APPLICATIONS (Continued) ADDRESS BUS CONTROL BUS DATA BUS RxD TxD SCN2651 SYNCHRONOUS TERMINAL OR PERIPHERAL DEVICE SYNCHRONOUS INTERFACE T O TERMINAL OR PERIPHERAL DEVICE ADDRESS BUS CONTROL BUS DATA BUS RxD TxD SCN2651 SYNCHRONOUS INTERFACE T O TELEPHONE LINES DCD RTS DSR DTR SYNC MODEM PHONE LINE INTERFACE TELEPHONE LINE RxC TxC RxC TxC CTS SD00056