SCHS047G

Texas Instruments

Data sheet acquired from Harris Semiconductor

Manufacturer: Texas Instruments

Document: 28 Pages / 1Mb

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NTE4052BT TI | Alldatasheet

Document overview

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PDF pages: 28

Technical content

Features

Wide Range of Digital and Analog Signal Levels P-P
Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD -VEE = 18V
High OFF Resistance, Channel Leakage of±100pA (Typ) at VDD -VEE = 18V
Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD -VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD -VEE = 20V)
Matched Switch Characteristics, rON = 5Ω (Typ) for VDD -VEE = 15V
Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2µW (Typ) at VDD -VSS = VDD -VEE = 10V
Binary Address Decoding on Chip
5V, 10V, and 15V Parametric Ratings
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25 oC
Break-Before-Make Switching Eliminates Channel Overlap

Applications

Analog and Digital Multiplexing and Demultiplexing
A/D and D/A Conversion
Signal Gating CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V P-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a VDD -VEE of up to 13V can be controlled; for VDD -VEE level differences above 13V, a VDD -VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE = -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full V DD -VSS and VDD -VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw conﬁguration. When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

Ordering Information

TEMP. RANGE (oC) PACKAGE CD4051BF3A, CD4052BF3A, CD4053BF3A -55 to 125 16 Ld CERAMIC DIP CD4051BE, CD4052BE, CD4053BE -55 to 125 16 Ld PDIP CD4051BM, CD4051BMT, CD4051BM96 CD4052BM, CD4052BMT, CD4052BM96 CD4053BM, CD4053BMT, CD4053BM96 -55 to 125 16 Ld SOIC CD4051BNSR, CD4052BNSR, CD4053BNSR -55 to 125 16 Ld SOP CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR -55 to 125 16 Ld TSSOP August 1998 - Revised October 2003 [ /Title (CD405 1B, C D4052 B , C D4053 B ) /Sub- ject (CMOS A nalog M ulti- plex- ers/Dem ultiplex- ers with Logic Level C onver- sion) /Author /Key- w ords (Harris Semi- conduc- tor, C D4000

CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) TOP VIEW CD4052B (PDIP, CDIP, SOP, TSSOP) TOP VIEW CD4053B (PDIP, CDIP, SOP, TSSOP) TOP VIEW COM OUT/IN INH VSS VEE VDD A B C CHANNELS IN/OU T CHANNELS IN/OUT CHANNELS IN/OUT COMMON “Y” OUT/IN INH VSS VEE VDD COMMON “X” OUT/IN A B Y CHANNELS IN/OUT Y CHANNELS IN/OUT X CHANNELS IN/OUT X CHANNELS IN/OUT by bx cy OUT/IN CX OR CY IN/OUT CX INH VSS VEE VDD OUT/IN ax OR ay ay ax A B C OUT/IN bx OR by IN/OUT IN/OUT Functional Block Diagrams CD4051B A † B † C † INH † 134 2 5 1 12 15 14 TG TG TG TG TG TG TG TG COMMON OUT/IN 01234567 BINARY TO

1 OF 8

16 VDD

†All inputs are protected by standard CMOS protection network. CD4051B, CD4052B, CD4053B

Functional Block Diagrams (Continued) 1211 15 14 0123 3210 X CHANNELS IN/OUT Y CHANNELS IN/OUT BINARY TO

1 OF 4

10A † B † INH † VSS VEE VDD TG TG TG TG TG TG TG TG 4251 LOGIC LEVEL CONVERSION A † B † C † INH † 123 5 1 2 13 TG TG TG TG TG TG COMMON OUT/IN axaybxbycxcy 8 7VSS VEE

1 OF 2

†All inputs are protected by standard CMOS protection network. COMMON OUT/IN COMMON OUT/IN ax OR ay bx OR by cx OR cy CD4051B, CD4052B, CD4053B

“ON” CHANNEL(S)INHIBIT C B A CD4051B 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7

1 X X X None

0 0 0 0x, 0y 0 0 1 1x, 1y 0 1 0 2x, 2y 0 1 1 3x, 3y

1 X X None

1 X None

X = Don’t Care CD4051B, CD4052B, CD4053B

Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-) Operating Conditions Package Thermal Impedance,θJA (see Note 1): (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. Electrical SpeciﬁcationsCommon Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPL Y =±5V, AV = +1, R L = 100Ω , Unless Otherwise Speciﬁed (Note 3) PARAMETER CONDITIONS LIMITS AT INDICATED TEMPERATURES ( oC) UNITSVIS (V) V EE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX SIGNAL INPUTS (VIS) AND OUTPUTS (V OS ) Quiescent Device Current, IDD Max - - - 5 5 5 150 150 - 0.04 5 µA - - - 10 10 10 300 300 - 0.04 10 µA - - - 15 20 20 600 600 - 0.04 20 µA - - - 20 100 100 3000 3000 - 0.08 100 µA Drain to Source ON Resistance rON Max 0 ≤ VIS ≤ VDD - 0 0 5 800 850 1200 1300 - 470 1050 Ω - 0 0 10 310 330 520 550 - 180 400 Ω - 0 0 15 200 210 300 320 - 125 240 Ω Change in ON Resistance (Between Any Two Channels), ON OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max) -0 0 1 8 ± 100 (Note 2) ± 1000 (Note 2) - ± 0.01 ± 100 (Note 2) nA Capacitance: - -5 5- 5 Input, C IS ---- - 5 - p F Output, COS Feedthrough C IOS ---- - 0 . 2 - p F Propagation Delay Time (Signal Input to Output VDD R L = 200kΩ , C L = 50pF, tr, tf = 20ns 5 ---- -3 06 0n s 1 0---- -1 53 0n s 1 5---- -1 02 0n s CD4051B, CD4052B, CD4053B

CONTROL (ADDRESS OR INHIBIT), V C Input Low Voltage, VIL, Max VIL = VDD through 1kΩ ; VIH = VDD through 1kΩ V EE = VSS , R L = 1kΩ to VSS , IIS < 2µA on All OFF Channels 1 03333 - - 3 V 1 54444 - - 4 V Input High Voltage, V IH, Min 1 07777 7 - - V 15 11 11 11 11 11 - - V Input Current, I IN (Max) V IN = 0, 18 18 ± 0.1 ± 0.1 ± 1 ± 1- ± 10-5 ± 0.1 µA Propagation Delay Time: Address-to-Signal OUT (Channels ON or OFF) See Figures 10, 11, 14 t r, tf = 20ns, C L = 50pF, R L = 10kΩ 0 0 5 ---- - 4 5 0 7 2 0 n s 0 0 1 0---- - 1 6 0 3 2 0 n s 0 0 1 5---- - 1 2 0 2 4 0 n s - 5 0 5 ---- - 2 2 5 4 5 0 n s Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning ON) See Figure 11 t r, tf = 20ns, C L = 50pF, R L = 1kΩ 0 0 5 ---- - 4 0 0 7 2 0 n s 0 0 1 0---- - 1 6 0 3 2 0 n s 0 0 1 5---- - 1 2 0 2 4 0 n s - 1 00 5 ---- - 2 0 0 4 0 0 n s Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15 t r, tf = 20ns, C L = 50pF, R L = 10kΩ 0 0 5 ---- - 2 0 0 4 5 0 n s 0 0 1 0---- -9 0 2 1 0 n s 0 0 1 5---- -7 0 1 6 0 n s - 1 00 5 ---- - 1 3 0 3 0 0 n s Input Capacitance, C IN (Any Address or Inhibit Input) ---- - 5 7 . 5p F NOTE: 2. Determined by minimum feasible leakage measurement for automatic testing. Electrical Speciﬁcations PARAMETER TEST CONDITIONS LIMITS UNITSVIS (V) V DD (V) R L (kΩ ) TYP Cutoff (-3dB) Frequency Chan- nel ON (Sine Wave Input) 5 (Note 3) 10 1 V OS at Common OUT/IN CD4053 30 MHz VEE = VSS , CD4052 25 MHz CD4051 20 MHz VOS at Any Channel 60 MHz Electrical SpeciﬁcationsCommon Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPL Y =±5V, AV = +1, R L = 100Ω , Unless Otherwise Speciﬁed (Continued)(Note 3) PARAMETER CONDITIONS LIMITS AT INDICATED TEMPERATURES ( oC) UNITSVIS (V) V EE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX 20Log V OS V IS CD4051B, CD4052B, CD4053B

10 MHz

Peak-to-Peak voltage symmetrical about

FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL

FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING

4 C L

FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT FIGURE 19. INPUT CURRENT FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)

160 DIGITAL

unused inputs to either VDD or VSS . unused inputs to either VDD or VSS .

www.ti.com 22-Jul-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 7901502EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7901502EA CD4052BF3A 8101801EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8101801EA CD4053BF3A CD4051BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -55 to 125 CD4051BE CD4051BEE3 PREVIEW PDIP N 16 25 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CD4051BE CD4051BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4051BE CD4051BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4051BF CD4051BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4051BF3A CD4051BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4051BM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B

www.ti.com 22-Jul-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4051BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM051B CD4051BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B CD4052BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4052BE CD4052BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4052BE CD4052BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4052BF CD4052BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7901502EA CD4052BF3A CD4052BM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BMG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BMT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052B CD4052BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052B CD4052BPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B CD4052BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B

www.ti.com 22-Jul-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4052BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM052B CD4052BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CM052B CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B CD4053BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4053BE CD4053BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4053BE CD4053BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4053BF CD4053BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8101801EA CD4053BF3A CD4053BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4053BM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BMG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BMT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053B CD4053BPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B CD4053BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B

www.ti.com 22-Jul-2014 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4053BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM053B CD4053BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 CM053B CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 22-Jul-2014 Addendum-Page 5 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :

Catalog: CD4051B , CD4052B , CD4053B
Automotive: CD4051B-Q1 , CD4051B-Q1 , CD4053B-Q1 , CD4053B-Q1
Military: CD4051B-MIL , CD4052B-MIL , CD4053B-MIL NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4051BM96 SOIC D 16 2500 333.2 345.9 28.6 CD4051BM96 SOIC D 16 2500 364.0 364.0 27.0 CD4051BM96 SOIC D 16 2500 367.0 367.0 38.0 CD4051BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4051BM96G4 SOIC D 16 2500 367.0 367.0 38.0 CD4051BM96G4 SOIC D 16 2500 333.2 345.9 28.6 CD4051BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4051BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD4052BM96 SOIC D 16 2500 333.2 345.9 28.6 CD4052BM96 SOIC D 16 2500 364.0 364.0 27.0 CD4052BM96G3 SOIC D 16 2500 364.0 364.0 27.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4052BM96G4 SOIC D 16 2500 333.2 345.9 28.6 CD4052BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4052BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 CD4052BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD4053BM96 SOIC D 16 2500 333.2 345.9 28.6 CD4053BM96 SOIC D 16 2500 364.0 364.0 27.0 CD4053BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4053BM96G4 SOIC D 16 2500 333.2 345.9 28.6 CD4053BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4053BPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4053BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 CD4053BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 3

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Product Information

SCHS047G specifications and overview.

Summary

Data sheet acquired from Harris Semiconductor

Description

Data sheet acquired from Harris Semiconductor

Source title SCHS047G Datasheet(PDF) - Texas Instruments

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