SCG9800

SCG9800 ETC1 | Alldatasheet

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SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 1 Sept 2000 SCG9800 Microcontroller Specification FEATURE SUMMARY Technology − CMOS technology. CPU − 8-bit CPU core. − 128 powerful and easy-to-use instruction set. Memory − Internal RAM: 240 x 8 − Memory is organized as 16K-byte page. − External memory access of up to 1M x 8, can be both ROM and RAM. I/O Structure − Memory mapped I/O structure. Oscillation Frequency − RC Oscillator for the main system clock up to 4MHz, instruction cycle ~0.5us. − Subsystem clock frequency of 32.768kHz for real time timer. Power Down − Stop mode (stop main and subsystem clock to core) − Sleep mode (stop main system clock only) Interrupts − 2 timer interrupts. − 1 real time interrupt. − 1 external event interrupt. − 1 software interrupt. I/O Ports − 1 8-bit programmable I/O port. − 1 2-bit output port. Timer − 2 8-bit pre-scalar auto reload timers which can be cascaded to form one 16-bit timer. − 1 real time timer. − 1 watch dog timer. Operating Voltage − 2.4V to 5.5V.

and will have an extra byte for some addressing modes. Register (iPAGE), it becomes a 20-bit address that can access up to 1,048,576 bytes. incremented to the next instruction after an instruction fetch. Table 1. Different types of interrupt bits are always set to zero. significant two bits are always set to zero. An 8-bit Accumulator is used for arithmetic, logical and data movement operation. An 8-bit temporarily storage is used for accumulator.

stack frame starts from the highest address memory location. ALU operations and instruction execution sequences. Figure 3. 8-bit Program Status carry flag is set to 1. Otherwise, it is cleared to 0. is a bit shifted out of the specified source operand. Executing single instruction of “SETC” or “CLRC” can also alter this flag. Upon returning from an interrupt service routine, this flag will be restored. zero flag will also be set to 1 if the content of the source operand is zero. Upon returning from an interrupt service routine, this flag will be restored. This flag will also be restored upon returning from an interrupt service routine.

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 5 Sept 2000 Interrupt Mask Flag (I) The flag will be set to 1 when entering an interrupt service routine. By that time, all other interrupt events will be pending. After exiting from the interrupt service routine, this interrupt mask flag will be cleared to 0. Then interrupt handling will be resumed. Memory By connecting PAD_EXT_ADDR to HIGH, external memory access of 512K bytes is allowed. In addition, setting bit5 of the internal register TCONG will expand memory access to another 512K bytes. This extra external memory block can be RAM or ROM. For this ROM-less chip, memory is arranged in 16K-byte page size each. Therefore, there can have 32 pages for 512K bytes of memory space. Regarding the instruction pointer, it is organized as iPAGE:PC for instruction fetch. Change of program flow between pages is by modifying the PAGE register and then followed by executing a JMP or CALL instruction. These two instructions will load the PAGE register to iPAGE and change the content in PC for long JMP or CALL instruction. It does not need to change the PAGE register if it is a short JMP/CALL (i.e. JMP/CALL within page) because the PAGE register is normally the same as the iPAGE register. To exit a subroutine, long or short return type must be specified for long or short CALL respectively. The microcontroller has 240 bytes internal RAM data storage of address $10-$FF. This area includes stack frame and data memory. The stack frame is usually initialized at the highest RAM address location, i.e. $FF. Oscillation Circuits Main system and subsystem oscillation circuitry generates the internal clock signal for the CPU and other hardware timings. The main system clock uses the RC oscillation source. The operating frequency is up to 4 MHz. This clock is for the CPU and the two timers. The subsystem clock is for the real time signals. It uses a 32.768 kHz crystal. It has to be tied to a voltage level, either HIGH or LOW, if the real time timer and the watch dog timer are not used. Power Down The microcontroller supports power down mode for saving power. Executing a STOP instruction will stop both main system and subsystem clock to the core to save most of the microcontroller power. To enter sleep mode, execute a SLEEP instruction will stop the system clock only. Only an external interrupt will release the microcontroller from STOP mode if external interrupt enable bit is set to 1. For SLEEP mode, the microcontroller will be awoken every 0.5 sec or by the external interrupt if corresponding enable bit is set to 1.

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 6 Sept 2000 Interrupts The MICROCONTROLLER has 2 timer interrupts, one real time interrupt, one external event interrupt and one software interrupt. When interrupt occurs, the content of PC, iPAGE and PS are pushed onto the stack in sequence. And then, the corresponding interrupt vector is loaded into iPAGE:PC. Upon executing a RTI instruction, the registers are popped out of the stack in the reversed order. The preference of interrupt priority is Timer 0 / RTC interrupt, Timer 1 interrupt and then external interrupt. I/O Ports The microcontroller has one 2-bit output port and one software-controllable 8-bit I/O port. For I/O port 0, there is a pull-low resistor when it is configured in input mode, and this resistor is disabled when it is in output mode. For Port 5, it is a 2-bit output port only. Remark: Port 4 bit3 can be an output if the chip is not configured as 8M bits external memory access via setting bit6 of the internal register TCONG. Timers The microcontroller has two programmable 8-bit timers (T0 and T1) for system timing. It has also a real time timer and a watch dog timer when subsystem clock is employed. All the timers can be enabled or disabled by configuring an internal register, TCONG. At CPU resets, all of them are disabled. T0 and T1 are up-counters and can be configured as either two 8-bit pre-scalar auto reload timer or as a 16-bit pre-scalar auto reload timer. The timer overflow flag will be set if the timer overflows. Then an interrupt will be generated if the corresponding interrupt enable bit is set to 1. The real time timer provides 0.5 sec interrupt for RTC functions. Watch dog timer will overflow in ~1 sec and then will reset the CPU.

Figure 4. Block diagram of SCG9800

Table 2. Pin Description

1 A0 O/P Address bus Pad type 2

2 A1 O/P Address bus Pad type 2

3 A2 O/P Address bus Pad type 2

4 A3 O/P Address bus Pad type 2

5 A4 O/P Address bus Pad type 2

6 A5 O/P Address bus Pad type 2

7 A6 O/P Address bus Pad type 2

8 A7 O/P Address bus Pad type 2

9 VDD Power Supply Voltage

10 VSS Power Ground

11 D0 I/O Data bus Pad type 1

12 D1 I/O Data bus Pad type 1

13 D2 I/O Data bus Pad type 1

14 D3 I/O Data bus Pad type 1

15 D4 I/O Data bus Pad type 1

16 D5 I/O Data bus Pad type 1

17 D6 I/O Data bus Pad type 1

18 D7 I/O Data bus Pad type 1

19 P50 O/P Port 5 Pad type 2

20 P51 O/P Port 5 Pad type 2

23 P00 I/O Port 0 Pad type 1

24 P01 I/O Port 0 Pad type 1

25 P02 I/O Port 0 Pad type 1

26 VDD Power Supply Voltage

27 VSS Power Ground

28 P03 I/O Port 0 Pad type 1

29 P04 I/O Port 0 Pad type 1

30 P05 I/O Port 0 Pad type 1

31 P06 I/O Port 0 Pad type 1

32 P07 I/O Port 0 Pad type 1

33 EXT_ADDR I/P External address Pad type 4

34 TEST_ROM I/P Test pin, no connection Pad type 4

35 VSS Power Ground

36 VDD Power Supply Voltage

37 RESET I/P Reset pin Pad type 3

38 EXT_INT I/P External Interrupt pin Pad type 4

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 9 Sept 2000 Pin Name Type Description Pad Type 40 CLK320 O/P 32.768KHz RTC Pad type 6

41 TEST I/P Test pin, no connection Pad type 4

42 P_CLK_0 O/P RC oscillator output Pad type 6

43 P_CLK I/P RC oscillator for the main system clock Pad type 5

44 A15 I/O Address bus Pad type 1

45 A14 I/O Address bus Pad type 1

46 A13 I/O Address bus Pad type 1

47 A12 I/O Address bus Pad type 1

48 A11 I/O Address bus Pad type 1

49 A10 I/O Address bus Pad type 1

50 A9 I/O Address bus Pad type 1

51 A8 I/O Address bus Pad type 1

52 VSS Power Ground

53 VDD Power Supply Voltage

54 CS2 O/P Chip select 2 Pad type 2

55 CS1 O/P Chip select 1 Pad type 2

56 WR O/P Write signal Pad type 2

57 RD O/P Read signal Pad type 2

58 P43/A19 O/P Port 4 bit3/ Address bus bit19 Pad type 2

59 A18 O/P Address bus Pad type 2

60 A17 O/P Address bus Pad type 2

61 A16 O/P Address bus Pad type 2

Figure 15. Timer Configuration Port

Figure 18. Timer 0 and Timer 1 Preset Value Register

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 17 Sept 2000 INSTRUCTION SUMMARY There are 128 instructions. All instructions are one or two byte instructions. The followings are the notations used: A Accumulator B B Register CC a r r y b i t Z Zero bit N Negative bit X X Index Register Y Y Index Register SP Stack Pointer Register (SP) Stack BANK Data Bank Register PAGE Page Register iPAGE The page register for PC19-PC14 PC Program Counter PC13-0 PS Program Status I Interrupt flag (X) RAM pointed by X (Y) RAM pointed by Y label A 8-bit RAM/Register label (label) RAM pointed by the label ADDR14 A 14-bit address ADDR 8 A 8-bit address #CONSTANT A 8-bit constant

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 18 Sept 2000 INSTRUCTION SET 1. ADC A Code 0100 0000 Operation A + A + C→ A Flags N, Z, C 2. ADC X Code 0100 0010 Operation X + A + C→ A Flags N, Z, C 3. ADC Y Code 0100 0011 Operation Y + A + C→ A Flags N, Z, C 4. ADC (X) Code 0100 0110 Operation (X) + A + C→ A Flags N, Z, C 5. ADC (Y) Code 0100 0111 Operation (Y) + A + C→ A Flags N, Z, C 6. ADC label Code 0100 0100 zzzz zzzz Operation (zzzz zzzz)+A+C→ A Flags N, Z, C 7. ADC #CONSTANT Code 0100 0001 zzzz zzzz Operation Zzzz zzzz +A+C→ A Flags N, Z, C 8. AND A Code 0100 1000 Operation A Λ A→ A Flags N,Z 9. AND X Code 0100 1010 Operation X Λ A→ A Flags N,Z 10. AND Y Code 0100 1011 Operation Y Λ A→ A Flags N,Z 11. AND (X) Code 0100 1110 Operation (X) Λ A→ A Flags N,Z 12. AND (Y) Code 0100 1111 Operation (Y) Λ A→ A Flags N,Z 13. AND label Code 0100 1100 zzzz zzzz Operation (zzzz zzzz)Λ A→ A Flags N,Z 14. AND #CONSTANT Code 0100 1001 zzzz zzzz Operation Zzzz zzzz Λ A → A Flags N,Z 15. BRA ADDR8 Code 0011 0010 zzzz zzzz Operation Zzzz zzzz → PC0-7 Flags -----

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 19 Sept 2000 16. CALL ADDR14 Code 11zz zzzz zzzz zzzz Operation PC → (SP);SP-2→ SP ADDR14 → PC[13:0] If PAGE ≠ iPAGE IPAGE→ (SP);SP-1→ SP PAGE → iPAGE Flags ----- 17. CLR A Code 0010 1000 Operation 0 → A Flags N,Z 18. CLR X Code 0010 1010 Operation 0 → X Flags ----- 19. CLR Y Code 0010 1011 Operation 0 → Y Flags ----- 20. CLR (X) Code 0010 1110 Operation 0 → (X) Flags ----- 21. CLR (Y) Code 0010 1111 Operation 0 → (Y) Flags ----- 22. CLR label Code 0010 1100 Operation 0 → (zzzz zzzz) Flags ----- 23. CLRC Code 0110 0001 Operation 0 → C Flags C 24. CMP Code 0000 0001 zzzz zzzz Operation A ∀ zzzz zzzz Flags Z 25. CMP label Code 0000 0101 zzzz zzzz Operation A ∀ (zzzz zzzz) Flags Z 26. CPMX #CONSTANT Code 0000 1001 zzzz zzzz Operation (X) ∀ zzzz zzzz Flags Z 27. CPMX label Code 0000 1101 zzzz zzzz Operation (X) ∀ zzzz zzzz Flags Z 28. CPX #CONSTANT Code 0001 0001 zzzz zzzz Operation X ∀ zzzz zzzz Flags Z 29. CPX label Code 0001 0101 zzzz zzzz Operation X ∀ (zzzz zzzz) Flags Z 30. CPY #CONSTANT Code 0001 1001 zzzz zzzz Operation Y ∀ zzzz zzzz Flags Z 31. CPY label Code 0001 1101 zzzz zzzz Operation Y ∀ (zzzz zzzz) Flags Z

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 20 Sept 2000 32. DEC A Code 0110 1000 Operation A – 1 → A Flags N, Z, C 33. DEC X Code 0110 1010 Operation X – 1 → X Flags N, Z, C 34. DEC Y Code 0110 1011 Operation Y – 1 → Y Flags N, Z, C 35. DEC (X) Code 0110 1110 Operation (X) – 1 → (X) Flags N, Z, C 36. DEC (Y) Code 0110 1111 Operation (Y) – 1 → (Y) Flags N, Z, C 37. DEC label Code 0110 1100 zzzz zzzz Operation (zzzz zzzz)-1 → (zzzzzzzz) Flags N, Z, C 38. EOR X Code 0101 1010 Operation X ∀ A → A Flags N, Z 39. EOR Y Code 0101 1011 Operation Y ∀ A → A Flags N, Z 40. EOR (X) Code 0101 1110 Operation (X) ∀ A → A Flags N, Z 41. EOR (Y) Code 0101 1111 Operation (Y) ∀ A → A Flags N, Z 42. EOR label Code 0101 1100 zzzz zzzz Operation (zzzz zzzz)∀ A → A Flags N, Z 43. EOR #CONSTANT Code 0101 1001 zzzz zzzz Operation zzzz zzzz ∀ A → A Flags N, Z 44. INC A Code 0110 0000 Operation A + 1 → A Flags N, Z, C 45. INC X Code 0110 0010 Operation X + 1 → X Flags N, Z, C 46. INC Y Code 0110 0011 Operation Y + 1 → Y Flags N, Z, C 47. INC (X) Code 0110 0110 Operation (X) + 1 → X Flags N, Z, C 48. INC (Y) Code 0110 0111 Operation (Y) + 1 → Y Flags N, Z, C

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 21 Sept 2000 49. INC label Code 0110 0100 zzzz zzzz Operation (zzzz zzzz) + 1 → (zzzz zzzz) Flags N, Z, C 50. INT Code 0011 0110 Operation PC LOW → (SP), SP-1 → SP PCHIGH→ (SP), SP-1 → SP IPAGE → (SP), SP-1 → SP PS → (SP), SP-1 → SP 1 → I 3FC0H → PC 3 → iPAGE,PAGE Flags I 51. JA Code 0111 0001 Operation A → PC[7:0] Flags ----- 52. JUMP ADDR14 Code 10zz zzzz zzzz zzzz Operation ADDR14 → PC[13:0] If PAGE≠iPAGE PAGE → iPAGE Flags ----- 53. MOV A, X Code 0000 0010 Operation A → X Flags ----- 54. MOV A, Y Code 0000 0011 Operation A → Y Flags ----- 55. MOV A, (X) Code 0000 0110 Operation A → (X) Flags ----- 56. MOV A, (Y) Code 0000 0111 Operation A → (Y) Flags ----- 57. MOV A label Code 0000 0100 zzzz zzzz Operation A → (zzzz zzzz) Flags ----- 58. MOV X, A Code 0001 0000 Operation X → A Flags N, Z 59. MOV X, Y Code 0001 0011 Operation X → Y Flags ----- 60. MOV X, (Y) Code 0001 0111 Operation X → (Y) Flags ----- 61. MOV X, label Code 0001 0100 zzzz zzzz Operation X → (zzzz zzzz) Flags ----- 62. MOV Y, A Code 0001 1000 Operation Y → A Flags N, Z

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 22 Sept 2000 63. MOV Y, X Code 0001 1010 Operation Y → X Flags ----- 64. MOV Y, (X) Code 0001 1110 Operation Y → (X) Flags ----- 65. MOV Y, label Code 0001 1100 zzzz zzzz Operation Y → (zzzz zzzz) Flags ----- 66. MOV (X), A Code 0011 0000 Operation (X) → A Flags N, Z 67. MOV (X), Y Code 0011 0011 Operation (X) → Y Flags ----- 68. MOV (X), (Y) Code 0011 0111 Operation (X) → (Y) Flags ----- 69. MOV (X), label Code 0011 0100 zzzz zzzz Operation (X) → (zzzz zzzz) Flags ----- 70. MOV (Y), A Code 0011 1000 Operation (Y) → A Flags N, Z 71. MOV (Y), X Code 0011 1010 Operation (Y) → X Flags ----- 72. MOV (Y), (X) Code 0011 1110 Operation (Y) → (X) Flags ----- 73. MOV (Y), label Code 0011 1100 zzzz zzzz Operation (Y) → (zzzz zzzz) Flags ----- 74. MOV label, A Code 0010 0000 zzzz zzzz Operation (zzzz zzzz) → A Flags N, Z 75. MOV label, X Code 0010 0010 zzzz zzzz Operation (zzzz zzzz) → X Flags ----- 76. MOV label, Y Code 0010 0011 zzzz zzzz Operation (zzzz zzzz) → Y Flags ----- 77. MOV label, (X) Code 0010 0110 zzzz zzzz Operation (zzzz zzzz) → (X) Flags ----- 78. MOV label, (Y) Code 0010 0111 zzzz zzzz Operation (zzzz zzzz) → (Y) Flags ----- 79. MOV #CONSTANT, A Code 0000 1000 zzzz zzzz Operation Zzzz zzzz → A Flags N, Z

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 23 Sept 2000 80. MOV #CONSTANT, X Code 0000 1010 zzzz zzzz Operation Zzzz zzzz → X Flags ----- 81. MOV #CONSTANT, Y Code 0000 1011 zzzz zzzz Operation Zzzz zzzz → Y Flags ----- 82. MOV #CONSTANT, (X) Code 0000 1110 zzzz zzzz Operation Zzzz zzzz → (X) Flags ----- 83. MOV #CONSTANT, (Y) Code 0000 1111 zzzz zzzz Operation zzzz zzzz → (Y) Flags ----- 84. NOP Code 0000 0000 Operation No operation Flags ----- 85. OR X Code 0101 0010 Operation X V A→ A Flags N, Z 86. OR Y Code 0101 0011 Operation Y V A→ A Flags N, Z 87. OR (X) Code 0101 0110 Operation (X) V A→ A Flags N, Z 88. OR (Y) Code 0101 0111 Operation (Y) V A→ A Flags N, Z 89. OR label Code 0101 0100 zzzz zzzz Operation (zzzz zzzz)V A→ A Flags N, Z 90. OR #CONSTANT Code 0101 0001 zzzz zzzz Operation Zzzz zzzzV A→ A Flags N, Z 91. POP Code 0011 1111 Operation SP+1→ SP (SP)→ A Flags ----- 92. PSHPAGE Code 0110 1101 Operation PAGE→ (SP); SP-1→ SP Flags ----- 93. PUSH Code 0110 1001 Operation A→ (SP),SP-1→ SP Flags ----- 94. ROL A Code 0111 0000 Operation C← A← C Flags N, Z, C 95. ROL X Code 0111 0010 Operation C← X← C Flags N, Z, C 96. ROL Y Code 0111 0011 Operation C← Y← C Flags N, Z, C

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 24 Sept 2000 97. ROL (X) Code 0111 0110 Operation C← (X)← C Flags N, Z, C 98. ROL (Y) Code 0111 0111 Operation C← (Y)← C Flags N, Z, C 99. ROL label Code 0111 0100 zzzz zzzz Operation C← (zzzz zzzz)← C Flags N, Z, C 100. ROM A Code 0111 1101 Operation ROM (BANK,X,A)→ A Flags ----- 101. ROM Y Code 0111 1001 Operation ROM (BANK,X,Y)→ A Flags ----- 102. ROMDBL Code 0001 1001 Operation ROM (BANK,X,Y)→ B ROM (BANK,X,Y+1)→ A Flags ----- 103. ROR A Code 0111 1000 Operation C ¡ A¡ C Flags N, Z, C 104. ROR X Code 0111 1010 Operation C→ X→ C Flags N, Z, C 105. ROR Y Code 0111 1011 Operation C→ Y→ C Flags N, Z, C 106. ROR (X) Code 0111 1110 Operation C→ (X)→ C Flags N, Z, C 107. ROR (Y) Code 0111 1111 Operation C→ (Y)→ C Flags N, Z, C 108. ROR label Code 0111 1100 zzzz zzzz Operation C→ (zzzz zzzz)→ C Flags N, Z, C 109. RTI Code 0100 0101 Operation SP+1→ SP (SP)→ PS;SP+1→ 1 (SP)→ IPAGE,PAGE; SP+1→ SP (SP)¡ PCHIGH; SP+1¡ SP (SP)→ PCLOW Flags ----- 110. RTL Code 0100 1101 Operation SP+1→ SP (SP)→ iPAGE,PAGE; SP+1→ SP (SP)→ PCHIGH SP+1→ SP (SP)→ PCLOW Flags ----- 111. RTS Code 0101 0101 Operation SP+1→ SP (SP)→ PCHIGH; SP+1→ SP (SP)→ PCLOW Flags -----

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 25 Sept 2000 112. SETC Code 0110 0101 Operation 1→ C Flags C 113. SETZ Code 0101 1000 Operation 1→ Z,0→ A, Flags N, Z 114. SKIPC Code 0011 0001 Operation PC+2→ PC if C = 1 Flags ----- 115. SKIPMI Code 0001 0110 Operation PC+2→ PC if N = 1 Flags ----- 116. SKIPNC Code 0011 1001 Operation PC+2→ PC if C = 0 Flags ----- 117. SKIPNZ Code 0010 1001 Operation PC+2→ PC if Z = 0 Flags ----- 118. SKIPPL Code 0001 1111 Operation PC+2→ PC if N = 0 Flags ----- 119. SKIPZ Code 0010 0001 Operation PC+2→ PC if Z = 1 Flags ----- 120. SLEEP Code 0000 1100 Operation Sleep Flags ----- 121. STOP Code 0010 0100 Operation Stop 122. TAPAGE Code 0011 1 0101 Operation A→ PAGE Flags ----- 123. TZ Code 0101 0000 Operation Z=1 if A = 0 Z=0 if A ≠ 0 Flags N, Z 124. WRITE Code 0101 1101 Operation A→ (BANK,X,Y) Flags ----- 125. XB Code 0010 0101 Operation B ↔ A Flags ----- 126. XBANK Code 0011 0101 Operation BANK ↔ A Flags ----- 127. XSP Code 0011 1101 Operation SP ↔ A Flags ----- 128. XST Code 0010 1101 Operation PS ↔ A Flags N, Z, C, I

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 26 Sept 2000

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings: 1. VDD 7.0V 2. VIH VDD + 0.3V 3. VIL VSS - 0.3V 4. Operating Temperature 0 °C to + 60°C 5. Storage Temperature -50 °C to + 150°C Recommended Operating: MIN TYP MAX Unit 1. Operating Voltage (VDD) 2.4 3.0 5.5 V 2. Operating Frequency (Fosc) - 4.0 - MHz 3. Input Voltage VIL 0 0.4 0.8 V VIL 0 0.6 1.0 V VIL 0 1.5 1.8V V 4. Output Voltage 4.1 VDD = 2.4V VOH 2.0 - - V @1mA VOL - - 0.4 V 4.2 VDD = 3.0V VOH 2.4 - - V @2mA VOL - - 0.6 V 4.3 VDD = 5.5V VOH 4.0 - - V @10mA VOL - - 1.5 V 5. Input Current V I H = V D D I H --0 . 3 µA (P0, P1 and P3) - - 150 µA (P0 only via internal pull-low resistor) VIL = OV IL - - 0.3 µA (leakage) 6. Output Current IOL@VOL =0.4V 2.0 3.0 - mA IOL@VOL =0.6V 3.0 7.0 - mA 6.3 VDD = 5.5V, IOH@VOH =4.0V 8 10 - mA IOL@VOL =1.5V 16 20 - mA 7. Current Dissipation 7.1 Operating Current @4MHz, 3.0V & Output Pad Load = 50pF 1.0 1.5 4.5 mA & Output Pad Load = 50pF 7.3 Standby Current (OFF mode) - 1.0 9.0 µA

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 27 Sept 2000 PAD Co-ordinates

61 A16

60 A17

59 A18

58 P43/A19

9 VDD

52 VSS

10 VSS

(0,0) 50 A9 12 D1

49 A10

48 A11

47 A12

46 A13

45 A14

44 A15

19 P50

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P51 P00 P01 P02 VDD VSS P03 P04 P05 P06 P07 EXT_ADDR TEST_ROM VSS VDD RESET- EXT_INT CLK32I CLK32O TEST P_CLK_O P_CLK The substrate of IC should be connected to VSS

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 28 Sept 2000 Pad No Pad Name X Y Pad No Pad Name X Y 1 A0 -1773.100 1127.050 41 TEST 1496.500 -1722.550 2 A1 -1773.100 987.050 42 P_CLK_0 1636.500 -1722.550 3 A2 -1773.100 847.050 43 P_CLK 1776.500 -1722.550 4 A3 -1773.100 707.050 44 A15 1766.900 -746.700 5 A4 -1773.100 567.050 45 A14 1766.900 -606.700 6 A5 -1773.100 427.050 46 A13 1766.900 -466.700 7 A6 -1773.100 287.050 47 A12 1766.900 -326.700 8 A7 -1773.100 147.050 48 A11 1766.900 -186.700 9 VDD -1773.100 7.050 49 A10 1766.900 -46.700 10 VSS -1773.100 -132.950 50 A9 1766.900 93.300 11 D0 -1773.100 -272.950 51 A8 1766.900 233.300 12 D1 -1773.100 -412.950 52 VSS 1766.900 373.300 13 D2 -1773.100 -552.950 53 VDD 1766.900 513.300 14 D3 -1773.100 -692.950 54 CS2 1766.900 653.300 15 D4 -1773.100 -832.950 55 CS1 1766.900 793.300 16 D5 -1773.100 -972.950 56 WR 1766.900 933.300 17 D6 -1773.100 -1112.950 57 RD 1766.900 1073.300 18 D7 -1773.100 -1252.950 58 P43/A19 1766.900 1213.300 19 P50 -1773.100 -1512.950 59 A18 1766.900 1353.300 20 P51 -1563.500 -1722.550 60 A17 1766.900 1493.300 21 - - - 61 A16 1766.900 1633.300 22 - - - 23 P00 -1143.500 -1722.550 24 P01 -1003.500 -1722.550 25 P02 -863.500 -1722.550 26 VDD -723.500 -1722.550 27 VSS -583.500 -1722.550 28 P03 -443.500 -1722.550 29 P04 -303.500 -1722.550 30 P05 -163.500 -1722.550 31 P06 -23.500 -1722.550 32 P07 116.500 -1722.550 33 EXT_ADDR 256.500 -1722.550 34 TEST_ROM 396.500 -1722.550 35 VSS 656.500 -1722.550 36 VDD 796.500 -1722.550 37 RESET 936.500 -1722.550 38 EXT_INT 1076.500 -1722.550 39 CLK32I 1216.500 -1722.550 40 CLK320 1356.500 -1722.550

SCG9800 8-BIT MICROCONTROLLER Score Concept Semiconductor Ltd. 29 Sept 2000 Application Circuit SCG9800 1 SCG9800 application circuit A 11Saturday, September 16, 2000 Title Size Document Number Rev Date: Sheet of VCC VCC OPTIONAL OPTIONAL SCORE CONCEPT SEMICONDUCTOR LIMITED A10 A11 A12 A13 A14 A15 A16 A17 A18 RD- D7A7 P5W0 P5W1 WR- CS1- CS2- A10 A11 A12 A13 A14 A15 RD- RESET- A16 A17 A18 P43/A19 C1 C2 27C040 A012 A111 A210 A39 A48 A57 A66 A75 A827 A926 A1023 A1125 A124 A1328 A1429 A153 A162 CE22 OE24 O0 13 O1 14 O2 15 O3 17 O4 18 O5 19 O6 20 O7 21 A1730 A1831 22p 100K 32768R3 47K 0.1u LED LED LED LED SCG9800 A7 8 VDD9 A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 GND10 D011 D112 D213 D314 D415 D516 D617 D718 P5019 P5120 P0023 P0124 P0225 VDD26 GND27 P0328 P0429 P0530 P0631 P0732 EXT_ADDR33 TEST_ROM34 GND35 VDD36 RESET37 EXT_INT38 CLK32I39 CLK32O40 TEST 41P_CLK_O 42P_CLK 43A15 44A14 45A13 46A12 47A11 48A10 49A9 50A8 51GND 52VDD 53CS2 54CS1 55WR 56 RD 57 P43/A1958 A18 59 A17 60 A16 61