SCB68171

SCB68171 ETC | Alldatasheet

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Very Little Serial Interface Chip Preliminary Specification Microprocessor Products DESCRIPTION FEATURES PIN CONFIGURATION The Signetics Very Little Serial Interface © 70mA open-collector drive for Chip (VLSIC) is a bipolar interface de- © SERDATN vice which connects one or more Low capacitive loading concur [if PB} Voc sol I prowdos us ving andrecoving * Dieeriminates SERCLK Into om — in addition to latching data in both the. *ingle-phase chip clock output xstanty (a ba) svocux transmit and receive directions. © Separates data and start bits for both receive and transmit xbatan [6] [2] srsResern SERCLK on the VMSbus has a wave- ¢ provides single bus load for RESETOON [I Fi] sencux form as shown in Figure 1, with four — muitiple VMSbus controllers ReseTON [7] [35] seRDATN edges per cycle which are designated, simplifies controller design and ono [H Fry erscuxo C1, $1, C2, $2. SYSCLK is used to ~ Siows use of slower tech discriminate (differentiate) the phases of nology oP View SERCLK. The SYSCLK input should VMEbus receiver for SYSCLK ‘coves have a nominal 50% duty cycle and a © VMEbus driver/recelver for cycle time which is 2/11 that of | SYSRESETN SERCLK, but SYSCLK and SERCLK 16-pin DIP need not be synchronous or have any fixed phase relationship. The 16MHz ORDERING INFORMATION requirements for a back plane 29MHz | — = Voo BY 25% ‘The VLSIC samples the XDATAN input on the SERCLK edge designated C1. XDATAN is clocked directly to SER- DATN. The VLSIC then clocks the low- active OR (positive logic AND) of SER- DATN and SERDATIN to RDATAN on the S1 edge. if XDATAN was high at C1, the VLSIC then samples the XSTARTN input on the C2 edge, and if it is low, the VLSIC makes SERDATN low, thus mak- ing a VMSbus start bit. If XDATAN was high at S1, then on the S2 edge it clocks the low active OR of SERDATN and SERDATIN to RSTARTN. If SERDATN was low at S1, it keeps (or makes) RSTARTN high at S2. CHIPCLK is driven high from the C1 edge of SERCLK, and driven low from the C2 edge. Thus RDATAN and RSTARTN setup to CHIPCLK edges by approximately the low time of SERCLK. ‘The VMSbus controller(s) must meet the specified setup and hold times to C1 for XDATAN and to C2 for XSTARTN. dune 15, 1986 2-499

Signetics Microprocessor Products Preliminary Specification Se ee eee eee Very Little Serial Interface Chip (VLSIC) SCB68174 DESCRIPTION (Continued) XSTARTN low, and CHIPCLK high directly mous function of driving and receiving SYS- A VMSbus controller is required to "jam" the sets the flipflop controlling SERDATN, and RESETN on the VMEbus. A low on the ‘ous by sending a string of "ones" (low) on makes SERDATN low. (Note that a VMSbus RESETIN input makes the VLSIC drive the SERDATN when a start bit is sensed while controller would never assert both XDATAN SYSRESETN pin low. SYSRESETN is also the controller is sending or tracking a frame. and XSTARTN low in normal operation.) The received and driven onto two open-collector The first one bit should directly follow the assertion of both XDATAN and XSTARTN outputs RESETOIN and RESETO2N. RE- misplaced start bit. Since the minimum S2-to- must occur soon enough to satisfy the SER- SETO1N has a high drive capability and is C1 time of SERCLK (25ns) is less than the DATN to S1 setup requirements of all the suitable for connection to the RESETN pin of sum of the maximum S2-to-RSTART-low time modules on the VMSbus. a 680x0 processor, while RESETO2N has plus the minimum setup of XDATAN to C1, a sarily j ‘ lower drive and capacitance and can be controller cannot do this using XDATAN in Tne VLSIC poplar aioe elie connected to the processor's HALTN pin. the normal fashion. SBD Ot SP This function has no connection to the rest of functionality is at a premium in this area. to vigio. and could thus be used for some The following feature is provided to solve this Accordingly, the VLSIG includes an autono- ih problem. The condition XDATAN low, other purpose. PIN DESCRIPTION | mwewone | Ra | | NAME AND FUNCTION SERCLK 11 |_| | Direct connect to VMSbus clock: Clocks SERDATN to RDATAN, RSTARTN. Clocks XDATAN, XSTARTN to SERDATN. Used to generate single-phase CHIPCLK. SYSCLK 13 | 1 | Direct connect to VMEbus clock or other signal meeting the specified frequency relationship to SERCLK: Used to discriminate the phases of SERCLK. SYSCLKO 9 | © | Repeater of SYSCLK for onboard use. SERDATN | 10 | 1/0 | Direct connect to VMSbus data in bipolar open-collector links: Provides data output function for other types of links (e.g. optical). Requires pull-up resistor in either case. SERDATIN | 15 | 1 | Tied to high logic level in bipolar open-collector links: Provides data input function for other types of links (e.g. optical). CHIPCLK 1 | © | Single phase clock for VMSbus controllers. RDATAN 3 | © | Conveys one/zero bits to VMSbus controtler(s). RSTARTN | 2 | O | Conveys start bits to VMSbus controller(s). XDATAN 5 | 1 | Input from VMSbus controller(s): In normal operation, a low on this line indicates a "one" bit should be ! sent. Simultaneous assertion of XDATAN and XSTARTN low, while CHIPCLK is high, drives SERDATN low directly in a "jam" condition XSTARTN 4 | 1 | Input from VMSbus controller(s): In normal operation, a low on this line indicates a "'start" bit should be sent. Simultaneous assertion of XDATAN and XSTARTN low, while CHIPCLK is high, drives SERDATN low directly in a "jam" condition. RESETIN 14 | 1 | Input from onboard logic: Low state forces SYSRESETN low. SYSRESETN| 12 | 1/0 | Direct connect to VMEbus system reset: Open-collector output from RESETIN, received to drive RESETOIN and RESETO2N. Does not affect other VLSIC logic. RESETOIN | 7 | O | High-drive open-collector output from SYSRESETN. RESETO2ZN | 6 | O | Low-drive open-collector output from SYSRESETN. Voc 16 +5 Volts GND 8 Ground VMSBUS CONTROLLER DESIGN CHIPCLK, and may release XSTARTN to 4. If two VMSbus controllers connected to Controllers using VLSIC should signal as high in response to the falling edge. the same VLSIC become "locally desyn- follows on XDATAN and XSTARTN. Since these are typically open-collector chronized’’, it is possible that one will act bt outputs of the controllers, there may be a present XDATAN low and the other ' Contrliers should oe a he taling age timing advantage to do so. XSTARTN low for the same bit cell If this of CHIPCLK, and on XSTARTN in re- 3. A controller should present XDATAN and ‘occurs, XDATAN predominates and SER- sponse to the rising edge of CHIPCLK. XSTARTN low in a "jam" situation, in a DATN is driven low for a "'one" bit. Thus For a 2.9MHz SERCLK, they have at combinatorial fashion from RSTARTN. @ possible transient combination of XDA- least 90nsec to do so, and approximately Thereafter the controller can release TAN and XSTARTN low and CHIPCLK 420nsec from RDATAN valid. XSTARTN from the lowgoing edge of high actually nas re eifect The controller i CHIPCLK, and may either signal 511 or presenting XSTAI jereatter receives 2 Controllers may release wong doe ot 512 one bits in the usual fashion (1 and 2 RDATAN low, and continues to try to i 9 above), or may just keep XDATAN low. send the start bit. June 15, 1986 2-500

Figure 1. VLSIC Timing

Signetics Microprocessor Products Preliminary Specification Very Little Serial Interface Chip (VLSIC) SCB68174 ABSOLUTE MAXIMUM RATINGS’ Vin Input voltage range =05 to +55 Ts1e Storage temperature range =65 to +150 DC ELECTRICAL CHARACTERISTICS Vcc = 5V +5%, Ta=0°C to +70°C, Ry = 90, Cy = 15pF% 4 fie Low-level input current Vin = 0.4V. mA ii High-level input current « Vin=2.7V pA Vit Low-level input voltage Vv Vin High-level input voltage Vv Vou Low level output voltage CHIPCLK, RDATAN, RSTARTN, RESETO2N lo. = 8mA v SYSCLKO lou = 24mA v SERDATN, RESETOIN, SYSRESETN lo. = 70mA Vv Vou High level output voltage CHIPCLK, RDATAN, RSTARTN, SYSCLKO lon = -3mA 27 Vv lou Output leakage current SERDATN, RESETO1N, SYSRESETN RESETO2N Von = 5.5V 100 BA log Voc supply current Voc = Max 60 mA Q Input capacitance SERCLK, SYSCLK 5 pF Cio VO capacitance SERDATN 10 pF NOTES: |. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or at any other conditions other than those indicated in the Electrical Characteristics section of this data sheet is not implied. 2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature. 3. Parameters are valid over specified temperature range. 4. All voltage measurements are referenced to ground (GND). All time measurements are referenced at input voltages of 0.8V and 2V as appropriate. June 15, 1986 2-502

Signetics Microprocessor Products Preliminary Specification Very Little Serial interface Chip (VLSIC) SCB68174 AC ELECTRICAL CHARACTERISTICS Voc = 5V 5%, Ta =0°C to +70°C, Ri = 90, C = 50pF® * (except as noted) 1 | Prop, C1 or C2 to SERDATN low 10 20 ns 2 | Prop, C1 to SERDATN released 10 25 ns 3 | Prop, $1 (2) to RDATAN (RSTARTN) low 20 ns 4 | Prop, $1 (S2) to RDATAN (RSTARTN) high 20 ns 5 | Prop, C2 to CHIPCLK low 15 ns 6 | Prop, C1 to CHIPCLK high 12 ns 7 | Prop, XDATAN low and XSTARTN low (with CHIPCLK high) to SERDATN low® 25 ns 8 | RDATAN low to CHIPCLK low ter-10 ns 9 | RDATAN high to CHIPCLK low ta-12 ns 10 | RSTARTN low to CHIPCLK high tor-10 ns 11 | RSTARTN high to CHIPCLK high tor-12 ns 12 | Setup, SERDATN and/or SERDATIN low to S1 or S2 8 ns 13 | Hold, SERDATN and/or SERDATIN low after S1 or S2 2 ns 14 | Setup, SERDATN and SERDATIN high to S1 or S2 6 ns 15 | Hold, SERDATN and SERDATIN high ater S1 or S2 2 ns 16 | Setup, XDATAN low to C1, XSTARTN low to C2 7 ns 17. | Hold, XDATAN low after C1, XSTARTN low after C2 0 ns 18 | Setup, XDATAN high to C1, XSTAATN high to C2 7 ns 19 | Hold, XDATAN high after C1, XSTARTN high after C2 0 ns 20 | Pulse Width, XDATAN and XSTARTN low with CHIPCLK high 10 ns 21 | Prop, SYSCLK low to SYSCLKO low 8 15 ns 22 | Prop, SYSCLK high to SYSCLKO high 5 12 ns 23 | Pulse width, SERCLK low (tou) 15 ns 23 | Pulse width, SYSCLK low (Isycu) 10 ns 24 | Pulse width, SYSCLK high (tsycx) 10 ns 25 | Cycle time, SYSCLK (tsycy) 62 ns 25A | Cycle time, SERCLK (general case)| 5.49(tsysy) 561{tsysy) ns 26 | Pulse width, SERCLK high, C1 to S1 (teycy = 62.5) 174,25 ns (general case)| 2.5tsycy + 18 ns 27 | Pulse width, SERCLK high, C2 to S2 (tsycy = 62.5) 120 ns (general case) Atsycv)-5_ | ns TEST CONDITIONS ow a ! = on | DUT re | [somes Te sous Te compcux naranrn, Roatan | 4ssn | | Syepesern neserosn, svscLKa 1820 1] neseroon June 15, 1986 2-503