SCAN921821TSM/NOPB

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 SCAN921821Dual18-BitSerializerwithPre-emphasis,IEEE1149.1(JTAG),andAt-Speed BIST Check forSamples: SCAN921821 1FEATURES DESCRIPTION The SCAN921821 isa dualchannel18-bitserializer 2• 15-66MHz Dual 18:1Serializerwith2.376Gbps featuringsignalconditioning,boundarySCAN, and at-TotalThroughput speed BIST.Each serializerblocktransformsan 18-• 8-levelSelectablePre-emphasis on Each bitparallelLVCMOS/LVTTL data bus intoa single Channel DrivesLossy Cables and Backplanes Bus LVDS data stream withembedded clock.This singleserialdata stream with embedded clock• >15kV HBM ESD Protectionon Bus LVDS I/O simplifiesPCB design and reduces PCB cost byPins narrowingdata paths thatin turnreduce PCB size• Robust BLVDS SerialData Transmissionwith and layers.The singleserialdata stream alsoEmbedded Clock forExceptionalNoise reduces cablesize,the number of connectors,andImmunity and Low EMI eliminatesclock-to-dataand data-to-dataskew.

Power Saving ControlPin forEach Channel Each channel also has an 8-levelselectablepre-• IEEE 1149.1"JTAG" Compliant emphasis feature that significantlyextends performanceover lossyinterconnect.Each channel• At-Speed BIST -PRBS Generation alsohas itsown powerdown pinthatsaves power by• No ExternalCoding Required reducingsupply currentwhen the channel is not• InternalPLL, No ExternalPLL Components beingused.Required The SCAN921821 also incorporatesadvanced• Single+3.3V Power Supply testabilityfeaturesincludingIEEE 1149.1 and at-
Low Power: 260 mW (typ)Per Channel at66 speed BIST PRBS patterngenerationto facilitate MHz withPRBS-15 Pattern verificationofboardand linkintegrity
Single3.3V Supply
FabricatedwithAdvanced CMOS Process Technology
Industrial−40 to+85°C Temperature Range
Compact 100-ballNFBGA Package Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

IEEE 1149.1 Test Access Port D INA D INB D OUTAP D OUTAN D OUTBP D OUTBN TDI TDO TMS TCK BIST PWDNA SYNCA TxCLK PWDNB SYNCB TRST PEMB PEMA BISTA BISTB ENA ENB SCAN921821 SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 www.ti.com Block Diagram These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.3Vto+4V SupplyVoltage(VDD )Ramp Rate < 30 V/ms LVCMOS/LVTTL InputVoltage −0.3Vto(VDD +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VDD +0.3V) Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuit Duration 10ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +220°C Maximum Package Power Dissipationat25°C NFBGA-100 3.57W DeratingAbove 25°C 28.57mW/ °C Thermalresistance θJA 35°C/W θJC 11.1°C/W ESD Rating HBM, 1.5KΩ,100 pF Allpins >8 kV Bus LVDS pins >15 kV MM, 0Ω,200 pF >1200 V CDM >2 kV (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe specified.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications.

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDD ) 3.15 3.3 3.45 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C ClockRate 15 66 MHz SupplyNoise 100 mV p-p DC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL InputDC Specifications HighLevelInputVIH 2.0 VDD VVoltage Low LevelInputVIL GND 0.8 VVoltage VCL InputClamp Voltage ICL = −18 mA −1.5 -0.7 V HighLevelInputIINH VIN = VDD = VDDMAX −20 ±2 +20 μACurrent Low LevelOutputIINL VIN = VSS ,VDD = VDDMAX −10 ±2 +10 μACurrent 1149.1(JTAG) DC Specifications HighLevelInputVIH 2.0 VDD VVoltage Low LevelInputVIL GND 0.8 VVoltage VCL InputClamp Voltage ICL = −18 mA −1.5 -0.7 V HighLevelInputIINH VIN = VDD = VDDMAX -20 +20 μACurrent Low LevelOutputIINL VIN = VSS ,VDD = VDDMAX -200 +200 μACurrent HighLevelOutputVOH IOH = −9 mA 2.3 VDD mVVoltage Low LevelOutputVOL IOL = 9 mA GND 0.5 mVVoltage OutputShortCircuitIOS VOUT = 0 V -100 -80 -50 mACurrent PWDN orEN = 0.8V,VOUT = 0 V -10 +10 μAOutputTri-stateIOZ Current PWDN orEN = 0.8V,VOUT = VDD -30 +30 μA Bus LVDS Output DC Specifications OutputDifferentialVOD See Figure10,R L = 100Ω 450 500 550 mVVoltage(DO+) -(DO-) OutputDifferentialΔVOD 2 15 mVVoltageUnbalance VOS OffsetVoltage 1.05 1.2 1.25 V OffsetVoltageΔVOS 2.7 15 mVUnbalance (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN921821

SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units Pre-EmphasisLevel= 1 1.10 1.24 1.35 Pre-EmphasisLevel= 2 1.35 1.47 1.55 Pre-EmphasisLevel= 3 1.55 1.70 1.80Pre-EmphasisOutput Q POV VoltageRatio Pre-EmphasisLevel= 4 1.80 1.91 1.95 |VODPRE /VOD | Pre-EmphasisLevel= 5 1.95 2.08 2.20 Pre-EmphasisLevel= 6 2.10 2.21 2.35 Pre-EmphasisLevel= 7 2.15 2.30 2.50 OutputShortCircuitIOS DO = 0V,Din= H, PWDN and EN = 2.4V -10 -25 -75 mACurrent PWDN orEN = 0.8V,DO = 0V (3) -10 ± 1 +10 µATRI-STATE OutputIOZ Current PWDN orEN = 0.8V,DO = VDD (3) -55 ± 6 +55 µA Power Supply Current(DVDD, PVDD and AVDD Pins) f= 66 MHz, PRBS-15 160 225 mAPattern TotalSupplyCurrent C L = 15pF,IDD f= 66 MHz, WorstCase(includesloadcurrent) R L = 100 Ω Pattern(Checker-Board 180 mA Pattern) f= 66 MHz, PRBS-15 240 mAPatternTotalSupplyCurrent C L = 15pF,IDDP withPre-Emphasis f= 66 MHz, WorstCaseR L = 100 Ω(includesloadcurrent) Pattern(Checker-Board 280 325 mA Pattern) SupplyCurrentIDDX PWDN = 0.8V,EN = 0.8V 1.0 3.0 mAPowerdown (3) IOZ ismeasured ateach pin.The DOUT pinnotundertestisfloatedtoisolatetheTRI-STATE currentflow. Timing Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tTCP TransmitClockPeriod 15.2 T 66.7 ns TransmitClockHightTCIH 0.4T 0.5T 0.6T nsTime TransmitClockLowtTCIL 0.4T 0.5T 0.6T nsTime TCLK InputTransitiontCLKT 3 6 nsTime tJIT TCLK InputJitter See (3) 80 ps (RMS) (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (3) Specifiedby designusingstatisticalanalysis.

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 AC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units SerializerAC Specifications Bus LVDS Low-to-HightLLHT 0.3 0.4 nsSee Figure2,(3) TransitionTime R L = 100Ω, Bus LVDS High-to-Low C L=10pF toGNDtLHLT 0.3 0.4 nsTransitionTime DIN (0-17)SetuptotDIS 1.9 nsSee Figure4,(3) TCLK R L = 100Ω, DIN (0-17)Holdfrom C L=10pF toGNDtDIH 0.6 nsTCLK DO ± HIGH totHZD 3.9 10 nsTRI-STATE Delay DO ± LOW toTRI-tLZD 3.5 10 nsSee Figure5STATE Delay R L = 100Ω, DO ± TRI-STATE to C L=10pF toGNDtZHD 3.2 10 nsHIGH Delay DO ± TRI-STATE totZLD 2.4 10 nsLOW Delay See Figure7,tSPW SYNC PulseWidth 5*tTCP 6*tTCP nsR L = 100Ω SerializerPLL Lock See Figure6,tPLD 510*tTCP 1024*tTCP nsTime R L = 100Ω tSD SerializerDelay See Figure8 ,R L = 100Ω tTCP + 2.5 tTCP + 4.5 tTCP + 6.5 ns ChanneltoChanneltSKCC 70 psSkew Room Temperature,VDD = 3.3V, pstRJIT Random Jitter 6.166 MHz (RMS)

15 MHz -390 320 psDeterministicJittertDJIT Figure9,(3)

66 MHz -60 30 ps

1149.1(JTAG) AC Specifications Maximum TCK ClockfMAX 25 MHzFrequency TDI orTMS SetuptotS 2.4 nsTCK, H orL TDI orTMS HoldfromtH 2.8 nsC L = 15pF,TCK, H orL R L = 500 Ω TCK PulseWidth,H ortW1 10 nsL tW2 TRST PulseWidth,L 10 ns RecoveryTime,TRSTtREC 2 nstoTCK (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (3) Specifiedby designusingstatisticalanalysis. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN921821

SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 www.ti.com AC Timing Diagrams and TestCircuits Figure1. “Worst Case ” SerializerIDD TestPattern Figure2. SerializerBus LVDS DistributedOutput Load and TransitionTimes Figure3. SerializerInputClock TransitionTime Figure4. SerializerSetup/HoldTimes

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 Figure5. SerializerTRI-STATE TestCircuitand Timing Figure6. SerializerPLL Lock Time,and PWRDN TRI-STATE Delays Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN921821

SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 www.ti.com Figure7. SYNC Timing Delay Figure8. SerializerDelay

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 Figure9. DeterministicJitterand IdealBitPosition VOD = (DO +)–(DO −). Differentialoutputsignalisshown as (DO+)–(DO −),deviceinData Transfermode. Figure10. VOD Diagram Pre-emphasis TruthTable PEM LEVEL PEM2 PEM1 PEM0

0 L L L

1 L L H

2 L H L

3 L H H

4 H L L

5 H L H

6 H H L

7 H H H

PV SS DOUTBN AV DD ENB AV DD A9 A10 DOUTAN DOUTAP B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DINB16 AV DD DOUTBP AV DD PEMB1 AV SS PEMB0 DINB14 C2 C3 C4 C5 C6 C7 C8 DV DD DV SS PV DDDV DD PEMA0 AV DD PEMA2 C9 C10 PEMA1 AV DD D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DINB12 DINB15 DV SS AV SS DV SS DINA17 DINA13 BISTA ENA DINB11 E2 E3 E4 E5 E6 E7 E8 DINB9 DINB5 PV DD DINA11 DINA14 DINA12 DINA9 E9 E10 SYNCA DINA16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DINB10 DINB7 DINB2 DV SS DINA4 DINA10 DINA8 DINA0 DINA5 G1 G2 G3 G4 G5 G6 G7 G8 DINB4 DINA2DV DDDV SS DV DD DINA1 DINA7 G9 G10 DINA3 DV DD J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 DINB0 DV DD TRST PV DD PV SS PV DD NC H1 H2 H3 H4 H5 H6 H7 H8 DINB1 TxCLK TCK DV SS PV DD PV SS DV SS H9 H10 DV DD PWDNB K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DV SS TMS DV SS TDO DV DD PV SS PV SS DINB13 DINB6 DINB3 SYNCB TDI PWDNA DINA6 DINA15 AV SS AV SS DINB17 AV SS DINB8 PEMB2 DV SS SCAN921821 SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 www.ti.com Pin Diagram Figure11. SCAN921821TVV Top View

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www.ti.com SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013 Pin Descriptions Pin Name Pin Count I/O,Type Description DATA PINS DINA0-17 18 Transmitterinputs.Thereisa pull-downcircuitryon each ofthesepinswhichareactive I,LVCMOS ifrespectivePWDNA orPWDNB pinispulledhigh.DINB0-17 18 DOUTAP 1 DOUTAN 1 O,BLVDS Invertingand non-invertingdifferentialtransmitteroutputs. DOUTBP 1 DOUTAN 1 TIMING AND CONTROL PINS Transmitterreferenceclock.Used tostrobedataattheinputsand todrivetheTxCLK 1 I,LVCMOS transmitterPLL.Thereisa pull-upcircuitryon thispinwhichisalwaysactive. ENA 1 Transmitteroutputsenablepins.Thereisa pull-downcircuitryon each ofthesepinsthat I,LVCMOS areactiveifcorrespondingPWDNA orPWDNB pinispulledhigh.When thesepinsare ENB 1 settoLOW, thetransmitteroutputswillbe disabled.The PLL willremainlocked. PWDNA 1 Stand-bymode pins.Thereisa pull-downcircuitryon each ofthesepinsthatarealways I,LVCMOS active.When thesepinsaresettoLOW, thetransmitterwillbe putinlowpower mode PWDNB 1 and thePLL willloselock. SYNCA 1 Transmittersynchronizationpins.Thereisa pull-downcircuitryon each ofthesepins thatareactiveifcorrespondingPWDNA orPWDNB pinispulledhigh.When thesepinsI,LVCMOS aresettoHIGH, thetransmitterwillignoreincomingdataand send SYNC patternstoSYNCB 1 providea lockingreferencetoreceiver(s). PRE-EMPHASIS PINS PEMA0-2 3 8-levelpre-emphasisselectionpins.Thereisa pull-downcircuitryon each ofthesepins I,LVCMOS whichareactiveifcorrespondingPWDNA orPWDNB pinispulledhigh.PEMB0-2 3 JTAG PINS TestData InputtosupportIEEE 1149.1.Thereisa pull-upcircuitryon thispinwhichisTDI 1 I,LVCMOS alwaysactive. TDO 1 O, LVCMOS TestData OutputtosupportIEEE 1149.1. TestMode SelectInputtosupportIEEE 1149.1.Thereisa pull-upcircuitryon thispinTMS 1 I,LVCMOS whichisalwaysactive. TCK 1 I,LVCMOS TestClockInputtosupportIEEE 1149.1.Thereisno failsafecircuitryon thispin. TestResetInputtosupportIEEE 1149.1.Thereisa pull-upcircuitryon thispinwhichisTRST 1 I,LVCMOS alwaysactive. BIST PINS BISTA 1 BIST selectionpins.These pinsselectwhichtransmitterwillgeneratea PRBS likedata. I,LVCMOS Thereisa pull-downcircuitryon thesepinswhichareactiveifcorrespondingPWDNA or BISTB 1 PWDNB pinispulledhigh. POWER PINS AVDD 6 I,POWER Power SupplyfortheLVDS circuitry. DVDD 8 I,POWER Power Supplyforthedigitalcircuitry. PVDD 5 I,POWER Power SupplyforthePLL and BG circuitry. AVSS 5 I,POWER Ground referencefortheLVDS circuitry. DVSS 10 I,POWER Ground referenceforthedigitalcircuitry. PVSS 5 I,POWER Ground referenceforthePLL and BG circuitry. OTHER PINS NC 1 N/A Not connected. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN921821

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REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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www.ti.com 26-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SCAN921821TSM/NOPB ACTIVE NFBGA NZD 100 240 Green (RoHS & no Sb/Br) SNAGCU Level-4-260C-72 HR -40 to 85 SCAN921821 TSM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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