SCAN921821

SCAN921821 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

Features

n 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps total throughput n 8-level selectable pre-emphasis on each channel drives lossy cables and backplanes n >15kV HBM ESD protection on Bus LVDS I/O pins n Robust BLVDS serial data transmission with embedded clock for exceptional noise immunity and low EMI n Power saving control pin for each channel n IEEE 1149.1 "JTAG" Compliant n At-Speed BIST - PRBS generation n No external coding required n Internal PLL, no external PLL components required n Single +3.3V power supply n Low power: 260 mW (typ) per channel at 66 MHz with PRBS-15 pattern n Single 3.3 V supply n Fabricated with advanced CMOS process technology n Industrial −40 to +85˚C temperature range n Compact 100-ball FBGA package Block Diagram 20084401 November 2004 SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST © 2004 National Semiconductor Corporation DS200844 www.national.com

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD) −0.3V to +4V Supply Voltage (VDD) Ramp Rate < 30 V/ms LVCMOS/LVTTL Input Voltage −0.3V to (V DD +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (V DD +0.3V) Bus LVDS Driver Output Voltage −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10ms Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) +220˚C Maximum Package Power Dissipation at 25˚C FBGA-100 3.57 W Derating Above 25˚C 28.57 mW/˚C Thermal resistance θ JA 35˚C/W θJC 11.1˚C/W ESD Rating HBM, 1.5 KΩ, 100 pF All pins >8k V Bus LVDS pins >15 kV MM, 0Ω, 200 pF >1200 V CDM >2k V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDD) 3.15 3.3 3.45 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Clock Rate 15 66 MHz Supply Noise 100 mV p-p Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL Input DC Specifications VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −1.5 -0.7 V IINH High Level Input Current VIN =V DD =V DDMAX −20 ±2 +20 µA IINL Low Level Output Current VIN =V SS,V DD =V DDMAX −10 ±2 +10 µA 1149.1 (JTAG) DC Specifications VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −1.5 -0.7 V IINH High Level Input Current VIN =V DD =V DDMAX -20 +20 µA IINL Low Level Output Current VIN =V SS,V DD =V DDMAX -200 +200 µA VOH High Level Output Voltage IOH =− 9m A 2 . 3 V DD mV VOL Low Level Output Voltage IOL = 9 mA GND 0.5 mV IOS Output Short Circuit Current VOUT = 0 V -100 -80 -50 mA IOZ Output Tri-state Current PWDN or EN = 0.8V, V OUT =0V -10 +10 µA PWDN or EN = 0.8V, V OUT = VDD -30 +30 µA SCAN921821 www.national.com 2

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units Bus LVDS Output DC Specifications VOD Output Differential Voltage (DO+) - (DO-) Figure 10,R L = 100Ω 450 500 550 mV ∆VOD Output Differential Voltage Unbalance 21 5 m V VOS Offset Voltage 1.05 1.2 1.25 V ∆VOS Offset Voltage Unbalance 2.7 15 mV QPOV Pre-Emphasis Output Voltage Ratio |V ODPRE /V OD | Pre-Emphasis Level = 1 1.10 1.24 1.35 Pre-Emphasis Level = 2 1.35 1.47 1.55 Pre-Emphasis Level = 3 1.55 1.70 1.80 Pre-Emphasis Level = 4 1.80 1.91 1.95 Pre-Emphasis Level = 5 1.95 2.08 2.20 Pre-Emphasis Level = 6 2.10 2.21 2.35 Pre-Emphasis Level = 7 2.15 2.30 2.50 I OS Output Short Circuit Current DO = 0V, Din = H, PWDN and EN = 2.4V -10 -25 -75 mA IOZ TRI-STATE Output Current PWDN or EN = 0.8V, DO = 0V (Note 4) -10 ± 1 +10 µA PWDN or EN = 0.8V, DO = VDD (Note 4) -55 ± 6 +55 µA Power Supply Current (DVDD, PVDD and AVDD Pins) IDD Total Supply Current (includes load current) CL = 15pF, RL = 100 Ω f = 66 MHz, PRBS-15 Pattern 160 225 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 180 mA IDDP Total Supply Current with Pre-Emphasis (includes load current) CL = 15pF, RL = 100 Ω f = 66 MHz, PRBS-15 Pattern 240 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 280 325 mA IDDX Supply Current Powerdown PWDN = 0.8V, EN = 0.8V 1.0 3.0 mA Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period 15.2 T 66.7 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 36 n s tJIT TCLK Input Jitter (Note 5) 80 ps (RMS) SCAN921821 www.national.com3

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units Serializer AC Specifications tLLHT Bus LVDS Low-to-High Transition Time Figure 2, (Note 5) RL = 100Ω, CL=10pF to GND 0.3 0.4 ns tLHLT Bus LVDS High-to-Low Transition Time 0.3 0.4 ns tDIS DIN (0-17) Setup to TCLK Figure 4, (Note 5) RL = 100Ω, CL=10pF to GND 1.9 ns tDIH DIN (0-17) Hold from TCLK 0.6 ns tHZD DO ± HIGH to TRI-STATE Delay Figure 5 RL = 100Ω, CL=10pF to GND 3.9 10 ns tLZD DO ± LOW to TRI-STATE Delay 3.5 10 ns tZHD DO ± TRI-STATE to HIGH Delay 3.2 10 ns tZLD DO ± TRI-STATE to LOW Delay 2.4 10 ns tSPW SYNC Pulse Width Figure 7, RL = 100Ω 5*tTCP 6*tTCP ns tPLD Serializer PLL Lock Time Figure 6, RL = 100Ω 510*tTCP 1024*tTCP ns tSD Serializer Delay Figure 8,R L = 100Ω tTCP + 2.5 t TCP + 4.5 t TCP + 6.5 ns tSKCC Channel to Channel Skew 70 ps tRJIT Random Jitter Room Temperature, VDD = 3.3V, 66 MHz 6.1 ps (RMS) tDJIT Deterministic Jitter Figure 9, (Note 5)

15 MHz -390 320 ps

66 MHz -60 30 ps

1149.1 (JTAG) AC Specifications fMAX Maximum TCK Clock Frequency CL = 15pF, RL = 500 Ω

25 MHz

T C K ,Ho rL 2.4 ns tH TDI or TMS Hold from TCK, H or L 2.8 ns tW1 TCK Pulse Width, H or L 10 ns tW2 TRST Pulse Width, L 10 ns tREC Recovery Time, TRST to TCK 2n s Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for V CC = 3.3V and T A = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH and VTL which are differential voltages. Note 4: IOZ is measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow. Note 5: Guaranteed by Design (GBD) using statistical analysis. SCAN921821 www.national.com 4

0 LLL

7 HHH

FIGURE 9. Deterministic Jitter and Ideal Bit Position Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. FIGURE 10. VOD Diagram

www.national.com9

Pin Name Pin Count I/O, Type Description DATA PINS DINA0-17 18 I, LVCMOS Transmitter inputs. There is a pull-down circuitry on each of these pins which are active if respective PWDNA or PWDNB pin is pulled high. DINB0-17 18 DOUTAP 1 O,BLVDS Inverting and non-inverting differential transmitter outputs.DOUTAN 1 DOUTBP 1 DOUTAN 1 TIMING AND CONTROL PINS TxCLK 1 I, LVCMOS Transmitter reference clock. Used to strobe data at the inputs and to drive the transmitter PLL. There is a pull-up circuitry on this pin which is always active. ENA 1 I, LVCMOS Transmitter outputs enable pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to LOW, the transmitter outputs will be disabled. The PLL will remain locked.ENB 1 PWDNA I, LVCMOS Stand-by mode pins. There is a pull-down circuitry on each of these pins that are always active. When these pins are set to LOW, the transmitter will be put in low power mode and the PLL will lose lock.PWDNB SYNCA 1 I, LVCMOS Transmitter synchronization pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to HIGH, the transmitter will ignore incoming data and send SYNC patterns to provide a locking reference to receiver(s).SYNCB 1 PRE-EMPHASIS PINS PEMA0-2 3 I, LVCMOS 8-level pre-emphasis selection pins. There is a pull-down circuitry on each of these pins which are active if corresponding PWDNA or PWDNB pin is pulled high.PEMB0-2 3 JTAG PINS TDI 1 I, LVCMOS Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TDO 1 O, LVCMOS Test Data Output to support IEEE 1149.1. TMS 1 I, LVCMOS Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TCK 1 I, LVCMOS Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin. TRST 1 I, LVCMOS Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. BIST PINS BISTA 1 I, LVCMOS BIST selection pins. These pins select which transmitter will generate a PRBS like data. There is a pull-down circuitry on these pins which are active if corresponding PWDNA or PWDNB pin is pulled high. BISTB 1 POWER PINS AVDD 6 I, POWER Power Supply for the LVDS circuitry. DVDD 8 I, POWER Power Supply for the digital circuitry. PVDD 5 I, POWER Power Supply for the PLL and BG circuitry. AVSS 5 I, POWER Ground reference for the LVDS circuitry. DVSS 10 I, POWER Ground reference for the digital circuitry. PVSS 5 I, POWER Ground reference for the PLL and BG circuitry. OTHER PINS NC 1 N/A Not connected. SCAN921821 www.national.com 10

Physical Dimensions inches (millimeters) unless otherwise noted Dimensions shown in millimeters only Order Number SCAN921821TSM National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST