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SCAN921260UJB/NOPB

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SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 SCAN921260X61:10DeserializerwithIEEE1149.1(JTAG)andat-speedBIST Check forSamples: SCAN921260 1FEATURES DESCRIPTION The SCAN921260 integratessixdeserializerdevices 2• IEEE 1149.1(JTAG) Compliant and At-Speed into a single chip. The SCAN921260 canBIST TestModes simultaneouslydeserializeup tosixdatastreamsthat• DeserializesOne toSixBusLVDS InputSerial have been serializedby the Texas Instruments Data Streams With Embedded Clocks SCAN921023 Bus LVDS serializer.The devicealso includesa seventhserialinputchannelthatservesas• Seven SelectableSerialInputstoSupport N+1 a redundantinput.Redundancy ofDeserializedStreams

Seventh Channel Has SinglePin Monitor Each deserializerblockintheSCAN921260 operates Output That ReflectsInputFrom Seventh independentlywith itsown clockrecoverycircuitry and lock-detectsignaling.Channel Input
ParallelClock Rate Up To 66 MHz The SCAN921260 uses a single+3.3V power supply withan estimatedpower dissipationof1.2W at3.3V• On Chip FilteringforPLL with a PRBS-15 pattern.Refer to the Connection• High Impedance InputsUpon Power Off(Vcc = Diagramsforpackaginginformation.0V)
SinglePower Supply at+3.3V
196-PinNFBGA Package (Low-ProfileBallGrid Array)Package
IndustrialTemperature Range Operation:−40 to+85 FunctionalBlock Diagram Figure1. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2001–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) Over operatingfree-airtemperaturerange(unlessotherwisenoted) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto3.9V LVCMOS/LVTTL OutputVoltage −0.3Vto3.9V Bus LVDS ReceiverInputVoltage −0.3Vto3.9V Bus LVDS DriverOutputVoltage −0.3Vto3.9V Bus LVDS OutputShortCircuitDuration 10ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,10 seconds) +225°C Max Pkg Power DissipationCapacity@ 25°C 196 NFBGA 3.7W Package Derating: 196 NFBGA 29.4mW/ °C above +25°C ThermalResistance: θJA 34°C/W θJC 8°C/W ESD Rating: Human Body Model >2KV Machine Model >750V (1) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications (2) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation. RECOMMENDED OPERATING CONDITIONS Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +85 °C ClockRate 20 66 MHz

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (1) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC Specifications:AppliestopinsinPin DescriptiontablewithtypeCMOS Inputor Output VIH HighLevelInputVoltage InputPins 2.0 VCC V VIL Low LevelInputVoltage InputPins GND 0.8 V VCL InputClamp Voltage InputPins -0.87 -1.5 V IIN InputCurrent Vin= 0 or3.6V,InputPins -20 +20 uA VOH HighLevelOutputVoltage IOH = 6mA, OutputPins 2 3 VCC V VOL Low LevelOutputVoltage IOL = 6mA, OutputPins GND 0.18 0.4 V VOH HighLevelOutputVoltage IOH = 12mA, TDO Output 2 3 VCC V VOL Low LevelOutputVoltage IOL = 12mA, TDO Output GND 0.18 0.4 V IOS OutputshortCircuitCurrent Vout= 0V,OutputPins -15 -46 -85 mA IOS OutputshortCircuitCurrent Vout= 0V,TDO Output -15 -120 mA PD* orREN = 0.8VIOZ Tri-stateOutputCurrent -10 +/-0.2 +10 uAVout= 0V orVCC Bus LVDS DC specifications:AppliestopinsinPin DescriptiontablewithtypeBus LVDS Inputs VTH DifferentialThresholdHighVoltage VCM = 1.1V(VRI+-VRI-) +3 +50 mV VTL DifferentialThresholdLow Voltage -50 -2 mV Vin= +2.4V or0V,IIN InputCurrent -10 +/-1 +10 uAVcc = 3.6or0V Supply Current 3.6V,CheckerBoard Pattern,ICCR WorstCase SupplyCurrent 600 660 mAC L = 15pF,66Mhz SupplyCurrentwhen Powered PWRDN= 0.8VICCXR 0.36 1 mADown REN = 0.8V Timing Requirements forREFCLK tRFCP REFCLK Period 15.15 50 ns tRFDC REFCLK DutyCycle 40 50 60 % tRFCP /tTC RatioofREFCLK toTCLK 0.95 1.05 P tRFTT REFCLK TransitionTime 8 ns DeserializerSwitchingCharacteristics tRCP RCLK Period RCLK 15.15 50 ns tRDC RCLK DutyCycle RCLK (2) 45 50 55 % PeriodofBus LVDS signalwhentCHTST CHTST (3) 25 nsCHTST isselectedby MUX CMOS/TTL Low-to-HighTransitiontCLH C L = 15pF 1.7 6 nsTime CMOS/TTL High-to-LowTransitiontCHL C L = 15pF 1.6 6 nsTime tROS Rout Data ValidbeforeRCLK C L = 15pF,see Figure3 0.35*tRCP ns tROH Rout Data ValidafterRCLK C L = 15pF,see Figure3 -0.35*tRCP ns tHZR HightoTri-stateDelay 12 ns tLZR Low toTri-stateDelay 12 ns C L = 15pF,see Figure8 tZHR Tri-statetoHighDelay 12 ns tZLR Tri-statetoLow Delay 12 ns tDD DeserializerDelay See Figure2 1.75*tRCP +3 1.75*tRCP +7 1.75*tRCP +10.5 ns (1) TypicalvaluesaregivenforVcc = 3.3Vand TA =25°C (2) Specifiedby designusingstatisticalanalysis. (3) Because theBus LVDS serialdatastreamisnotdecoded,themaximum frequencyoftheCHTST outputdrivercouldbe exceeded ifthe datastreamwere switchedtoCHTST. The maximum frequencyoftheBUS LVDS inputshouldnotexceed theparallelclockrate. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified Symbol Parameter Conditions Min Typ Max Units

66 MHz 2 usDeserializerPLL LOCK Time fromtDSR1 See Figure4(4)

PWRDN (withSYNCPAT) 20 MHz 10 us 66 MHz 1.5 usDeserializerPLL Lock Time fromtDSR2 See Figure5(4) SYNCPAT 20 MHz 5 us tRNMI-R IdealStrobeWindow Right 66 MHz, see Figure11 +400 ps tRNMI-L IdealStrobeWindow Left 66 MHz, see Figure11 -400 ps (4) ForthepurposeofspecifyingdeserializerPLL performancetDSR1 and tDSR2 arespecifiedwiththeREFCLK runningand stable,and specificconditionsoftheincomingdatastream(SYNCPATs). tDSR1 isthetimerequiredforthedeserializertoindicatelockupon power- up orwhen leavingthepower-down mode. tDSR2 isthetimerequiredtoindicatelockforthepowered-upand enableddeserializerwhen theinput(RI+and RI−)conditionschange fromnotreceivingdatatoreceivingsynchronizationpatterns(SYNCPATs). The timetolock torandom dataisdependentupon theincomingdata. SCAN CIRCUITRY TIMING REQUIREMENTS Symbol Parameter Conditions Min Typ Max Units fMAX Maximum TCK Clock 25.0 50.0 MHz Frequency tS TDI toTCK, H orL 1.0 ns tH TDI toTCK, H orL 2.0 ns tS TMS toTCK, H orL 2.5 ns R L = 500Ω,C L = 35 pF tH TMS toTCK, H orL 1.5 ns tW TCK PulseWidth,H orL 10.0 ns tW TRST PulseWidth,L 2.5 ns tREC RecoveryTime,TRST to 2.0 ns TCK

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SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com CONTROL PINS TRUTH TABLE PWRDN REN SEL2 SEL1 SEL0 Rout(1) CHTST LOCK[0:5] RCLK[0:5] H H L L L Din6Decoded to Din0(notdecoded) Active(3) Active(4)(2) Rout 0 (0:9)(2) H H L L H Din6Decoded to Din1(notdecoded) Active(3) Active(4)(2) Rout 1 (0:9)(2) H H L H L Din6Decoded to Din2(notdecoded) Active(3) Active(4)(2) Rout 2 (0:9)(2) H H L H H Din6Decoded to Din3(notdecoded) Active(3) Active(4)(2) Rout 3 (0:9)(2) H H H L L Din6Decoded to Din4(notdecoded) Active(3) Active(4)(2) Rout 4 (0:9)(2) H H H L H Din6Decoded to Din5(notdecoded) Active(3) Active(4)(2) Rout 5 (0:9)(2) H H H H L Din6isnot Z Active(3) Active(4)(2) Decoded H H H H H Din6isnot Din6(notdecoded) Active(3) Active(4)(2) Decoded L X X X X Z Z Z Z H L X X X Z Z Active(3) Z (1) The routingoftheDininputstotheDeserializersand totheCHTST outputsaredependenton thestatesofSEL [0:2]. (2) Rout n[0:9]and RCLK [0:5]aretri-statedwhen LOCKn[0:5]isHigh. (3) LOCK ActiveindicatesthattheLOCK outputwillreflectthestateofitsrespectiveDeserializerwithregardtotheselecteddatastream. (4) RCLK ActiveindicatesthattheRCLK willbe runningiftheDeserializerislocked. TIMING DIAGRAMS Figure2. DeserializerDelay tDD Figure3. Output Timing tROS and tROH

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 Figure4. Locktime from PWRDN* tDSR1 Figure5. Locktime toSYNCPAT tDSR2 Figure6. Unlock Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Note:C L includesJigand straycapacitance.FortheTDO output,C L = 35pF. Figure7. Output Load forTiming and SwitchingCharacteristics Note:C L includesJigand straycapacitance.FortheTDO output,C L = 35pF. Figure8. DeserializerTri-stateTestCircuitand Timing

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013

APPLICATION INFORMATION

USING THE SCAN921023 and SCAN921260 The SCAN921260 combines six1:10 deserializersintoa singlechip.Each of the sixdeserializersacceptsa BusLVDS data stream up to 660 Mbps from TI'sSCAN921023 Serializer.The deserializersthen recoverthe embedded two clockbitsand datatodelivertheresulting10-bitwide words totheoutput.A seventhserialdata inputprovidesn+1 redundancycapability.The usercan program theseventhinputtobe an alternativeinputto any ofthesixdeserializers.Whicheverinputisreplacedby theseventhinputisthenroutedtotheCHANNEL TEST (CHTST) pinon receiveroutputport.The Deserializeruses a separatereferenceclock(REFCLK) and an onboard PLL toextracttheclockinformationfrom theincomingdatastreamand thendeserializethedata.The Deserializermonitorstheincomingclockinformation,determineslockstatus,and assertstheLOCKn outputhigh when lossoflockoccurs. Each ofthe6 channelsactscompletelyindependentofeach other.Each independentchannelhas outputsfora 10-bitwidedataword,therecoveredclockout,and thelock-detectoutput. The SCAN921260 has threeoperatingstates:Initialization,Data Transfer,and Resynchronization.In addition, therearetwo passivestates:Powerdown and Tri-state. The followingsectionsdescribeeach operatingmode and passivestate. INITIALIZATION BeforetheSCAN921260 receivesand deserializesdata,itand thetransmittingserializerdevicesmust initialize thelink.InitializationreferstosynchronizingtheSerializer'sand theDeserializer'sPLL'stolocalclocks.The local clocksmust be the same frequencyor withina specifiedrange iffrom differentsources.Afteralldevices synchronizetolocalclocks,theDeserializerssynchronizetotheSerializersas thesecond and finalinitialization step. Step 1: Afterapplyingpower to the Deserializer,the outputsare held in Tri-stateand the on-chippower- sequencingcircuitrydisablestheinternalcircuits.When Vcc reachesVccOK (2.1V),thePLL ineach deserializer beginslockingto the localclock(REFCLK). A localon-boardoscillatoror othersourceprovidesthe specified clockinputtotheREFCLK pin. Step 2: The DeserializerPLL must synchronizeto the Serializerto completethe initialization.Refer to the SerializerdatasheetfortheproperoperationduringthisstepoftheInitializationState.The Deserializeridentifies therisingclockedge ina synchronizationpatternorrandom dataand after80 clockcycleswillsynchronizetothe data stream from the serializer.At the pointwhere the Deserializer'sPLL locksto the embedded clock,the LOCKn pingoes low and validdata appears on the output.Note thatthisdiffersfrom previousdeserializers where theLOCKn signalwas notsynchronoustovaliddataappearingon theoutputs. DATA TRANSFER Afterinitialization,theserializertransfersdatatothedeserializers.The serialdatastreamincludesa startand stopbitappended by theserializer,whichframethetendatabits.The startbitisalwayshighand thestopbitis alwayslow.The startand stopbitsalsofunctionas clockbitsembedded intheserialstream. The Serializertransmitsthe data and clockbits(10+2 bits)at 12 timesthe TCLK frequency.For example,if TCLK is40 MHz, the serialrateis40 X 12 = 480 Mbps. Since only10 bitsare from inputdata,the serial 'payload'rateis10 timestheTCLK frequency.For instance,ifTCLK = 40 MHz, thepayloaddatais40 X 10 = 400 Mbps. TCLK isprovidedby thedatasourceand must be intherange20 MHz to40 MHz nominal. When one ofsixDeserializerchannelssynchronizestotheinputfrom a Serializer,itdrivesitsLOCKn pinlow and synchronouslydeliversvaliddataon theoutput.The Deserializerlockstotheembedded clock,uses itto generatemultipleinternaldata strobes,and drivesthe embedded clockto the RCLKn pin.The RCLKn is synchronousto the data on the ROUT[n0:n9] pins.While LOCKn is low,data on ROUT [n0:n9]is valid. Otherwise,ROUT[n0:n9]isinvalid. AllROUT, LOCK, and RCLK signalswilldrivea minimum ofthreeCMOS inputgates(15pF load)witha 66 MHz clock.Thisamount ofdriveallowsbussingoutputsoftwo Deserializersand a destinationASIC.REN controlsTri- stateofalltheoutputs. The Deserializerinputpinsarehighimpedance duringPowerdown (PWRDN low)and power-off(Vcc = 0V). Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com RESYNCHRONIZATION Whenever one ofthesixDeserializersloseslock,itwillautomaticallytrytoresynchronize.For example,ifthe embedded clockedge isnotdetectedtwo timesinsuccession,thePLL loseslockand theLOCKn pinisdriven high.The systemmust monitortheLOCKn pintodeterminewhen dataisvalid. The userhas thechoiceofallowingthedeserializertore-synchtothedatastreamortoforcesynchronizationby pulsingtheSerializerSYNC1 orSYNC2 pin.Thisscheme isleftup totheuserdiscretion.One recommendation istoprovidea feedbackloopusingtheLOCKn pinitselftocontrolthesync requestoftheSerializer(SYNC1 or SYNC2). DualSYNC pinsaregivenformultiplecontrolina multi-dropapplication. POWERDOWN The Powerdown stateisa low power sleepmode thatthe Serializerand Deserializertypicallyoccupy while waitingforinitialization,or to reduce power consumptionwhen no data istransferred.The Deserializerenters Powerdown when PWRDN isdrivenlow.InPowerdown, thePLL stopsand theoutputsgo intoTri-state,which reducessupplycurrenttothemicroamp range.To exitPowerdown, thesystemdrivesPWRDN high. Upon exitingPowerdown, the Deserializerentersthe Initializationstate.The system must then allowtimeto Initializebeforedatatransfercan begin. TRI-STATE When thesystem drivesREN pinlow,theDeserializerentersTri-state.Thiswilltri-statethereceiveroutputpins (ROUT[00:59])and RCLK[0:5].When the system drivesREN high,the Deserializerwillreturnto the previous stateas longas allothercontrolpinsremainstatic(PWRDN). IEEE 1149.1TEST MODES The SCAN921260 featuresinterconnecttestaccessthatiscomplianttotheIEEE 1149.1StandardforBoundary Scan Test(JTAG).AlldigitalTTL I/O'son thedeviceare accessibleusingIEEE 1149.1,and enteringthistest mode willoverrideallinputcontrolcases includingPWRDN and REN. Inadditiontothe4 requiredTestAccess Port(TAP)signalsofTMS, TCK, TDI,and TDO, TRST isprovidedfortestreset. To supplement the testcoverage providedby the IEEE 1149.1 testaccess to the digitalTTL pins,the SCAN921260 has two instructionstotesttheLVDS interconnects.The firstisEXTEST. Thisisimplementedat LVDS levelsand isonlyintendedas a go no-gotest(e.g.missingcables).The second method istheRUNBIST instruction.Itisan "at-system-speed"interconnecttest.Itisexecutedinapproximately33mS witha system clock speed of 66MHz. There are 12 bitsin the RX BIST data registerfor notificationof PASS/FAIL and TEST_COMPLETE; two bitsforeach ofthesixchannels.The RX BIST registerisdefinedas (fromMSB toLSB): [BIST COMPLETE forChannel 6, BIST PASS/FAIL forChannel 6, BIST COMPLETE forChannel 5, BIST PASS/FAIL forChannel 5,BIST COMPLETE forChannel 4,BIST PASS/FAIL forChannel 4,BIST COMPLETE forChannel3,BIST PASS/FAIL forChannel3,BIST COMPLETE forChannel2,BIST PASS/FAIL forChannel2, BIST COMPLETE forChannel1,BIST PASS/FAIL forChannel1] A "pass"indicatesthattheBER (Bit-Error-Rate)isbetterthan10-7.Thisisa minimum test,so a "fail"indication means thattheBER ishigherthan10-7. The BIST featuresoftheSCAN921260 six(6)channeldeserializerarecompatiblewiththeBIST featureson the SCAN921023 Serializer. An importantdetailis thatonce both deviceshave the RUNBIST instructionloaded intotheirrespective instructionregisters,bothdevicesmust move intotheRTI statewithin4K system clocks(Ata system CLK of 66Mhz and TCK of1MHz thisallowsfor66 TCK cycles).Thisisnota concernwhen bothdevicesare on the same scan chainorLSP, however,itcan be a problemwithsome multi-dropdevices.Thistestmode has been simulatedand verifiedusingTl'sSCANSTA111. Typicalapplicationsof1149.1arebased aroundTTL-typeinputs.Withtheintroductionof1149.1intoLVDS there have been many hurdlestoovercome.One issueisthatTTL inputsand outputsdo notrequirebiascircuitsand arealwayson when power isapplied.Inthecase ofLVDS, therearemany circuitsrequiredtomake theinputs and outputsachievetheirtighttolerances.These circuitsrequiresettletimeonce power isappliedtoensurethey functionproperly.These circuitsare alsothe largestusers of power withinthe device.To reduce power in standby,these deviceshave a PWRDN pin to shut these circuitsdown. There is also a REN pin that enables/disablestheTTL outputs.

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 In the case of the 1149.1 functionality,these circuitsneed appropriatetime to stabilizebeforethey can be utilized.To achievestability,thesecircuitsare powered up when theTAP controllerstatemachine isnotinthe Test-Logic-Resetstate.The timethatittakesa TAP totraversefromTest-Logic-ResettoCapture-Data-Register runningat25MHz issufficienttoallowthesecircuitstostabilize. Once theTAP has leftTest-Logic-Reset,theinternalvalueofPWRDN isoverriddenand thedeviceispowered up.Thisincludesallforementionedcircuitsas wellas alloutputs.Ifan applicationrequiresthattheoutputsare toremaindisabledduring1149.1test,use REN and notPWRDN. KNOWN ERRATA: On theSCAN921260 onlytheoverriddenvalueofPWRDN ("1")iscapturedduringall1149.1 testsand nottheexternalvalueas seen on thepin. BIST ALONE TEST MODES The SCAN921260 also supportsa BIST Alone featurewhich can be run withoutenablingthe JTAG TAP controller.ThisfeatureprovidestheabilitytoruncontinuosBER testingon allchannels,oron individualchannels withoutaffectinglivetrafficon otherchannels.The abilitytoruntheBERT whileadjacentchannelsarecarrying normaltrafficisa usefultooltodeterminehow normaltrafficwillaffectBER on any givenchannel. The BIST Alone featurescan be accessed usingthe 5 pinsdefinedas BIST_SEL0, BIST_SEL1, BIST_SEL2, BIST_ACT, and BISTMODE_REQ. BIST_ACT activatesthe BIST Alone mode. The BIST Alone mode willcontinueuntildeactivatedby the BIST_ACT pin.The BIST_ACT inputmust be highor low for4 or more clockcyclesinorderto activateor deactivatetheBIST Alonemode. The BIST_ACT inputispulledlowinternally. BISTMODE_REQ isused toselecteithergrosserrorreportingor a specificoutputerrorreport.When theBIST Alone mode isactive,the LOCK(1:6) outputforallchannelsrunningBIST Alone willgo low,and ROUT(0:9) reportsany error.When BISTMODE_REQ islow theerrorreportingissettoGross Mode, and whenever a bit containsone or more errors,ROUT(0:9) forthatchannelgoes high and stayshigh untildeactivationby the BIST_ACT input.When BISTMODE_REQ ishigh,theoutputerrorreportingissettoBitErrormode. Whenever any databitcontainsan error,thedataoutputforthatcorrespondingbitgoes high.The defaultisGross Error mode. The threeBIST_SELn inputsdeterminewhichchannelisinBIST Alonemode accordingtothefollowingtable: Table1.BIST Alone Mode Selection BIST_ACT BIST_SEL2 BIST_SEL1 BIST_SEL0 BIST forChannel 1 0 0 0 0 1 0 0 1 1 1 0 1 0 2 1 0 1 1 3 1 1 0 0 4 1 1 0 1 5 1 1 1 0 AllChannels 1 1 1 1 IDLE

0 X X X IDLE

An allCMOS designoftheDeserializermakes itan inherentlylowpower device. POWERING UP THE DESERIALIZER The SCAN921260 can be powered up atany timeby followingthepropersequence.The REFCLK inputcan be runningbeforetheDeserializerpowers up,and itmust be runninginorderfortheDeserializertolocktoincoming data.The DeserializeroutputswillremaininTri-stateuntiltheDeserializerdetectsdatatransmissionatitsinputs and lockstotheincomingdatastream. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com TRANSMITTING DATA Once you power up theDeserializer,itmust be phase lockedtothetransmittertotransmitdata.Phase locking occurswhen theDeserializerlockstoincomingdataor when theSerializersends sync patterns.The Serializer sends SYNC patternswhenever theSYNC1 or SYNC2 inputsare high.The LOCKn outputoftheDeserializer remainshighuntilithas lockedtotheincomingdatastream.ConnectingtheLOCKn outputoftheDeserializerto one oftheSYNC inputsoftheSerializerwillensurethatenough SYNC patternsaresenttoachieveDeserializer lock. The Deserializercan alsolocktoincomingdataby simplypoweringup thedeviceand allowingthe“random lock” circuitrytofindand locktothedatastream. WhiletheDeserializerLOCKn outputislow,dataattheDeserializeroutputs(ROUT0-9) arevalid,exceptforthe specificcase of lossof lockduringtransmissionwhich isfurtherdiscussedin RECOVERING FROM LOCK LOSS . NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyreceivedata.Variousenvironmentaland systematicfactorsinclude:

Serializer:TCLK jitter,VCC noise(noisebandwidthand out-of-bandnoise)
Media:ISI,LargeVCM shifts
Deserializer:VCC noise RECOVERING FROM LOCK LOSS Inthecase where theDeserializerloseslockduringdatatransmission,up to1 cycleofdatathatwas previously receivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuitrequiresthat invalidclockinformationbe received2 timesina row toindicatelossoflock.Sinceclockinformationhas been lost,itispossiblethatdata was alsolostduringthesecycles.Therefore,afterthe Deserializerrelocksto the incomingdata stream and the DeserializerLOCKn pingoes low,at leastone previousdata cycleshouldbe suspectforbiterrors. The Deserializercan relockto the incomingdata stream by making the Serializerresend SYNC patterns,as describedabove, or by random locking,which can take more time,depending on the data patternsbeing received. HOT INSERTION AlltheBusLVDS devicesare hotpluggableifyou followa few rules.When inserting,ensuretheGround pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround.Random lockhotinsertionisillustratedinFigure11. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboard layoutand stack-upfortheSCAN921260 shouldbe designedtoprovidenoise-freepower tothe device.Good layoutpracticewillseparatehighfrequencyorhighlevelinputsand outputstominimizeunwanted straynoisepickup,feedbackand interference.There are a few common practiceswhich shouldbe followed when designingPCB's forBus LVDS Signaling.Recommended layoutpracticesare:
Use atleast4 PCB boardlayers(BusLVDS signals,ground,power,and TTL signals). – Power system performance may be greatlyimproved by using thindielectrics(4 to 10 mils)for power/groundsandwiches.This increasesthe intrinsiccapacitanceof the PCB power system which improvespower supplyfiltering,especiallyat highfrequencies,and makes the valueand placementof externalbypasscapacitorslesscritical.
Keep Serializersand Deserializersas closetothe(BusLVDS portside)connectoras possible. – Longerstubslowertheimpedance ofthebus,increasetheloadon theSerializer,and lowerthethreshold margin at the Deserializers.Deserializerdevicesshouldbe placedmuch lessthan one inchfrom slot connectors.Because transitiontimesare veryfaston the SerializerBus LVDS outputs,reducingstub lengthsas much as possibleisthebestmethod toensuresignalintegrity.
Bypass each Bus LVDS deviceand alsouse distributedbulkcapacitancebetween power planes.

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 – Surfacemount capacitorsplacedclosetopower and ground pinswork best.Externalbypass capacitors shouldincludeboth RF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused.Randomly distributedby- pass capacitorsshouldalsobe used. – Package and pinlayoutpermitting,itisalsorecommended touse two viasateach power pinas wellas all RF bypasscapacitorterminals.Dualviasreducetheinterconnectinductancebetween layersby up tohalf, therebyreducinginterconnectinductanceand extendingthe effectivefrequencyrange of the bypass components.

Leave unused Bus LVDS receiverinputsopen (floating).
IsolateTTL signalsfromBus LVDS signals. There aremore common practiceswhichshouldbe followedwhen designingPCBs forBLVDS/LVDS signaling. General applicationguidelinesare availablein the LVDS Owner's Manual, which may be found at www.ti.com/ww/en/analog/interface/lvds.shtml. For packaging informationon BGA's, please see AN- 1126(SNOA021 ) TRANSMISSION MEDIA The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurations,throughPCB trace,orthrough twistedpaircable.In point-to-pointconfigurations,the transmissionmedia need only be terminatedat the receiverend.Pleasenotethatinpoint-to-pointconfigurations,thepotentialofoffsettingthegroundlevelsofthe Serializervs.theDeserializermust be considered.Also,Bus LVDS providesa +/− 1.2V common mode rangeat thereceiverinputs. FAILSAFE BIASING FOR THE SCAN921260 The SCAN921260 has internalfailsafebiasingand an improvedinputthresholdsensitivityof+/− 50mV versus +/− 100mV forthe DS92LV1210 or DS92LV1212. This allowsforgreaterdifferentialnoise margin in the SCAN921260. However, incases where thereceiverinputisnotbeingactivelydriven,theincreasedsensitivity oftheSCAN921260 can pickupnoiseas a signaland cause unintentionallocking.For example,thiscan occur when theinputcableisdisconnected. Externalresistorscan be added tothereceivercircuitboardtopreventnoisepick-up.Typically,thenon-inverting receiverinputispulledup and theinvertingreceiverinputispulleddown by highvalueresistors.The pull-upand pull-downresistors(R1 and R 2) providea currentpath throughthe terminationresistor(RL) which biasesthe receiverinputswhen theyarenotconnectedtoan activedriver.The valueofthepull-upand pull-downresistors shouldbe chosen so thatenough currentisdrawn to providea +15mV drop acrossthe terminationresistor. Pleasesee Figure9 fortheFailsafeBiasingSetup. The parametertRNM iscalculatedby firstmeasuringhow much of the idealbitthe receiverneeds to ensure correctsampling.Afterdeterminingthisamount, what remains of the idealbitthatisavailableforexternal sourcesofnoiseiscalledtRNM .ItistheoffsetfromtDJIT(minor max) forthetestmask withintheeye opening. The verticallimitsofthemask aredeterminedby theSCAN921260 receiverinputthresholdof+/− 50mV. Pleaserefertotheeye mask patternofFigure10 fora graphicrepresentationoftDJIT and tRNM . Figure9. FailsafeBiasingSetup Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Figure10. DeterministicJitterand idealBitPosition tRNMI-L istheidealnoisemarginon theleftofthefigure,itisa negativevaluetoindicateearlywithrespecttoideal. tRNMI-R istheidealnoisemarginon therightoftheabove figure,itisa positivevaluetoindicatelatewithrespectto ideal. Figure11. IdealDeserializerNoise Margin (tRNMI )and Sampling Window

14 SubmitDocumentationFeedback Copyright© 2001–2013,Texas InstrumentsIncorporated

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 PIN DIAGRAM Figure12. SCAN921260UJB and SCAN921260UJBX (196pinNFBGA) Table2.PIN DESCRIPTIONS Pin Name Type Pins Description These pinscontrolwhichBus LVDS inputis steeredtotheCHTST output.The ControlPins TruthTabledescribestheirfunction.Thereare weak internalpull-upsthatshoulddefaultall SEL(0:2)tohigh.Forexample,ifyou chooseCMOSSEL (0:2) B13,C12, C13 nottouse ChannelTestMode and want theInput CHTST outputpermanentlydisabled,you can tieSEL2 and SEL1 highand SEL0 low.Ina noisyoperatingenvironment,itis recommended thatan externalpullup be used toensurethatSELn isinthehighstate. Bus LVDS A4-A3,A7-A6,A10-A9,A13-A12,C6-C5,C9-Rin+/-n Bus LVDS differentialinputpinsInput C8, C11-C10, AGND A5,A8,B7,B8,B11 AnalogGround AVDD A11,B6,B9,C7 AnalogVoltageSupply A lowon thispinputsthedeviceintosleep mode and a highmakes thepartactive.ThereCMOSPWRDN B5 isan internalpull-downthatdefaultsPWRDN toInput sleepmode. Activeoperationrequiresasserting a highon PWRDN. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SCAN921260

SNLS139F –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Table2.PIN DESCRIPTIONS (continued) Pin Name Type Pins Description EnablestheRoutn and RCLKn outputs.There CMOS isan internalpull-downthatdefaultsREN totri-REN A2Input statetheoutputs.Activeoutputsrequire assertinga highon REN. CMOSREFCLK B4 Frequencyreferenceclockinput.Input CMOS Allowslowspeed testingoftheRininputsCHTST C3Output undercontroloftheSEL (0:2)pins. IndicatesthestatusofthePLLs fortheCMOSLOCK (0:5) F3,P1,N3, P12,P13,D13 individualdeserializers:LOCK= L indicatesOutput locked,LOCK= H indicatesunlocked. E2,E4,E12,E13,E14,F4,G3, G4, G11, G12, H2, H3, H4, H11, H12, J2,J3,J11,J12,K2, CMOS K3,K4,K12,K13,L1,L3,L6,L8,L9,L11,L12, Outputsforthetenbitdeserializers,n =Rout nx Output L13,L14,M1, M2, M3, M4, M5, M6, M7, M8, deserializernumber,x = bitnumber M9, M10, M11, M12, M14, N1, N2, N4, N6, N9, N11, N12, N13, N14, P2,P3,P4,P11,P14 CMOS Recoveredclockforeach deserializer'soutputRCLK (0:5) F2,F13,L2,M13, N5, N10Output data. B1,B3,C4, D6, D12, E6,E7,E9,E10,F7,F10, DVDD F12,G6, G10, H6, H10, J5,J8,J9,J10,K5, DigitalSupplyVoltage. K6,K7,K10,L10 A1,B2,B14,D4, D5, D7, D9, D11, E5,E8,F5, DGND F6,F9,G5, G7, G8, G9, H5, H7, H8, H9, J6, DigitalGround. J7,K8,K9,L7 E1,F1,F14,G14, J1,J14,K1,K14,P5,P6,PVDD PLL SupplyVoltage.P9,P10 A14,B12,D10, F8,G1, G2, G13, H1, H13,PGND PLL Ground.H14, J4,J13,N7, N8, P7,P8 CMOSTMS C1 TestMode SelectinputtosupportIEEE 1149.1Input CMOSTRST C2 TestResetInputtosupportIEEE 1149.1Input CMOSTDI D1 TestData InputtosupportIEEE 1149.1Input CMOSTCK D2 TestClocktosupportIEEE 1149.1Input CMOSTDO D3 TestData OutputtosupportTDOOutput CMOSBISTMODE_REQ B10 BIST AloneErrorReportingMode SelectInputInput These pinscontrolwhichchannelsareactive fortheBIST Aloneoperationmode. The BIST CMOS AloneMode SelectionTabledescribestheirBIST_SEL(0:2) C14, D8, D14Input function.Thereareinternalpull-upsthatdefault allBIST_SEL(0:2)tohigh,whichistheidle stateforallchannelsinBIST Alonemode. A highon thisinputenablestheCHTST output. Thereisan internalpull-upthatdefaultsthe CHTST outputtotheactivemode. Note:CMOSCHTST_EN E3 CHTEST_EN requirestwo clockcyclesbeforeInput CHTST isenabledordisabled.When notusing CHTST output,asserta lowon thiscontrolpin toreducepower consumption.

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www.ti.com SNLS139F –DECEMBER 2001–REVISED APRIL 2013 Table2.PIN DESCRIPTIONS (continued) Pin Name Type Pins Description A highon thispinactivatestheBIST Alone operatingmode. Thereisa weak internalpull- down thatshoulddefaulttheBIST_ACT tode- CMOS activatetheBIST Aloneoperatingmode. InaBIST_ACT K11Input noisyoperatingenvironment,itis recommended thatan externalpulldown be used toensurethatBIST_ACT isinthelow state. N/C E11,F11,L4,L5 Unused solderballlocation.Do notconnect. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SCAN921260

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REVISION HISTORY

Changes from RevisionE (April2013)toRevisionF Page

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www.ti.com 24-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SCAN921260UJB/NOPB ACTIVE NFBGA NZH 196 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 85 SCAN921260 UJB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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www.ti.com UJB196A (Rev C)

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