SCAN921260

SCAN921260 NSC | Alldatasheet

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n IEEE 1149.1 (JTAG) Compliant and at-speed BIST test modes n Deserializes one to six BusLVDS input serial data streams with embedded clocks n Seven selectable serial inputs to support n+1 redundancy of deserialized streams n Seventh channel has single pin monitor output that reflects input from seventh channel input n Parallel clock rate up to 66MHz n On chip filtering for PLL n High impedance inputs upon power off (V cc = 0V) n Single power supply at +3.3V n 196-pin LBGA package (Low-profile Ball Grid Array) package n Industrial temperature range operation: −40 to +85 Functional Block Diagram Typical Application 20014702 TRI-STATE® is a registered trademark of National Semiconductor Corporation. July 2004 SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST © 2004 National Semiconductor Corporation DS200147 www.national.com

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to +4V LVCMOS/LVTTL Input Voltage −0.3V to 3.9V LVCMOS/LVTTL Output Voltage −0.3V to 3.9V Bus LVDS Receiver Input Voltage −0.3V to 3.9V Bus LVDS Driver Output Voltage −0.3V to 3.9V Bus LVDS Output Short Circuit Duration 10ms Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 10 seconds) +225˚C Max Pkg Power Dissipation Capacity @ 25˚C 196L BGA 3.7 W Package Derating: 196L BGA 29.4 mW/˚C above +25˚C Thermal Resistance: θJA 34˚C/W θJC 8˚C/W ESD Rating: Human Body Model >2KV Machine Model >750V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Clock Rate 20 66 MHz Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified(Note 2) Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC Specifications: Applies to pins in Pin Description table with type CMOS Input or Output V IH High Level Input Voltage Input Pins 2.0 V CC V VIL Low Level Input Voltage Input Pins GND 0.8 V VCL Input Clamp Voltage Input Pins -0.87 -1.5 V IIN Input Current V in = 0 or 3.6V, Input Pins -20 +20 uA VOH High Level Output Voltage I OH = 6mA, Output Pins 2 3 V CC V VOL Low Level Output Voltage I OL = 6mA, Output Pins GND 0.18 0.4 V VOH High Level Output Voltage I OH = 12mA, TDO Output 2 3 V CC V VOL Low Level Output Voltage I OL = 12mA, TDO Output GND 0.18 0.4 V IOS Output short Circuit Current V out = 0V, Output Pins -15 -46 -85 mA IOS Output short Circuit Current V out = 0V, TDO Output -15 -120 mA IOZ TRI-STATE Output Current PD* or REN = 0.8V Vout =0 Vo rV CC -10 +/-0.2 +10 uA Bus LVDS DC specifications: Applies to pins in Pin Description table with type Bus LVDS Inputs V TH Differential Threshold High Voltage VCM = 1.1V (V RI+-VRI-) +3 +50 mV VTL Differential Threshold Low Voltage -50 -2 mV IIN Input Current Vin = +2.4V or 0V, Vcc = 3.6 or 0V -10 +/- 1 +10 uA Supply Current I CCR Worst Case Supply Current 3.6V, Checker Board Pattern, CL = 15pF, 66Mhz 600 660 mA ICCXR Supply Current when Powered Down PWRDN= 0.8V REN = 0.8V 0.36 1 mA SCAN921260 www.national.com 2

SCAN Circuitry Timing Requirements Symbol Parameter Conditions Min Typ Max Units fMAX Maximum TCK Clock Frequency RL = 500Ω,C L = 35 pF 25.0 50.0 MHz tS TDI to TCK, H or L 1.0 ns tH TDI to TCK, H or L 2.0 ns tS TMS to TCK, H or L 2.5 ns tH TMS to TCK, H or L 1.5 ns tW TCK Pulse Width, H or L 10.0 ns tW TRST Pulse Width, L 2.5 ns tREC Recovery Time, TRST to TCK 2.0 ns Block Diagram 20014701 SCAN921260 www.national.com 4

Note 8: The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2]. Note 9: LOCK Active indicates that the LOCK output will reflect the state of it’s respective Deserializer with regard to the selected data stream. Note 10: RCLK Active indicates that the RCLK will be running if the Deserializer is locked. Note 11: Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High. FIGURE 1. Deserializer Delay tDD

Application Information

USING THE SCAN921023 and SCAN921260 The SCAN921260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream up to 660 Mbps from National Semiconductor’s SCAN921023 Serializer. The deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the output. A seventh serial data input provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to any of the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL TEST (CHTST) pin on receiver output port. The Deserializer uses a separate refer- ence clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCKn output high when loss of lock occurs. Each of the 6 channels acts completely independent of each other. Each independent channel has outputs for a 10-bit wide data word, the recovered clock out, and the lock-detect output. The SCAN921260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition, there are two passive states: Powerdown and TRI-STATE. The following sections describe each operating mode and passive state. INITIALIZATION Before the SCAN921260 receives and deserializes data, it and the transmitting serializer devices must initialize the link. Initialization refers to synchronizing the Serializer’s and the Deserializer’s PLL’s to local clocks. The local clocks must be the same frequency or within a specified range if from differ- ent sources. After all devices synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step. Step 1: After applying power to the Deserializer, the outputs are held in TRI-STATE and the on-chip power-sequencing circuitry disables the internal circuits. When V cc reaches VccOK (2.1V), the PLL in each deserializer begins locking to the local clock (REFCLK). A local on-board oscillator or other source provides the specified clock input to the REFCLK pin. Step 2: The Deserializer PLL must synchronize to the Seri- alizer to complete the initialization. Refer to the Serializer data sheet for the proper operation during this step of the Initialization State. The Deserializer identifies the rising clock edge in a synchronization pattern or random data and after 80 clock cycles will synchronize to the data stream from the serializer. At the point where the Deserializer’s PLL locks to the embedded clock, the LOCKn pin goes low and valid data appears on the output. Note that this differs from previous deserializers where the LOCKn signal was not synchronous to valid data appearing on the outputs. DATA TRANSFER After initialization, the serializer transfers data to the deseri- alizers. The serial data stream includes a start and stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial ’payload’ rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 = 400 Mbps. TCLK is provided by the data source and must be in the range 20 MHz to 40 MHz nominal. When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low and synchronously delivers valid data on the output. The Dese- rializer locks to the embedded clock, uses it to generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn is synchronous to the data on the ROUT[n0:n9] pins. While LOCKn is low, data on ROUT [n0:n9] is valid. Otherwise, ROUT[n0:n9] is invalid. All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 66 MHz clock. This amount of drive allows bussing outputs of two Deseri- alizers and a destination ASIC. REN controls TRI-STATE of all the outputs. The Deserializer input pins are high impedance during Pow- erdown (PWRDN low) and power-off (V cc = 0V). RESYNCHRONIZATION Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the em- bedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven high. The system must monitor the LOCKn pin to determine when data is valid. The user has the choice of allowing the deserializer to re- synch to the data stream or to force synchronization by pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is left up to the user discretion. One recommendation is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are given for multiple control in a multi-drop application. POWERDOWN The Powerdown state is a low power sleep mode that the Serializer and Deserializer typically occupy while waiting for initialization, or to reduce power consumption when no data is transferred. The Deserializer enters Powerdown when PWRDN is driven low. In Powerdown, the PLL stops and the outputs go into TRI-STATE, which reduces supply current to the microamp range. To exit Powerdown, the system drives PWRDN high. Upon exiting Powerdown, the Deserializer enters the Initial- ization state. The system must then allow time to Initialize before data transfer can begin. TRI-STATETRI-STATE When the system drives REN pin low, the Deserializer enters TRI-STATE. This will TRI-STATE the receiver output pins (ROUT[00:59]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the previous state as long as all other control pins remain static (PWRDN). IEEE 1149.1 TEST MODES The SCAN921260 features interconnect test access that is compliant to the IEEE 1149.1 Standard for Boundary Scan Test (JTAG). All digital TTL I/O’s on the device are accessible using IEEE 1149.1, and entering this test mode will override SCAN921260 www.national.com 8

Application Information (Continued) all input control cases including PWRDN and REN. In addi- tion to the 4 required Test Access Port (TAP) signals of TMS, TCK, TDI, and TDO, TRST is provided for test reset. To supplement the test coverage provided by the IEEE 1149.1 test access to the digital TTL pins, the SCAN921260 has two instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at LVDS levels and is only intended as a go no-go test (e.g. missing cables). The sec- ond method is the RUNBIST instruction. It is an "at-system- speed" interconnect test. It is executed in approximately 33mS with a system clock speed of 66MHz. There are 12 bits in the RX BIST data register for notification of PASS/ FAIL and TEST_COMPLETE; two bits for each of the six channels. The RX BIST register is defined as (from MSB to LSB): [BIST COMPLETE for Channel 6, BIST PASS/FAIL for Channel 6, BIST COMPLETE for Channel 5, BIST PASS/ FAIL for Channel 5, BIST COMPLETE for Channel 4, BIST PASS/FAIL for Channel 4, BIST COMPLETE for Channel 3, BIST PASS/FAIL for Channel 3, BIST COMPLETE for Chan- nel 2, BIST PASS/FAIL for Channel 2, BIST COMPLETE for Channel 1, BIST PASS/FAIL for Channel 1] A "pass" indicates that the BER (Bit-Error-Rate) is better than 10 -7. This is a minimum test, so a "fail" indication means that the BER is higher than 10 -7. The BIST features of the SCAN921260 six (6) channel de- serializer are compatible with the BIST features on the SCAN921023 Serializer. An important detail is that once both devices have the RUN- BIST instruction loaded into their respective instruction reg- isters, both devices must move into the RTI state within 4K system clocks (At a system CLK of 66Mhz and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan chain or LSP, however, it can be a problem with some multi-drop devices. This test mode has been simulated and verified using National’s SCANSTA111. Typical applications of 1149.1 are based around TTL-type inputs. With the introduction of 1149.1 into LVDS there have been many hurdles to overcome. One issue is that TTL inputs and outputs do not require bias circuits and are al- ways on when power is applied. In the case of LVDS, there are many circuits required to make the inputs and outputs achieve their tight tolerances. These circuits require settle time once power is applied to ensure they function properly. These circuits are also the largest users of power within the device. To reduce power in standby, these devices have a PWRDN pin to shut these circuits down. There is also a REN pin that enables/disables the TTL outputs. In the case of the 1149.1 functionality, these circuits need appropriate time to stabilize before they can be utilized. To achieve stability, these circuits are powered up when the TAP controller state machine is not in the Test-Logic-Reset state. The time that it takes a TAP to traverse from Test- Logic-Reset to Capture-Data-Register running at 25MHz is sufficient to allow these circuits to stabilize. Once the TAP has leftTest-Logic-Reset, the internal value of PWRDN is overridden and the device is powered up. This includes all fore mentioned circuits as well as all outputs. If an application requires that the outputs are to remain dis- abled during 1149.1 test, use REN and not PWRDN. KNOWN ERRATA: On the SCAN921260 only the overridden value of PWRDN ("1") is captured during all 1149.1 tests and not the external value as seen on the pin. BIST ALONE TEST MODES The SCAN921260 also supports a BIST Alone feature which can be run without enabling the JTAG TAP controller. This feature provides the ability to run continuos BER testing on all channels, or on individual channels without affecting live traffic on other channels. The ability to run the BERT while adjacent channels are carrying normal traffic is a useful tool to determine how normal traffic will affect BER on any given channel. The BIST Alone features can be accessed using the 5 pins defined as BIST_SEL0, BIST_SEL1, BIST_SEL2, BIS- T_ACT, and BISTMODE_REQ. BIST_ACT activates the BIST Alone mode. The BIST Alone mode will continue until deactivated by the BIST_ACT pin. The BIST_ACT input must be high or low for 4 or more clock cycles in order to activate or deactivate the BIST Alone mode. The BIST_ACT input is pulled low internally. BISTMODE_REQ is used to select either gross error report- ing or a specific output error report. When the BIST Alone mode is active, the LOCK(1:6) output for all channels run- ning BIST Alone will go low, and ROUT(0:9) reports any error. When BISTMODE_REQ is low the error reporting is set to Gross Mode, and whenever a bit contains one or more errors, ROUT(0:9) for that channel goes high and stays high until deactivation by the BIST_ACT input. When BISTMOD- E_REQ is high, the output error reporting is set to Bit Error mode. Whenever any data bit contains an error, the data output for that corresponding bit goes high. The default is Gross Error mode. The three BIST_SELn inputs determine which channel is in BIST Alone mode according to the following table: SCAN921260 www.national.com9

Application Information (Continued) BIST Alone Mode Selection BIST_ACT BIST_SEL2 BIST_SEL1 BIST_SEL0 BIST for Channel 1 000 0 1 001 1 1 010 2 1 011 3 1 100 4 1 101 5 1 1 1 0 All Channels 1 1 1 1 IDLE

0 X X X IDLE

An all CMOS design of the Deserializer makes it an inher- ently low power device. POWERING UP THE DESERIALIZER The SCAN921260 can be powered up at any time by follow- ing the proper sequence. The REFCLK input can be running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the De- serializer detects data transmission at its inputs and locks to the incoming data stream. TRANSMITTING DATA Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to one of the SYNC inputs of the Serializer will guarantee that enough SYNC patterns are sent to achieve Deserializer lock. The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock” circuitry to find and lock to the data stream. While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss" sec- tion below. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data. Various environmental and systematic factors include: Serializer: TCLK jitter, V CC noise (noise bandwidth and out-of-band noise) Media: ISI, Large V CM shifts Deserializer: VCC noise RECOVERING FROM LOCK LOSS In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. There- fore, after the Deserializer relocks to the incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be suspect for bit errors. The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as described above, or by random locking, which can take more time, depending on the data patterns being received. HOT INSERTION All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 10. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the SCAN921260 should be designed to provide noise-free power to the de- vice. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. There are a few common practices which should be followed when designing PCB’s for Bus LVDS Signaling. Recommended layout prac- tices are:  Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals). Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical.  Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible. Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity. SCAN921260 www.national.com 10

bulk capacitance between power planes. be at least 5X the power supply voltage being used. the effective frequency range of the bypass components.  Leave unused Bus LVDS receiver inputs open (floating).  Isolate TTL signals from Bus LVDS signals. on BGA’s, please see AN-1126. 1.2V common mode range at the receiver inputs. mask within the eye opening. SCAN921260 receiver input threshold of +/− 50mV. representation of tDJIT and tRNM. FIGURE 8. Failsafe Biasing Setup

SCAN921260UJB and SCAN921260UJBX (196 pin LBGA) 20014714 SCAN921260 www.national.com13

Pin Name Type Pins Description SEL (0:2) CMOS Input B13, C12, C13 These pins control which Bus LVDS input is steered to the CHTST output. The Control Pins Truth Table describes their function. There are weak internal pull-ups that should default all SEL(0:2) to high. For example, if you choose not to use Channel Test Mode and want the CHTST output permanently disabled, you can tie SEL2 and SEL1 high and SEL0 low. In a noisy operating environment, it is recommended that an external pull up be used to ensure that SELn is in the high state. Rin +/- n Bus LVDS Input A4-A3, A7-A6, A10-A9, A13-A12, C6-C5, C9-C8, C11-C10, Bus LVDS differential input pins AGND A5, A8, B7, B8, B11 Analog Ground AVDD A11, B6, B9, C7 Analog Voltage Supply PWRDN CMOS Input B5 A low on this pin puts the device into sleep mode and a high makes the part active. There is an internal pull-down that defaults PWRDN to sleep mode. Active operation requires asserting a high on PWRDN. REN CMOS Input A2 Enables the Routn and RCLKn outputs. There is an internal pull-down that defaults REN to TRI-STATE the outputs. Active outputs require asserting a high on REN. REFCLK CMOS Input B4 Frequency reference clock input. CHTST CMOS Output C3 Allows low speed testing of the Rin inputs under control of the SEL (0:2) pins. LOCK (0:5) CMOS Output F3, P1, N3, P12, P13, D13 Indicates the status of the PLLs for the individual deserializers: LOCK= L indicates locked, LOCK= H indicates unlocked. Rout nx CMOS Output E2, E4, E12, E13, E14, F4, G3, G4, G11, G12, H2, H3, H4, H11, H12, J2, J3, J11, J12, K2, K3, K4, K12, K13, L1, L3, L6, L8, L9, L11, L12, L13, L14, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M14, N1, N2, N4, N6, N9, N11, N12, N13, N14, P2, P3, P4, P11, P14 Outputs for the ten bit deserializers, n = deserializer number, x = bit number RCLK (0:5) CMOS Output F2, F13, L2, M13, N5, N10 Recovered clock for each deserializer’s output data. DVDD B1, B3, C4, D6, D12, E6, E7, E9, E10, F7, F10, F12, G6, G10, H6, H10, J5, J8, J9, J10, K5, K6, K7, K10, L10 Digital Supply Voltage. DGND A1, B2, B14, D4, D5, D7, D9, D11, E5, E8, F5, F6, F9, G5, G7, G8, G9, H5, H7, H8, H9, J6, J7, K8, K9, L7 Digital Ground. PVDD E1, F1, F14, G14, J1, J14, K1, K14, P5, P6, P9, P10 PLL Supply Voltage. PGND A14, B12, D10, F8, G1, G2, G13, H1, H13, H14, J4, J13, N7, N8, P7, P8 PLL Ground. SCAN921260 www.national.com 14

Pin Descriptions (Continued) Pin Name Type Pins Description TMS CMOS Input C1 Test Mode Select input to support IEEE 1149.1 TRST CMOS Input C2 Test Reset Input to support IEEE 1149.1 TDI CMOS Input D1 Test Data Input to support IEEE 1149.1 TCK CMOS Input D2 Test Clock to support IEEE 1149.1 TDO CMOS Output D3 Test Data Output to support TDO BISTMODE_REQ CMOS Input B10 BIST Alone Error Reporting Mode Select Input BIST_SEL(0:2) CMOS Input C14, D8, D14 These pins control which channels are active for the BIST Alone operation mode. The BIST Alone Mode Selection Table describes their function. There are internal pull-ups that default all BIST_SEL(0:2) to high, which is the idle state for all channels in BIST Alone mode. CHTST_EN CMOS Input E3 A high on this input enables the CHTST output. There is an internal pull-up that defaults the CHTST output to the active mode. Note: CHTEST_EN requires two clock cycles before CHTST is enabled or disabled. When not using CHTST output, assert a low on this control pin to reduce power consumption. BIST_ACT CMOS Input K11 A high on this pin activates the BIST Alone operating mode. There is a weak internal pull-down that should default the BIST_ACT to de-activate the BIST Alone operating mode. In a noisy operating environment, it is recommended that an external pull down be used to ensure that BIST_ACT is in the low state. N/C E11, F11, L4, L5 Unused solder ball location. Do not connect. SCAN921260 www.national.com15

Physical Dimensions inches (millimeters) unless otherwise noted Order Number SCAN921260UJB (Tray) Order Number SCAN921260UJBX (Tape and Reel) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.