SCAN921226H

SCAN921025H NSC | Alldatasheet

Document overview

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Technical content

Features

n High Temperature Operation to 125˚C n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. n Clock recovery from PLL lock to random data patterns. n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption< 600 mW (typ) @ 80 MHz n Single differential pair eliminates multi-channel skew n 800 Mbps serial Bus LVDS data rate (at 80 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits n Synchronization mode and LOCK indicator n Programmable edge trigger on clock n High impedance on receiver inputs when power is off n Bus LVDS serial output rated for 27Ω load n Small 49-lead BGA package Block Diagrams 20120701 October 2004 SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit BLVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST © 2004 National Semiconductor Corporation DS201207 www.national.com

Block Diagrams (Continued) Application 20120702 Functional Description The SCAN921025H and SCAN921226H are a 10-bit Serial- izer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 20 to 80 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable. The chipset has three active states of operation: Initializa- tion, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE. In addition to the active and passive states, there are also test modes for JTAG access and at-speed BIST. The following sections describe each operation and passive state and the test modes. Initialization Initialization of both devices must occur before data trans- mission begins. Initialization refers to synchronization of the Serializer and Deserializer PLL’s to local clocks, which may be the same or separate. Afterwards, synchronization of the Deserializer to Serializer occurs. Step 1: When you apply V CC to both Serializer and/or Dese- rializer, the respective outputs enter TRI-STATE, and on-chip power-on circuitry disables internal circuitry. When V CC reaches VCCOK (2.5V) the PLL in each device begins lock- ing to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin. The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the input clock rate. Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC patterns on the input. Step 2: The Deserializer PLL must synchronize to the Seri- alizer to complete initialization. The Deserializer will lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock to the Seri- alizer signal within a specified time. SeeFigure 16. The user’s application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low. When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low, the Deserializer outputs represent incoming Bus LVDS data. Data Transfer After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge. After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO ±) at 12 times the TCLK frequency. For example, if TCLK is 80 MHz, the serial rate is 80 x 12 = 960 Mega-bits-per-second. Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if TCLK = 80 MHz, the pay- load data rate is 80 x 10 = 800 Mbps. The data source provides TCLK and must be in the range of 20 MHz to 80 MHz nominal. The Serializer outputs (DO ±) can drive a point-to-point con- nection or in limited multi-point or multi-drop backplanes. The outputs transmit data when the enable pin (DEN) is SCAN921025H and SCAN921226H www.national.com 2

Data Transfer (Continued) high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE. When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0–ROUT9 is invalid. The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled by the RCLK_R/F input. SeeFigure 13. ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 80 MHz clock. Resynchronization When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the Dese- rializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE. The user’s system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for mul- tiple control in a multi-drop application. Sending sync pat- terns for resynchronization is desirable when lock times within a specific time are critical. However, the Deserializer can lock to random data, which is discussed in the next section. Random Lock Initialization and Resynchronization The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer. However, the SCAN921226H can attain lock to a data stream without requiring the Serializer to send special SYNC patterns. This allows the SCAN921226H to operate in “open-loop” applica- tions. Equally important is the Deserializer’s ability to support hot insertion into a running backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time. However, please seeTable 1for some general random lock times under specific conditions. The primary constraint on the “random” lock time is the initial phase relation be- tween the incoming data and the REFCLK when the Dese- rializer powers up. As described in the next paragraph, the data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than one Low- High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN 9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the Deserializer could become locked to the data pattern rather than the clock. Circuitry within the SCAN921226H can detect that the possibility of “false lock” exists. The circuitry accomplishes this by detect- ing more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock bits in the serial data stream. Graphical representations of RMT are shown inFigure 1. Please note that RMT only applies to bits DIN0-DIN8. Powerdown When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the Powerdown state, a low power sleep mode, to reduce power consump- tion. The Deserializer enters Powerdown when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In Powerdown, the PLL stops and the outputs enter TRI-STATE, which disables load cur- rent and reduces supply current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high. Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the de- vices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and assert LOCK high until lock to the Bus LVDS clock occurs. TRI-STATE The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. TABLE 1. Random Lock Times for the SCAN921226H

80 MHz Units

Maximum 18 µs Mean 3.0 µs Minimum 0.43 µs Conditions: PRBS 2 15,V CC = 3.3V 1) Difference in lock times are due to different starting points in the data pattern with multiple parts. Test Modes In addition to the IEEE 1149.1 test access to the digital TTL pins, the SCAN921025H and SCAN921226H have two in- structions to test the LVDS interconnects. The first is EX- TEST. This is implemented at LVDS levels and is only in- tended as a go no-go test (e.g. missing cables). The second method is the RUNBIST instruction. It is an "at-system- speed" interconnect test. It is executed in approximately 28mS with a system clock speed of 80MHz. There are two bits in the RX BIST data register for notification of PASS/ FAIL and TEST_COMPLETE. Pass indicates that the BER (Bit-Error-Rate) is better than 10 -7. An important detail is that once both devices have the RUN- BIST instruction loaded into their respective instruction reg- isters, both devices must move into the RTI state within 4K SCAN921025H and SCAN921226H www.national.com3

Test Modes (Continued) system clocks (At a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan chain or LSP , however, it can be a problem with some multi-drop devices. This test mode has been simulated and verified using National’s SCAN- STA111.

Ordering Information

SCAN921025HSM Serializer SLC49a SCAN921226HSM Deserializer SLC49a 20120724 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern 20120725 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern 20120726 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output

Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) −0.3V to +4V LVCMOS/LVTTL Input Voltage −0.3V to (V CC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (V CC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.9V Bus LVDS Driver Output Voltage −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10mS Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) +220˚C Maximum Package Power Dissipation Capacity @ 25˚C Package: 49L BGA 1.47 W Package Derating: 49L BGA 11.8 mW/˚C above +25˚C θja 85˚C/W ESD Rating HBM >2kV MM > 250V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +125 ˚C Receiver Input Range 0 2.4 V Supply Noise Voltage (VCC) 100 mV P-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA -0.86 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±1 +10 µA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins ROUT, RCLK, LOCK = outputs) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −0.62 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±1 +15 µA VOH High Level Output Voltage I OH = −9 mA 2.2 3.0 V CC V VOL Low Level Output Voltage I OL = 9 mA GND 0.25 0.5 V IOS Output Short Circuit Current VOUT = 0V −15 −47 −85 mA IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, V OUT =0 Vo rV C C −10 ±0.1 +10 µA SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−) V OD Output Differential Voltage (DO+)–(DO−) R L=2 7Ω, Figure 17 200 290 mV ∆VOD Output Differential Voltage Unbalance 35 mV VOS Offset Voltage 1.05 1.1 1.3 V ∆VOS Offset Voltage Unbalance 4.8 35 mV IOS Output Short Circuit Current D0 = 0V, DIN = High,PWRDN and DEN = 2.4V −56 −90 mA IOZ TRI-STATE Output Current PWRDN or DEN = 0.8V, DO = 0V or VCC −10 ±1 +10 µA IOX Power-Off Output Current VCC = 0V, DO=0V or 3.6V −20 ±1 +30 µA SCAN921025H and SCAN921226H www.national.com5

Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) VTH Differential Threshold High Voltage VCM = +1.1V +6 +50 mV VTL Differential Threshold Low Voltage −50 −12 mV I IN Input Current V IN = +2.4V, VCC = 3.6V or 0V −10 ±1 +10 µA VIN = 0V, VCC = 3.6V or 0V −10 ±0.05 +10 µA SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCD Serializer Supply Current RL = 27 Ω f = 20 MHz 45 60 mA Worst Case Figure 2 f = 80 MHz 90 105 mA ICCXD Serializer Supply Current Powerdown PWRDN = 0.8V, f = 80MHz 0.2 2.0 mA DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCR Deserializer Supply Current C L = 15 pF f = 20 MHz 50 75 mA Worst Case Figure 3 f = 80 MHz 100 120 mA ICCXR Deserializer Supply Current Powerdown PWRDN = 0.8V, REN = 0.8V 0.36 1.0 mA SCAN CIRCUITRY DC SPECIFICATIONS, SERIALIZER AND DESERIALIZER (applies to SCAN pins as noted) VIH High Level Input Voltage V CC = 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST 2.0 V CC V VIL Low Level Input Voltage V CC = 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST GND 0.8 V VCL Input Clamp Voltage V CC = 3.0V, ICL = −18 mA, pins TCK, TMS, TDI, and TRST −0.85 −1.5 V IIH Input Current V CC = 3.6V, VIN = 3.6V, pins TCK, TMS, TDI, and TRST 1 +10 µA IIL Input Current V CC = 3.6V, VIN = 0.0V, TCK Input -10 -1 µA IILR Input Current V CC = 3.6V, VIN = 0V, pins TMS, TDI, and TRST -20 -10 µA VOH High Level Output Voltage V CC = 3.0V, IOH = −12 mA, TDO output 2.2 2.6 V VOL Low Level Output Voltage V CC = 3.0V, IOL = 12 mA, TDO output 0.3 0.5 V IOS Output Short Circuit Current V CC = 3.6V, VOUT = 0.0V, TDO output -15 -90 -120 mA IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, V OUT =0 Vo rV C C −10 0 +10 µA Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period 12.5 T 50.0 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 36 n s tJIT TCLK Input Jitter 150 ps (RMS) Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tLLHT Bus LVDS Low-to-High Transition Time RL =2 7Ω CL=10pF to GND Figure 4 (Note 4) 0.2 0.4 ns t LHLT Bus LVDS High-to-Low Transition Time 0.25 0.4 ns SCAN921025H and SCAN921226H www.national.com 6

Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. FIGURE 17. VOD Diagram

Application Information

USING THE SCAN921025H AND SCAN921226H The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of parallel LVTTL data over a serial Bus LVDS link up to 800 Mbps. An on-board PLL serializes the input data and embeds two clock bits within the data stream. The Deserializer uses a separate reference clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and as- serts the LOCK output high when loss of lock occurs. POWER CONSIDERATIONS An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. In addition, the constant current source nature of the Bus LVDS outputs minimizes the slope of the speed vs. I CC curve of conventional CMOS designs. POWERING UP THE DESERIALIZER The SCAN921226H can be powered up at any time by following the proper sequence. The REFCLK input can be running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to the incoming data stream. TRANSMITTING DATA Once you power up the Serializer and Deserializer, they must be phase locked to each other to transmit data. Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends patterns. The Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCK output of the Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCK output of the Deserializer to one of the SYNC inputs of the Serializer will guarantee that enough SYNC patterns are sent to achieve Deserializer lock. The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock” circuitry to find and lock to the data stream. While the Deserializer LOCK output is low, data at the De- serializer outputs (ROUT0-9) is valid, except for the specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss" section be- low. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data. Various environmental and systematic factors include: Serializer: TCLK jitter, V CC noise (noise bandwidth and out-of-band noise) Media: ISI, Large VCM shifts Deserializer: VCC noise RECOVERING FROM LOCK LOSS In the case where the Deserializer loses lock during data transmission, up to 3 cycles of data that were previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 4 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. There- fore, after the Deserializer relocks to the incoming data stream and the Deserializer LOCK pin goes low, at least three previous data cycles should be suspect for bit errors. The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as described above, or by random locking, which can take more time, depending on the data patterns being received. HOT INSERTION All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes con- tact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illus- trated in Figure 21. PCB CONSIDERATIONS The Bus LVDS Serializer and Deserializer should be placed as close to the edge connector as possible. In multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to the Serializer driving the backplane traces. Longer stubs lower the imped- ance of the bus, increase the load on the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity. TRANSMISSION MEDIA The Serializer and Deserializer can also be used in point-to- point configuration of a backplane, through a PCB trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be terminated at the receiver end. Please note that in point-to-point configuration, the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS pro- vides a +/− 1.2V common mode range at the receiver inputs. FAILSAFE BIASING FOR THE SCAN921226H The SCAN921226H has an improved input threshold sensi- tivity of +/− 50mV versus +/− 100mV for the DS92LV1210 or DS92LV1212. This allows for greater differential noise mar- gin in the SCAN921226H. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the SCAN921226H can pickup noise as a sig- nal and cause unintentional locking. For example, this can occur when the input cable is disconnected. External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. the pull-up and pull-down resistors (R 1 and R2) provide a current path through the termination resistor (RL) which biases the receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor. Please seeFigure 18 for the Failsafe Biasing Setup. SCAN921025H and SCAN921226H www.national.com15

SCAN921025HSM - Serializer (Top View) 20120730 SCAN921226HSM - Deserializer (Top View) 20120731 SCAN921025H and SCAN921226H www.national.com 18

Serializer Pin Descriptions Pin Name I/O Ball Id. Description DIN I A3, B1, C1, D1, D2, D3, E1, E2, F2, F4 Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. TCLKR/F I G3 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge. Low selects falling edge. DO+ O D7 + Serial Data Output. Non-inverting Bus LVDS differential output. DO− O D5 − Serial Data Output. Inverting Bus LVDS differential output. DEN I D6 Serial Data Output Enable. LVTTL level input. A low puts the Bus LVDS outputs in TRI-STATE. PWRDN I C7 Powerdown. LVTTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs putting the device into a low power sleep mode. TCLK I E4 Transmit Clock. LVTTL level input. Input for 20MHz – 80MHz system clock. SYNC I A4, B3 Assertion of SYNC (high) for at least 1024 synchronization symbols to be transmitted on the Bus LVDS serial output. Synchronization symbols continue to be sent if SYNC continues to be asserted. TTL level input. The two SYNC pins are ORed. DVCC I C3, C4, E5 Digital Circuit power supply. DGND I A1, C2, F5, E6, G4 Digital Circuit ground. AVCC I A5, A6, B4, B7, G5 Analog power supply (PLL and Analog Circuits). AGND I B5, B6, C6, E7, F7 Analog ground (PLL and Analog Circuits). TDI I F1 Test Data Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. TDO O G1 Test Data Output to support IEEE 1149.1 TMS I E3 Test Mode Select Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. TCK I F3 Test Clock Input to support IEEE 1149.1 TRST I G2 Test Reset Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. N/C N/A A2, A7, B2, C5, D4, F6, G6, G7 Leave open circuit, do not connect SCAN921025H and SCAN921226H www.national.com19

Deserializer Pin Descriptions Pin Name I/O Ball Id. Description ROUT O A5, B4, B6, C4, C7, D6, F5, F7, G4, G5 Data Output. ±9 mA CMOS level outputs. RCLKR/F I B3 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I D2 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I C1 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I D3 Powerdown. TTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs putting the device into a low power sleep mode. LOCK O E1 LOCK goes low when the Deserializer PLL locks onto the embedded clock edge. CMOS level output. Totem pole output structure, does not directly support wired OR connections. RCLK O E2 Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT, CMOS level output. REN I D1 Output Enable. TTL level input. When driven low, TRI-STATEs ROUT0–ROUT9 and RCLK. DVCC I A7, B7, C5, C6, D5 Digital Circuit power supply. DGND I A1, A6, B5, D7, E4, E7, Digital Circuit ground. AVCC I B1, C2, F1, F2, G1 Analog power supply (PLL and Analog Circuits). AGND I A4, B2, F3, F4, G2 Analog ground (PLL and Analog Circuits). REFCLK I A3 Use this pin to supply a REFCLK signal for the internal PLL frequency. TDI I F6 Test Data Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. TDO O G6 Test Data Output to support IEEE 1149.1 TMS I G7 Test Mode Select Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. TCK I E5 Test Clock Input to support IEEE 1149.1 TRST I E6 Test Reset Input to support IEEE 1149.1. There is an internal pullup resistor that defaults this input to high per IEEE 1149.1. N/C N/A A2, C3, D4, E3 Leave open circuit, do not connect Deserializer Truth Table INPUTS OUTPUTS PWRDN REN ROUT [0:9] LOCK RCLK H (4) H Z H Z H H Active L Active LX Z Z Z H L Z Active Z 1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream. 2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F. 3) ROUT and RCLK are TRI-STATED when LOCK is asserted High. 4) During Power-up. SCAN921025H and SCAN921226H www.national.com 20

Physical Dimensions inches (millimeters) unless otherwise noted Order Number SCAN921025HSM or SCAN921226HSM National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit BLVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

Summary

High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

Description

High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

Source title SCAN921226H Datasheet(PDF) - National Semiconductor (TI)

Read SCAN921226H online.