SCAN921224

SCAN921023 NSC | Alldatasheet

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Technical content

Features

n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. n Clock recovery from PLL lock to random data patterns. n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption< 500 mW (typ) @ 66 MHz n Single differential pair eliminates multi-channel skew n Flow-through pinout for easy PCB layout n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits n Synchronization mode and LOCK indicator n Programmable edge trigger on clock n High impedance on receiver inputs when power is off n Bus LVDS serial output rated for 27Ω load n Small 49-lead BGA package Block Diagrams DS200001-1 April 2001 SCAN921023/SCAN921224 20-66 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST © 2001 National Semiconductor Corporation DS200001 www.national.com

Block Diagrams (Continued) Functional Description The SCAN921023 and SCAN921224 are a 10-bit Serializer and Deserializer chipset designed to transmit data over dif- ferential backplanes at clock speeds from 20 to 66 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable. The chipset has three active states of operation: Initializa- tion, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE. In addition to the active and passive states, there are also test modes for JTAG access and at-speed BIST. The following sections describe each operation and passive state and the test modes. Initialization Initialization of both devices must occur before data trans- mission begins. Initialization refers to synchronization of the Serializer and Deserializer PLL’s to local clocks, which may be the same or separate. Afterwards, synchronization of the Deserializer to Serializer occurs. Step 1: When you apply V CC to both Serializer and/or Dese- rializer, the respective outputs enter TRI-STATE, and on-chip power-on circuitry disables internal circuitry. When V CC reaches VCC OK (2.5V) the PLL in each device begins lock- ing to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin. The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the input clock rate. Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC patterns on the input. Step 2: The Deserializer PLL must synchronize to the Seri- alizer to complete initialization. The Deserializer will lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock to the Seri- alizer signal within a specified time. See Figure 9. The user’s application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low. When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low, the Deserializer outputs represent incoming Bus LVDS data. Data Transfer After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge. After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO ±) at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 x 12 = 792 Mega-bits-per-second. Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz, the pay- load data rate is 66 x 10 = 660 Mbps. The data source provides TCLK and must be in the range of 20 MHz to 66 MHz nominal. The Serializer outputs (DO ±) can drive a point-to-point con- nection or in limited multi-point or multi-drop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE. When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded Application DS200001-2 SCAN921023/SCAN921224 www.national.com 2

of three CMOS input gates (15 pF load) with a 66 MHz clock. outputs (including RCLK) will enter TRI-STATE. pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. data contained in the data stream can also affect lock time. Figure 1. Please note that RMT only applies to bits exit Powerdown, you must drive the PWRDN pin high. high until lock to the Bus LVDS clock occurs. static (SYNC1, SYNC2, PWRDN, TCLK_R/F). LOCK output remains active, reflecting the state of the PLL.

66 MHz Units

pattern with multiple parts. tions to test the LVDS interconnects. The first is EXTEST.

Ordering Information

SCAN921023SLC Serializer SLC49a SCAN921224SLC Deserializer SLC49a DS200001-24 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DS200001-25 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS200001-26 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) −0.3V to +4V LVCMOS/LVTTL Input Voltage −0.3V to (V CC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (V CC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.9V Bus LVDS Driver Output Voltage −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10mS Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) +260˚C Maximum Package Power Dissipation Capacity @ 25˚C Package: 49L BGA 1.47 W Package Derating: 49L BGA 11.8 mW/˚C above +25˚C θja 85˚C/W ESD Rating HBM >2kV MM 250V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC ) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Receiver Input Range 0 2.4 V Supply Noise Voltage (VCC ) 100 mV P-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA -0.86 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±1 +10 µA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins ROUT, RCLK, LOCK = outputs) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −0.62 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±1 +15 µA IILR Input Current, TMS, TDI, TRST inputs VIN = 0V or 3.6V -20 -10 µA VOH High Level Output Voltage IOH = −9 mA 2.2 3.0 V CC V VOL Low Level Output Voltage I OL = 9 mA GND 0.25 0.5 V IOS Output Short Circuit Current VOUT = 0V −15 −47 −85 mA IOS Output Short Circuit Current, TDO output -15 -70 -100 mA IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, V OUT =0 Vo rV C C −10 ±0.1 +10 µA SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−) V OD Output Differential Voltage (DO+)–(DO−) R L=2 7Ω ,Figure 18 200 290 mV ΔVOD Output Differential Voltage Unbalance 35 mV VOS Offset Voltage 1.05 1.1 1.3 V ΔVOS Offset Voltage Unbalance 4.8 35 mV IOS Output Short Circuit Current D0 = 0V, DIN = High,PWRDN and DEN = 2.4V −56 −90 mA IOZ TRI-STATE Output Current PWRDN or DEN = 0.8V, DO = 0V or VCC −10 ±1 +10 µA IOX Power-Off Output Current VCC = 0V, DO=0V or 3.6V −20 ±1 +25 µA SCAN921023/SCAN921224 www.national.com5

Serializer Switching Characteristics(Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tDJIT Deterministic Jitter R L = 27Ω , C L=10pF to GND, (Note 6)

20 MHz -300 -135 35 pS

66 MHz -245 -40 160 pS

t RJIT Random Jitter R L =2 7Ω , C L=10pF to GND 19 25 pS (RMS) Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 15.15 T 50 nS tRFDC REFCLK Duty Cycle 30 50 70 % tRFCP /tTCP Ratio of REFCLK to TCLK 95 1 105 tRFTT REFCLK Transition Time 3 6 nS Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver out Clock Period tRCP =tTCP Figure 11 RCLK 15.15 50 nS tCLH CMOS/TTL Low-to-High Transition Time C L=1 5p F Figure 5 Rout(0-9), LOCK, RCLK 1.2 4 nS tCHL CMOS/TTL High-to-Low Transition Time 1.1 4 nS tDD Deserializer Delay Figure 12 tROS ROUT Data Valid before Figure 13 RCLK 20MHz 0.4*tRCP 0.5*tRCP nSRCLK RCLK 66MHz 0.38*tRCP 0.5*tRCP nS tROH ROUT Data valid after Figure 13 20MHz −0.4*t RCP −0.5*tRCP nS RCLK 66MHz −0.38*t RCP −0.5*tRCP nS tRDC RCLK Duty Cycle 45 50 55 % tHZR HIGH to TRI-STATE DelayFigure 14 Rout(0-9) 2.8 10 nS tLZR LOW to TRI-STATE Delay 2.8 10 nS tZHR TRI-STATE to HIGH Delay 4.2 10 nS tZLR TRI-STATE to LOW Delay 4.2 10 nS tDSR1 Deserializer PLL Lock Time from PWRDWN (with SYNCPAT) Figure 15 Figure 16 (Note 7) 20MHz 2.6 4 µS 66MHz 0.84 3 µS tDSR2 Deserializer PLL Lock time from SYNCPAT 20MHz 1 2 µS 66MHz 0.29 0.8 µS tZHLK TRI-STATE to HIGH Delay (power-up) LOCK 3.7 12 nS SCAN921023/SCAN921224 www.national.com7

Over recommended operating supply and temperature ranges unless otherwise specified.

66 MHz 250 400 pS

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:Typical values are given for VCC = 3.3V and TA = +25˚C. VTH and VTL which are differential voltages. Note 4:tLLHT and tLHLT specifications are Guaranteed By Design (GBD) using statistical analysis. Note 5:Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer. Note 6:tDJIT specifications are Guaranteed By Design using statistical analysis. not receiving data to receiving synchronization patterns (SYNCPATs). Margin is Guaranteed By Design (GBD) using statistical analysis. FIGURE 2. “Worst Case” Serializer ICC Test Pattern

SCAN921023SLC - Serializer (Top View) DS200001-30 SCAN921224SLC - Deserializer (Top View) DS200001-31 SCAN921023/SCAN921224 www.national.com17

Serializer Pin Description Pin Name I/O Ball Id. Description DIN I A3, B1, C1, D1, D2, D3, E1, E2, F2, Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. TCLKR/F I G3 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge. Low selects falling edge. DO+ O D7 + Serial Data Output. Non-inverting Bus LVDS differential output. DO− O D5 − Serial Data Output. Inverting Bus LVDS differential output. DEN I D6 Serial Data Output Enable. LVTTL level input. A low puts the Bus LVDS outputs in TRI-STATE. PWRDN I C7 Powerdown. LVTTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs putting the device into a low power sleep mode. TCLK I E4 Transmit Clock. LVTTL level input. Input for 20 MHz–66 MHz system clock. SYNC I A4, B3 Assertion of SYNC (high) for at least 1024 synchronization symbols to be transmitted on the Bus LVDS serial output. Synchronization symbols continue to be sent if SYNC continues to be asserted. TTL level input. The two SYNC pins are ORed. DVCC I C3, C4, E5 Digital Circuit power supply. DGND I A1, C2, F5, E6, G4 Digital Circuit ground. AVCC I A5, A6, B4, B7, G5 Analog power supply (PLL and Analog Circuits). AGND I B5, B6, C6, E7, F7 Analog ground (PLL and Analog Circuits). TDI I F1 Test Data Input to support IEEE 1149.1 TDO O G1 Test Data Output to support IEEE 1149.1 TMS I E3 Test Mode Select Input to support IEEE 1149.1 TCK I F3 Test Clock Input to support IEEE 1149.1 TRST I G2 Test Reset Input to support IEEE 1149.1 N/C N/A A2, A7, B2, C5, D4, F6, G6, G7 Leave open circuit, do not connect Deserializer Pin Description Pin Name I/O Ball Id. Description ROUT O A5, B4, B6, C4, C7, D6, F5, F7, G4, Data Output.±9 mA CMOS level outputs. RCLKR/F I B3 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I D2 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I C1 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I D3 Powerdown. TTL level input. PWRDN driven low shuts down the PLL and TRI-STATEs outputs putting the device into a low power sleep mode. SCAN921023/SCAN921224 www.national.com 18

Deserializer Pin Description(Continued) Pin Name I/O Ball Id. Description LOCK O E1 LOCK goes low when the Deserializer PLL locks onto the embedded clock edge. CMOS level output. Totem pole output structure, does not directly support wired OR connections. RCLK O E2 Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT, CMOS level output. REN I D1 Output Enable. TTL level input. When driven low, TRI-STATEs ROUT0–ROUT9 and RCLK. DVCC I A7, B7, C5, C6, D5 Digital Circuit power supply. DGND I A1, A6, B5, D7, E4, E7, Digital Circuit ground. AVCC I B1, C2, F1, F2, G1 Analog power supply (PLL and Analog Circuits). AGND I A4, B2, F3, F4, G2 Analog ground (PLL and Analog Circuits). REFCLK I A3 Use this pin to supply a REFCLK signal for the internal PLL frequency. TDI I F6 Test Data Input to support IEEE 1149.1 TDO O G6 Test Data Output to support IEEE 1149.1 TMS I G7 Test Mode Select Input to support IEEE 1149.1 TCK I E5 Test Clock Input to support IEEE 1149.1 TRST I E6 Test Reset Input to support IEEE 1149.1 N/C N/A A2, C3, D4, Leave open circuit, do not connect Deserializer Truth Table INPUTS OUTPUTS PWRDN REN ROUT [0:9] LOCK RCLK H (4) H Z H Z H H Active L Active LX Z Z Z H L Z Active Z 1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream. 2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F. 3) ROUT and RCLK are TRI-STATED when LOCK is asserted High. 4) During Power-up. SCAN921023/SCAN921224 www.national.com19

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Order Number SCAN921023SLC or SCAN921224SLC SCAN921023/SCAN921224 20-66 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.