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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 SCAN921025andSCAN92122630-80MHz10BitBusLVDSSerializerandDeserializer withIEEE1149.1(JTAG)andat-speedBIST Check forSamples: SCAN921025 ,SCAN921226 1FEATURES DESCRIPTION The SCAN921025 transformsa 10-bitwide parallel 2• IEEE 1149.1(JTAG) Compliant and At-Speed LVCMOS/LVTTL data bus intoa singlehigh speedBIST TestMode. Bus LVDS serialdata stream withembedded clock.• Clock Recovery From PLL Lock toRandom The SCAN921226 receivestheBus LVDS serialdata Data Patterns. stream and transformsitback intoa 10-bitwide paralleldatabus and recoversparallelclock.• SpecifiedTransitionEvery Data TransferCycle
- Chipset(Tx+ Rx) Power Consumption < 600 Both devices are compliant with IEEE 1149.1 mW (typ)@ 80 MHz Standard for Boundary Scan Test. IEEE 1149.1 featuresprovidethe designor testengineeraccess• SingleDifferentialPairEliminatesMulti- via a standard Test Access Port (TAP) to theChannel Skew backplaneor cable interconnectsand the abilityto• 800 Mbps SerialBus LVDS Data Rate (At80 verifydifferentialsignalintegrity.The pairof devicesMHz Clock) alsofeaturesan at-speedBIST mode which allows the interconnectsbetween the Serializerand• 10-BitParallelInterfacefor1 Byte Data Plus 2 Deserializertobe verifiedat-speed.ControlBits
- SynchronizationMode and LOCK Indicator The SCAN921025 transmitsdataoverbackplanesor cable.The singledifferentialpairdata path makes• Programmable Edge Triggeron Clock PCB design easier.In addition,the reduced cable,• High Impedance on ReceiverInputsWhen PCB tracecount,and connectorsizetremendouslyPower isOff reduce cost.Since one outputtransmitsclockand
- Bus LVDS SerialOutput Rated for27Ω Load databitsserially,iteliminatesclock-to-dataand data- to-dataskew. The powerdown pin saves power by• Small 49-Lead NFBGA Package reducingsupplycurrentwhen notusingeitherdevice. Upon power up of the Serializer,you can choose to activate synchronizationmode or allow the Deserializerto use the synchronization-to-random- datafeature.By usingthesynchronizationmode, the Deserializerwillestablishlock to a signalwithin specifiedlocktimes.Inaddition,theembedded clock ensures a transitionon the bus every 12-bitcycle. This eliminatestransmissionerrorsdue to charged cable conditions.Furthermore,you may put the SCAN921025 outputpinsintoTri-stateto achievea high impedance state.The PLL can lock to frequenciesbetween 30 MHz and 80 MHz. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2001–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Block Diagrams Application
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The SCAN921025 and SCAN921226 are a 10-bitSerializerand Deserializerchipsetdesignedtotransmitdata overdifferentialbackplanesatclockspeeds from30 to80 MHz. The chipsetisalsocapableofdrivingdataover UnshieldedTwistedPair(UTP) cable. The chipsethas threeactivestatesof operation:Initialization, Data Transfer, and Resynchronization; and two passivestates:Powerdown and TRI-STATE . In additionto the activeand passivestates,thereare alsotest modes forJTAG accessand at-speedBIST. The followingsectionsdescribeeach operationand passivestateand thetestmodes. Initialization Initializationofbothdevicesmust occurbeforedatatransmissionbegins.Initializationreferstosynchronizationof the Serializerand DeserializerPLL's to localclocks,which may be the same or separate.Afterwards, synchronizationoftheDeserializertoSerializeroccurs. Step 1:When you applyVCC tobothSerializerand/orDeserializer,therespectiveoutputsenterTRI-STATE, and on-chippower-oncircuitrydisablesinternalcircuitry.When VCC reachesVCC OK (2.5V)thePLL ineach device beginslockingtoa localclock.For theSerializer,thelocalclockisthetransmitclock(TCLK) providedby the sourceASIC orotherdevice.FortheDeserializer,you must applya localclocktotheREFCLK pin. The Serializeroutputsremain in TRI-STATE whilethe PLL locksto the TCLK. Afterlockingto TCLK, the Serializerisnow readytosend dataorSYNC patterns,dependingon thelevelsoftheSYNC1 and SYNC2 inputs or a datastream.The SYNC patternsentby theSerializerconsistsofsixones and sixzerosswitchingatthe inputclockrate. Note thatthe DeserializerLOCK outputwillremain highwhileitsPLL locksto the incomingdata or to SYNC patternson theinput. Step 2:The DeserializerPLL must synchronizetotheSerializertocompleteinitialization.The Deserializerwill locktonon-repetitivedatapatterns.However,thetransmissionofSYNC patternsenablestheDeserializertolock totheSerializersignalwithina specifiedtime.See Figure11. The user'sapplicationdeterminescontrolof the SYNC1 and SYNC 2 pins.One recommendationisa direct feedbackloopfrom the LOCK pin.Under allcircumstances,the SerializerstopssendingSYNC patternsafter bothSYNC inputsreturnlow. When theDeserializerdetectsedge transitionsattheBus LVDS input,itwillattempttolocktotheembedded clockinformation.When theDeserializerlockstotheBus LVDS clock,theLOCK outputwillgo low.When LOCK islow,theDeserializeroutputsrepresentincomingBus LVDS data. Data Transfer Afterinitialization,theSerializerwillacceptdatafrom inputsDIN0–DIN9. The Serializeruses theTCLK inputto latchincomingData. The TCLK_R/ F pin selectswhich edge the Serializeruses to strobeincomingdata. TCLK_R/ F highselectstherisingedge forclockingdataand low selectsthefallingedge.IfeitheroftheSYNC inputsishighfor5*TCLK cycles,thedataatDIN0-DIN9 isignoredregardlessofclockedge. Afterdeterminingwhich clockedge touse,a startand stopbit,appended internally,frame thedatabitsinthe register.The startbitisalways high and the stop bitisalways low.The startand stop bitsfunctionas the embedded clockbitsintheserialstream. The Serializertransmitsserializeddataand clockbits(10+2 bits)from theserialdataoutput(DO ±) at12 times theTCLK frequency.For example,ifTCLK is80 MHz, theserialrateis80 × 12 = 960 Mega-bits-per-second. Sinceonly10 bitsarefrominputdata,theserial“payload”rateis10 timestheTCLK frequency.For instance,if TCLK = 80 MHz, thepayloaddatarateis80 × 10 = 800 Mbps. The datasourceprovidesTCLK and must be in therangeof30 MHz to80 MHz nominal. The Serializeroutputs(DO ±) can drivea point-to-pointconnectionor in limitedmulti-pointor multi-drop backplanes.The outputstransmitdata when the enablepin(DEN) ishigh,PWRDN = high,and SYNC1 and SYNC2 arelow.When DEN isdrivenlow,theSerializeroutputpinswillenterTRI-STATE. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com When the Deserializersynchronizesto the Serializer,the LOCK pin is low.The Deserializerlocksto the embedded clockand uses ittorecovertheserializeddata.ROUT dataisvalidwhen LOCK islow.Otherwise ROUT0 –ROUT9 isinvalid. The ROUT0-ROUT9 pinsuse theRCLK pinas thereferencetodata.The polarityoftheRCLK edge iscontrolled by theRCLK_R/ F input.See Figure15. ROUT(0-9),LOCK and RCLK outputswilldrivea maximum ofthreeCMOS inputgates(15 pF load)witha 80 MHz clock. Resynchronization When theDeserializerPLL lockstotheembedded clockedge,theDeserializerLOCK pinassertsa low.Ifthe Deserializerloseslock,theLOCK pinoutputwillgo highand theoutputs(includingRCLK) willenterTRI-STATE. The user'ssystem monitorstheLOCK pintodetecta lossofsynchronization.Upon detection,thesystem can arrangetopulsetheSerializerSYNC1 or SYNC2 pintoresynchronize.Multipleresynchronizationapproaches are possible.One recommendationistoprovidea feedbackloopusingtheLOCK pinitselftocontrolthesync requestoftheSerializer(SYNC1 or SYNC2). Dual SYNC pinsare providedformultiplecontrolina multi-drop application.Sending sync patternsforresynchronizationisdesirablewhen locktimeswithina specifictimeare critical.However,theDeserializercan locktorandom data,whichisdiscussedinthenextsection. Random Lock Initializationand Resynchronization The initializationand resynchronizationmethods describedintheirrespectivesectionsare the fastestways to establishthelinkbetween theSerializerand Deserializer.However, theSCAN921226 can attainlocktoa data streamwithoutrequiringtheSerializertosend specialSYNC patterns.ThisallowstheSCAN921226 tooperate in“open-loop” applications.EquallyimportantistheDeserializer'sabilitytosupporthotinsertionintoa running backplane.Intheopen looporhotinsertioncase,we assume thedatastreamisessentiallyrandom.Therefore, because lock time variesdue to data stream characteristics,we cannot possiblypredictexact lock time. However, please see Table 1 forsome generalrandom locktimes under specificconditions.The primary constrainton the “random” locktimeisthe initialphase relationbetween the incomingdata and the REFCLK when theDeserializerpowers up.As describedinthenextparagraph,thedatacontainedinthedatastreamcan alsoaffectlocktime. Ifa specificpatternisrepetitive,theDeserializercouldenter“falselock”-falselyrecognizingthedatapatternas theclockingbits.We refertosuch a patternas a repetitivemulti-transition,RMT. Thisoccurswhen more than one Low-Hightransitiontakesplaceina clockcycleovermultiplecycles.Thisoccurswhen any bit,exceptDIN 9, isheld at a low stateand the adjacentbitisheld high,creatinga 0-1 transition.In the worstcase,the Deserializercouldbecome lockedtothedatapatternratherthantheclock.CircuitrywithintheSCAN921226 can detectthatthe possibilityof “falselock” exists.The circuitryaccomplishesthisby detectingmore than one potentialpositionforclockingbits.Upon detection,the circuitrywillpreventthe LOCK outputfrom becoming activeuntilthe potential“falselock” patternchanges. The falselockdetectcircuitryexpectsthe data will eventuallychange,causingtheDeserializertoloselocktothedatapatternand thencontinuesearchingforclock bitsintheserialdatastream.GraphicalrepresentationsofRMT are shown inFigure3.PleasenotethatRMT onlyappliestobitsDIN0-DIN8. Powerdown When no data transferoccurs,you can use the Powerdown state.The Serializerand Deserializeruse the Powerdown state,a low power sleepmode, toreducepower consumption.The DeserializerentersPowerdown when you drivePWRDN and REN low.The SerializerentersPowerdown when you drivePWRDN low.In Powerdown, thePLL stopsand theoutputsenterTRI-STATE, which disablesloadcurrentand reducessupply currenttothemilliampererange.To exitPowerdown, you must drivethePWRDN pinhigh. Beforevaliddataexchanges between theSerializerand Deserializer,you must reinitializeand resynchronizethe devicestoeach other.InitializationoftheSerializertakes510 TCLK cycles.The Deserializerwillinitializeand assertLOCK highuntillocktotheBus LVDS clockoccurs.
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 TRI-STATE The SerializerentersTRI-STATE when theDEN pinisdrivenlow.Thisputsbothdriveroutputpins(DO+ and DO −)intoTRI-STATE. When you driveDEN high,theSerializerreturnstothepreviousstate,as longas allother controlpinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). When you drivethe REN pinlow,the DeserializerentersTRI-STATE. Consequently,the receiveroutputpins (ROUT0 –ROUT9) and RCLK willenterTRI-STATE. The LOCK outputremainsactive,reflectingthestateofthe PLL. Table1.Random Lock Times fortheSCAN921226 (1)
80 MHz Units
Maximum 18 μs Mean 3.0 μs Minimum 0.43 μs Conditions: PRBS 215,VCC = 3.3V (1) Differenceinlocktimesaredue todifferentstartingpointsinthedata patternwithmultipleparts. TestModes InadditiontotheIEEE 1149.1testaccesstothedigitalTTL pins,theSCAN921025 and SCAN921226 have two instructionstotesttheLVDS interconnects.The firstisEXTEST. ThisisimplementedatLVDS levelsand isonly intendedas a go no-go test(e.g.missingcables).The second method istheRUNBIST instruction.Itisan "at- system-speed"interconnecttest.Itisexecutedinapproximately33mS witha system clockspeed of 66MHz. There are two bitsinthe RX BIST data registerfornotificationof PASS/FAIL and TEST_COMPLETE. Pass indicatesthattheBER (Bit-Error-Rate)isbetterthan10-7. An importantdetailis thatonce both deviceshave the RUNBIST instructionloaded intotheirrespective instructionregisters,bothdevicesmust move intotheRTI statewithin4K system clocks(Ata SCLK of66Mhz and TCK of1MHz thisallowsfor66 TCK cycles).Thisisnota concernwhen bothdevicesareon thesame scan chainor LSP, however,itcan be a problemwithsome multi-dropdevices.Thistestmode has been simulated and verifiedusingTI'sSCANSTA111. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com RMT PatternsSeen on theBus LVDS SerialOutput Figure1.DIN0 Held Low-DIN1 Held High Creates Figure2.DIN8 Held Low-DIN9 Held High Creates an RMT Pattern an RMT Pattern Figure3.DIN4 Held Low-DIN5 Held High Createsan RMT Pattern These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VCC +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VCC +0.3V) Bus LVDS ReceiverInputVoltage −0.3Vto+3.9V Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuitDuration 10mS JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +220°C Maximum Package Power DissipationCapacity @ 25°C Package: 49L NFBGA 1.47W Package Derating: 49L NFBGA 11.8mW/ °C above +25°C θja 85°C/W ESD Rating HBM >2kV MM > 250V (1) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation.
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 RECOMMENDED OPERATING CONDITIONS Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +85 °C ReceiverInputRange 0 2.4 V SupplyNoiseVoltage(VCC ) 100 mV P-P
ELECTRICAL CHARACTERISTICS
Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytoDIN0-9,TCLK, PWRDN, TCLK_R/ F,SYNC1, SYNC2, DEN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA -0.86 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +10 μA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytopinsPWRDN, RCLK_R/ F,REN, REFCLK = inputs;applytopins ROUT, RCLK, LOCK = outputs) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −0.62 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +15 μA VOH HighLevelOutputVoltage IOH = −9 mA 2.2 3.0 VCC V VOL Low LevelOutputVoltage IOL = 9 mA GND 0.25 0.5 V IOS OutputShortCircuitCurrent VOUT = 0V −15 −47 −85 mA IOS OutputShortCircuitCurrent,TDO -15 -70 -100 mA output IOZ TRI-STATE OutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 ±0.1 +10 μA SERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsDO+ and DO −) VOD OutputDifferentialVoltage RL = 27Ω,see Figure19 200 290 mV(DO+)–(DO −) ΔVOD OutputDifferentialVoltageUnbalance 35 mV VOS OffsetVoltage 1.05 1.1 1.3 V ΔVOS OffsetVoltageUnbalance 4.8 35 mV IOS OutputShortCircuitCurrent D0 = 0V,DIN = High,PWRDN and DEN = −56 −90 mA2.4V IOZ TRI-STATE OutputCurrent PWRDN orDEN = 0.8V,DO = 0V orVCC −10 ±1 +10 μA IOX Power-OffOutputCurrent VCC = 0V,DO=0V or3.6V −20 ±1 +25 μA DESERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsRI+ and RI−) VTH DifferentialThresholdHighVoltage VCM = +1.1V +6 +50 mV VTL DifferentialThresholdLow Voltage −50 −12 mV IIN InputCurrent VIN = +2.4V,VCC = 3.6Vor0V −10 ±1 +10 μA VIN = 0V,VCC = 3.6Vor0V −10 ±0.05 +10 μA SERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCD SerializerSupplyCurrent RL = 27Ω f= 30 MHz 45 60 mA WorstCase See Figure4 f= 80 MHz 90 105 mA ICCXD SerializerSupplyCurrentPowerdown PWRDN = 0.8V,f= 80 MHz 0.2 1.0 mA DESERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCR DeserializerSupplyCurrent C L = 15 pF f= 30 MHz 50 75 mA WorstCase See Figure5 f= 80 MHz 100 120 mA ICCXR DeserializerSupplyCurrent PWRDN = 0.8V,REN = 0.8V 0.36 1.0 mAPowerdown Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units SCAN CIRCUITRY DC SPECIFICATIONS, SERIALIZER AND DESERIALIZER (appliestoSCAN pinsas noted) VIH HighLevelInputVoltage VCC = 3.0to3.6V,pinsTCK, TMS, TDI,and 2.0 VCC VTRST VIL Low LevelInputVoltage VCC = 3.0to3.6V,pinsTCK, TMS, TDI,and GND 0.8 VTRST VCL InputClamp Voltage VCC = 3.0V,ICL = −18 mA, pinsTCK, TMS, −0.85 −1.5 VTDI,and TRST IIH InputCurrent VCC = 3.6V,VIN = 3.6V,pinsTCK, TMS, TDI, 1 +10 μAand TRST IIL InputCurrent VCC = 3.6V,VIN = 0.0V,TCK Input -10 -1 μA IILR InputCurrent VCC = 3.6V,VIN = 0V,pinsTMS, TDI,and -20 -10 μA TRST VOH HighLevelOutputVoltage VCC = 3.0V,IOH = −12 mA, TDO output 2.2 2.6 V VOL Low LevelOutputVoltage VCC = 3.0V,IOL = 12 mA, TDO output 0.3 0.5 V IOS OutputShortCircuitCurrent VCC = 3.6V,VOUT = 0.0V,TDO output -15 -90 -120 mA IOZ TRI-STATE OutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 0 +10 μA SERIALIZER TIMING REQUIREMENTS FOR TCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tTCP TransmitClockPeriod 12.5 T 33.3 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime 3 6 ns tJIT TCLK InputJitter 150 ps (RMS) SERIALIZER SWITCHING CHARACTERISTICS Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tLLHT Bus LVDS Low-to-High R L = 27Ω 0.2 0.4 nsTransitionTime C L=10pF toGND (1) See Figure6tLHLT Bus LVDS High-to-Low 0.25 0.4 nsTransitionTime tDIS DIN (0-9)SetuptoTCLK R L = 27Ω, 0 ns C L=10pF toGNDtDIH DIN (0-9)Holdfrom 4.0 nsSee Figure9TCLK tHZD DO ± HIGH to R L = 27Ω, 3 10 nsTRI-STATE Delay C L=10pF toGND (2) See Figure10tLZD DO ± LOW toTRI- 3 10 nsSTATE Delay tZHD DO ± TRI-STATE to 5 10 nsHIGH Delay tZLD DO ± TRI-STATE to 6.5 10 nsLOW Delay tSPW SYNC PulseWidth R L = 27Ω 5*tTCP ns See Figure12tPLD SerializerPLL Lock Time 510*tTCP 513*tTCP ns tSD SerializerDelay R LLLHT = 27Ω,see Figure13 tTCP + 1.0 tTCP + 2.5 tTCP + 3.5 ns (1) tLLHT and tLHLT specificationsarespecifiedby designusingstatisticalanalysis. (2) Because theSerializerisinTRI-STATE mode, theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer.
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 SERIALIZER SWITCHING CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tDJIT DeterministicJitter -130 -40 +60 psR L = 27Ω, 80 MHzC L=10pF toGND (3) tRJIT Random Jitter 6 10 ps (RMS) (3) tDJIT specificationsarespecifiedby designusingstatisticalanalysis. DESERIALIZER TIMING REQUIREMENTS FOR REFCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 12.5 T 33.3 ns tRFDC REFCLK DutyCycle 30 50 70 % tRFCP / RatioofREFCLK toTCLK 95 1 105tTCP tRFTT REFCLK TransitionTime 3 6 ns DESERIALIZER SWITCHING CHARACTERISTICS Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP ReceiveroutClock tRCP = tTCP RCLK 12.5 33.3 nsPeriod See Figure13 tCLH CMOS/TTL Low- CL = 15 pF to-HighTransition See Figure7 1.2 4 ns Rout(0-9),Time LOCK tCHL CMOS/TTL High- RCLK to-LowTransition 1.1 4 ns Time tROS ROUT Data Valid See Figure15 RCLK 0.4*tRCP 0.5*tRCP nsbeforeRCLK 30 MHz RCLK 0.35*tRCP 0.5*tRCP ns80 MHz tROH ROUT Data valid See Figure15 30 MHz −0.4*tRCP −0.5*tRCP nsafterRCLK 80 MHz −0.35*tRCP −0.5*tRCP ns tRDC RCLK DutyCycle 45 50 55 % tHZR HIGH toTRI- See Figure16 2.8 10 nsSTATE Delay tLZR LOW toTRI- 2.8 10 nsSTATE Delay Rout(0-9) tZHR TRI-STATE to 4.2 10 nsHIGH Delay tZLR TRI-STATE to 4.2 10 nsLOW Delay Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com DESERIALIZER SWITCHING CHARACTERISTICS (continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tDSR1 DeserializerPLL See Figure17 and 30 MHz 1.7 3.5 μs Lock Time from Figure18(1) PWRDWN (with 80 MHz 1.0 2.5 μs SYNCPAT) tDSR2 DeserializerPLL 30 MHz 0.65 1.5 μs Lock timefrom 80 MHz 0.29 0.8 μsSYNCPAT tZHLK TRI-STATE to HIGH Delay LOCK 3.7 12 ns (power-up) tRNMI-R IdealNoiseMargin See Figure22 80 MHz +350 psRight(2) tRNMI-L IdealNoiseMargin See Figure22 80 MHz -385 psLeft(2) (1) ForthepurposeofspecifyingdeserializerPLL performance,tDSR1 and tDSR2 arespecifiedwiththeREFCLK runningand stable,and withspecificconditionsfortheincomingdatastream(SYNCPATs). Itisrecommended thatthedeserializerbe initializedusingeither tDSR1 timingortDSR2 timing.tDSR1 isthetimerequiredforthedeserializertoindicatelockupon power-uporwhen leavingthepower- down mode. Synchronizationpatternsshouldbe senttothedevicebeforeinitiatingeithercondition.tDSR2 isthetimerequiredtoindicate lockforthepowered-upand enableddeserializerwhen theinput(RI+and RI-)conditionschange fromnotreceivingdatatoreceiving synchronizationpatterns(SYNCPATs). (2) tRNM isa measure ofhow much phase noise(jitter)thedeserializercan tolerateintheincomingdatastreambeforebiterrorsoccur.The DeserializerNoiseMarginisspecifiedby designusingstatisticalanalysis. Table2. SCAN CIRCUITRY TIMING REQUIREMENTS Symbol Parameter Conditions Min Typ Max Units fMAX Maximum TCK Clock 25.0 50.0 MHz Frequency tS TDI toTCK, H orL 1.0 ns tH TDI toTCK, H orL 2.0 ns tS TMS toTCK, H orL 2.5 ns R L = 500Ω,C L = 35 pF tH TMS toTCK, H orL 1.5 ns tW TCK PulseWidth,H orL 10.0 ns tW TRST PulseWidth,L 2.5 ns tREC RecoveryTime,TRST to 2.0 ns TCK
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 AC TIMING DIAGRAMS AND TEST CIRCUITS Figure4. “Worst Case ” SerializerICC TestPattern Figure5. “Worst Case ” DeserializerICC TestPattern Figure6. SerializerBus LVDS Output Load and TransitionTimes Figure7. DeserializerCMOS/TTL Output Load and TransitionTimes Figure8. SerializerInputClock TransitionTime Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Timingshown forTCLK_R/ F = LOW Figure9. SerializerSetup/HoldTimes Figure10. SerializerTRI-STATE TestCircuitand Timing Figure11. SerializerPLL Lock Time,and PWRDN TRI-STATE Delays
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 Figure12. SYNC Timing Delays Figure13. SerializerDelay Figure14. DeserializerDelay Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Timingshown forRCLK_R/ F = LOW DutyCycle(tRDC )= Figure15. DeserializerData ValidOut Times Figure16. DeserializerTRI-STATE TestCircuitand Timing
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 Figure17. DeserializerPLL Lock Times and PWRDN TRI-STATE Delays Figure18. DeserializerPLL Lock Time from SyncPAT Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com VOD = (DO +)–(DO −). Differentialoutputsignalisshown as (DO+)–(DO −),deviceinData Transfermode. Figure19. VOD Diagram
APPLICATION INFORMATION
USING THE SCAN921025 AND SCAN921226 The Serializerand Deserializerchipsetisan easy to use transmitterand receiverpairthatsends 10 bitsof parallelLVTTL dataovera serialBus LVDS linkup to800 Mbps. An on-boardPLL serializestheinputdataand embeds two clockbitswithinthedatastream.The Deserializeruses a separatereferenceclock(REFCLK) and an onboard PLL toextracttheclockinformationfrom theincomingdatastreamand thendeserializethedata. The Deserializermonitorstheincomingclockinformation,determineslockstatus,and assertstheLOCK output highwhen lossoflockoccurs. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Inaddition,the constantcurrentsource natureof the Bus LVDS outputsminimizesthe slopeof the speed vs.ICC curve of conventionalCMOS designs. POWERING UP THE DESERIALIZER The SCAN921226 can be powered up atany timeby followingthepropersequence.The REFCLK inputcan be runningbeforetheDeserializerpowers up,and itmust be runninginorderfortheDeserializertolocktoincoming data.The Deserializeroutputswillremain inTRI-STATE untilthe Deserializerdetectsdata transmissionat its inputsand lockstotheincomingdatastream. TRANSMITTING DATA Once you power up theSerializerand Deserializer,theymust be phase lockedtoeach othertotransmitdata. Phase lockingoccurswhen theDeserializerlockstoincomingdataor when theSerializersends patterns.The Serializersends SYNC patternswhenever the SYNC1 or SYNC2 inputsare high.The LOCK outputof the Deserializerremainshighuntilithas lockedto the incomingdata stream.ConnectingtheLOCK outputof the Deserializerto one of the SYNC inputsof the Serializerwillensure thatenough SYNC patternsare sentto achieveDeserializerlock. The Deserializercan alsolocktoincomingdataby simplypoweringup thedeviceand allowingthe“random lock” circuitrytofindand locktothedatastream. WhiletheDeserializerLOCK outputislow,dataattheDeserializeroutputs(ROUT0-9) isvalid,exceptforthe specificcase of lossof lockduringtransmissionwhich isfurtherdiscussedin RECOVERING FROM LOCK LOSS .
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyreceivedata.Variousenvironmentaland systematicfactorsinclude:
- Serializer:TCLK jitter,VCC noise(noisebandwidthand out-of-bandnoise)
- Media:ISI,LargeVCM shifts
- Deserializer:VCC noise RECOVERING FROM LOCK LOSS In the case where the Deserializerloseslockduringdata transmission,up to 3 cyclesof data thatwere previouslyreceivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuit requiresthatinvalidclockinformationbe received4 times in a row to indicatelossof lock.Since clock informationhas been lost,itis possiblethatdata was also lostduringthese cycles.Therefore,afterthe Deserializerrelockstotheincomingdatastreamand theDeserializerLOCK pingoes low,atleastthreeprevious datacyclesshouldbe suspectforbiterrors. The Deserializercan relockto the incomingdata stream by making the Serializerresend SYNC patterns,as describedabove, or by random locking,which can take more time,depending on the data patternsbeing received. HOT INSERTION Allthe BLVDS devicesare hot pluggableifyou followa few rules.When inserting,ensure the Ground pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround.Random lockhotinsertionisillustratedinFigure23. PCB CONSIDERATIONS The Bus LVDS Serializerand Deserializershouldbe placedas closeto the edge connectoras possible.In multipleDeserializerapplications,thedistancefrom theDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longer stubslowertheimpedance ofthebus,increasetheloadon theSerializer,and lowerthethresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedmuch lessthan one inchfrom slotconnectors.Because transitiontimesare very faston the SerializerBus LVDS outputs,reducingstublengthsas much as possibleisthebestmethod toensuresignalintegrity. TRANSMISSION MEDIA The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationofa backplane,througha PCB trace,or throughtwistedpaircable.In point-to-pointconfiguration,the transmissionmedia need only be terminatedat the receiverend. Please note thatin point-to-pointconfiguration,the potentialof offsettingthe ground levelsof the Serializervs.the Deserializermust be considered.Also,Bus LVDS providesa +/− 1.2V common mode rangeatthereceiverinputs. FAILSAFE BIASING FOR THE SCAN921226 The SCAN921226 has an improved inputthresholdsensitivityof +/− 50mV versus +/− 100mV for the DS92LV1210 orDS92LV1212. ThisallowsforgreaterdifferentialnoisemarginintheSCAN921226. However,in cases where the receiverinputisnot beingactivelydriven,the increasedsensitivityof the SCAN921226 can pickupnoiseas a signaland cause unintentionallocking.For example,thiscan occurwhen theinputcableis disconnected. Externalresistorscan be added tothereceivercircuitboardtopreventnoisepick-up.Typically,thenon-inverting receiverinputispulledup and theinvertingreceiverinputispulleddown by highvalueresistors.thepull-upand pull-downresistors(R1 and R 2) providea currentpath throughthe terminationresistor(RL) which biasesthe receiverinputswhen theyarenotconnectedtoan activedriver.The valueofthepull-upand pull-downresistors shouldbe chosen so thatenough currentisdrawn to providea +15mV drop acrossthe terminationresistor. Pleasesee Figure20 fortheFailsafeBiasingSetup. Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY The parametertRNM iscalculatedby firstmeasuringhow much of the idealbitthe receiverneeds to ensure correctsampling.Afterdeterminingthisamount, what remains of the idealbitthatisavailableforexternal sourcesofnoiseiscalledtRNM .tRNM includestransmitterjitter. PleaserefertoFigure21 and Figure22 fora graphicrepresentationoftDJIT and tRNM .Also,fora more detailed explanationof tRNM , pleasesee the ApplicationNote titled'How to ValidateBLVDS SER/DES SignalIntegrity Usingan Eye Mask'(SNLA053 ). The verticallimitsofthemask aredeterminedby theSCAN921226 receiverinputthresholdof+/− 50mV. Figure20. FailsafeBiasingSetup Figure21. DeterministicJitterand IdealBitPosition tRNMI-L istheidealnoisemarginon theleftofthefigure,itisa negativevaluetoindicateearlywithrespecttoideal. tRNMI-R istheidealnoisemarginon therightoftheabove figure,itisa positivevaluetoindicatelatewithrespectto ideal. Figure22. IdealDeserializerNoise Margin (tRNMI )and Sampling Window
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 Figure23. Random Lock Hot Insertion PIN DIAGRAMS Figure24. SCAN921025SLC -Serializer(Top View) Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com Figure25. SCAN921226SLC -Deserializer(Top View) SERIALIZER PIN DESCRIPTIONS Pin Name I/O BallId. Description DIN I A3,B1,C1, D1, Data Input.LVTTL levelsinputs.Data on thesepinsareloadedintoa 10-bit D2, D3, E1,E2, inputregister. F2,F4 TCLKR/ F I G3 TransmitClockRising/Fallingstrobeselect.LVTTL levelinput.Selects TCLK activeedge forstrobingofDIN data.Highselectsrisingedge.Low selectsfallingedge. DO+ O D7 + SerialData Output.Non-invertingBus LVDS differentialoutput. DO − O D5 − SerialData Output.InvertingBus LVDS differentialoutput. DEN I D6 SerialData OutputEnable.LVTTL levelinput.A lowputstheBus LVDS outputsinTRI-STATE. PWRDN I C7 Powerdown. LVTTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATE outputsputtingthedeviceintoa lowpower sleepmode. TCLK I E4 TransmitClock.LVTTL levelinput.Inputfor30MHz – 80MHz systemclock. SYNC I A4,B3 AssertionofSYNC (high)foratleast1024 synchronizationsymbolstobe transmittedon theBus LVDS serialoutput.Synchronizationsymbols continuetobe sentifSYNC continuestobe asserted.TTL levelinput.The two SYNC pinsareORed. DVCC I C3, C4, E5 DigitalCircuitpower supply. DGND I A1,C2, F5,E6, DigitalCircuitground. AVCC I A5,A6,B4,B7, Analogpower supply(PLL and AnalogCircuits). AGND I B5,B6,C6, E7, Analogground(PLL and AnalogCircuits). TDI I F1 TestData InputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. TDO O G1 TestData OutputtosupportIEEE 1149.1
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013 SERIALIZER PIN DESCRIPTIONS (continued) Pin Name I/O BallId. Description TMS I E3 TestMode SelectInputtosupportIEEE 1149.1.Thereisan internalpullup resistorthatdefaultsthisinputtohighperIEEE 1149.1. TCK I F3 TestClockInputtosupportIEEE 1149.1 TRST I G2 TestResetInputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. N/C N/A A2,A7,B2,C5, Leave open circuit,do notconnect D4, F6,G6, G7 DESERIALIZER PIN DESCRIPTIONS Pin Name I/O BallId. Description ROUT O A5,B4,B6,C4, Data Output.±9 mA CMOS leveloutputs. C7, D6, F5,F7, G4, G5 RCLKR/ F I B3 RecoveredClockRising/Fallingstrobeselect.TTL levelinput.Selects RCLK activeedge forstrobingofROUT data.Highselectsrisingedge.Low selectsfallingedge. RI+ I D2 + SerialData Input.Non-invertingBus LVDS differentialinput. RI− I C1 − SerialData Input.InvertingBus LVDS differentialinput. PWRDN I D3 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATEs outputsputtingthedeviceintoa lowpower sleepmode. LOCK O E1 LOCK goes lowwhen theDeserializerPLL locksontotheembedded clock edge.CMOS leveloutput.Totem poleoutputstructure,does notdirectly supportwiredOR connections. RCLK O E2 RecoveredClock.Paralleldatarateclockrecoveredfromembedded clock. Used tostrobeROUT, CMOS leveloutput. REN I D1 OutputEnable.TTL levelinput.When drivenlow,TRI-STATES ROUT0 –ROUT9 and RCLK. DVCC I A7,B7,C5, C6, DigitalCircuitpower supply. DGND I A1,A6,B5,D7, DigitalCircuitground. E4,E7,G3 AVCC I B1,C2, F1,F2, Analogpower supply(PLL and AnalogCircuits). AGND I A4,B2,F3,F4, Analogground(PLL and AnalogCircuits). REFCLK I A3 Use thispintosupplya REFCLK signalfortheinternalPLL frequency. TDI I F6 TestData InputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. TDO O G6 TestData OutputtosupportIEEE 1149.1 TMS I G7 TestMode SelectInputtosupportIEEE 1149.1.Thereisan internalpullup resistorthatdefaultsthisinputtohighperIEEE 1149.1. TCK I E5 TestClockInputtosupportIEEE 1149.1 TRST I E6 TestResetInputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. N/C N/A A2,C3, D4, E3 Leave open circuit,do notconnect Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SCAN921025 SCAN921226
SCAN921025,SCAN921226 SNLS148C –DECEMBER 2001–REVISED APRIL 2013 www.ti.com DESERIALIZER TRUTH TABLE INPUTS OUTPUTS PWRDN REN ROUT 0:9 LOCK (2) RCLK (3) H (4) H Z H Z H H Active L Active L X Z Z Z H L Z Active Z (1) ROUT and RCLK areTRI-STATEd when LOCK isassertedHigh. (2) LOCK ActiveindicatestheLOCK outputwillreflectthestateoftheDeserializerwithregardtotheselecteddatastream. (3) RCLK ActiveindicatestheRCLK willbe runningiftheDeserializerislocked.The TimingofRCLK withrespecttoROUT isdetermined by RCLK_R/ F. (4) DuringPower-up.
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SCAN921025,SCAN921226 www.ti.com SNLS148C –DECEMBER 2001–REVISED APRIL 2013
REVISION HISTORY
Changes from RevisionB (April2013)toRevisionC Page Copyright© 2001–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SCAN921025 SCAN921226
www.ti.com 26-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SCAN921025SLC/NOPB NRND NFBGA NZA 49 416 Green (RoHS & no Sb/Br) SNAGCU Level-4-260C-72 HR SCAN921025 SLC SCAN921226SLC/NOPB NRND NFBGA NZA 49 416 Green (RoHS & no Sb/Br) SNAGCU Level-4-260C-72 HR SCAN921226 SLC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 26-Nov-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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