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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 SCAN921025HandSCAN921226HHighTemperature20-80MHz10BitBusLVDSSerDes withIEEE1149.1(JTAG)andat-speedBIST Check forSamples: SCAN921025H ,SCAN921226H 1FEATURES DESCRIPTION The SCAN921025H transformsa 10-bitwide parallel 2• High Temperature Operationto125°C LVCMOS/LVTTL data bus intoa singlehigh speed• IEEE 1149.1(JTAG) Compliant and At-Speed Bus LVDS serialdata stream withembedded clock.BIST TestMode The SCAN921226H receivesthe Bus LVDS serial
- Clock Recovery from PLL Lock toRandom datastreamand transformsitback intoa 10-bitwide paralleldatabus and recoversparallelclock.Data Patterns
- Ensured TransitionEvery Data TransferCycle Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1• Chipset(Tx+ Rx) Power Consumption < 600 featuresprovidethe designor testengineeraccessmW (Typ)@ 80 MHz via a standard Test Access Port (TAP) to the• SingleDifferentialPairEliminatesMulti- backplaneor cable interconnectsand the abilitytoChannel Skew verifydifferentialsignalintegrity.The pairof devices
- 800 Mbps SerialBus LVDS Data Rate (at80 alsofeaturesan at-speedBIST mode which allows the interconnectsbetween the SerializerandMHz Clock) Deserializertobe verifiedat-speed.• 10-bitParallelInterfacefor1 Byte Data Plus 2 ControlBits The SCAN921025H transmitsdata over backplanes or cable.The singledifferentialpairdatapathmakes• SynchronizationMode and LOCK Indicator PCB design easier.In addition,the reduced cable,• Programmable Edge Triggeron Clock PCB tracecount,and connectorsizetremendously
- High Impedance on ReceiverInputsWhen reduce cost.Since one outputtransmitsclockand Power isOff databitsserially,iteliminatesclock-to-dataand data- to-dataskew. The powerdown pin saves power by• Bus LVDS SerialOutput Rated for27Ω Load reducingsupplycurrentwhen notusingeitherdevice.• Small 49-Lead NFBGA Package Upon power up of the Serializer,you can choose to activate synchronizationmode or allow theAPPLICATIONS Deserializerto use the synchronization-to-random- datafeature.By usingthesynchronizationmode, the• Automotive Deserializerwillestablishlock to a signalwithin• Industrial specifiedlocktimes.Inaddition,theembedded clock
- Military/Aerospace ensures a transitionon the bus every 12-bitcycle. This eliminatestransmissionerrorsdue to charged cable conditions.Furthermore,you may put the SCAN921025H outputpinsintotri-statetoachievea high impedance state.The PLL can lock to frequenciesbetween 20 MHz and 80 MHz. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com Block Diagram Figure1. Application
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 FunctionalDescription The SCAN921025H and SCAN921226H are a 10-bitSerializerand Deserializerchipsetdesignedto transmit dataoverdifferentialbackplanesatclockspeeds from20 to80 MHz. The chipsetisalsocapableofdrivingdata overUnshieldedTwistedPair(UTP) cable. The chipsethas threeactivestatesof operation:Initialization,Data Transfer,and Resynchronization;and two passivestates:Powerdown and Tri-state.Inadditiontotheactiveand passivestates,therearealsotestmodes forJTAG accessand at-speedBIST. The followingsectionsdescribeeach operationand passivestateand thetestmodes. Initialization Initializationofbothdevicesmust occurbeforedatatransmissionbegins.Initializationreferstosynchronizationof the Serializerand DeserializerPLL's to localclocks,which may be the same or separate.Afterwards, synchronizationoftheDeserializertoSerializeroccurs. Step 1:When you applyVCC tobothSerializerand/orDeserializer,therespectiveoutputsentertri-state,and on- chippower-on circuitrydisablesinternalcircuitry.When VCC reaches VCC OK (2.5V)the PLL in each device beginslockingtoa localclock.For theSerializer,thelocalclockisthetransmitclock(TCLK) providedby the sourceASIC orotherdevice.FortheDeserializer,you must applya localclocktotheREFCLK pin. The Serializeroutputsremainintri-statewhilethePLL lockstotheTCLK. AfterlockingtoTCLK, theSerializeris now readytosend dataorSYNC patterns,dependingon thelevelsoftheSYNC1 and SYNC2 inputsora data stream.The SYNC patternsentby theSerializerconsistsofsixones and sixzerosswitchingattheinputclock rate. Note thatthe DeserializerLOCK outputwillremain highwhileitsPLL locksto the incomingdata or to SYNC patternson theinput. Step 2:The DeserializerPLL must synchronizetotheSerializertocompleteinitialization.The Deserializerwill locktonon-repetitivedatapatterns.However,thetransmissionofSYNC patternsenablestheDeserializertolock totheSerializersignalwithina specifiedtime.See Figure17. The user'sapplicationdeterminescontrolof the SYNC1 and SYNC 2 pins.One recommendationisa direct feedbackloopfrom the LOCK pin.Under allcircumstances,the SerializerstopssendingSYNC patternsafter bothSYNC inputsreturnlow. When theDeserializerdetectsedge transitionsattheBus LVDS input,itwillattempttolocktotheembedded clockinformation.When theDeserializerlockstotheBus LVDS clock,theLOCK outputwillgo low.When LOCK islow,theDeserializeroutputsrepresentincomingBus LVDS data. Data Transfer Afterinitialization,theSerializerwillacceptdatafrom inputsDIN0–DIN9. The Serializeruses theTCLK inputto latchincomingData. The TCLK_R/ F pin selectswhich edge the Serializeruses to strobeincomingdata. TCLK_R/ F highselectstherisingedge forclockingdataand low selectsthefallingedge.IfeitheroftheSYNC inputsishighfor5*TCLK cycles,thedataatDIN0-DIN9 isignoredregardlessofclockedge. Afterdeterminingwhich clockedge touse,a startand stopbit,appended internally,frame thedatabitsinthe register.The startbitisalways high and the stop bitisalways low.The startand stop bitsfunctionas the embedded clockbitsintheserialstream. The Serializertransmitsserializeddataand clockbits(10+2 bits)from theserialdataoutput(DO ±) at12 times theTCLK frequency.For example,ifTCLK is80 MHz, theserialrateis80 × 12 = 960 Mega-bits-per-second. Sinceonly10 bitsarefrominputdata,theserial“payload”rateis10 timestheTCLK frequency.For instance,if TCLK = 80 MHz, thepayloaddatarateis80 × 10 = 800 Mbps. The datasourceprovidesTCLK and must be in therangeof20 MHz to80 MHz nominal. The Serializeroutputs(DO ±) can drivea point-to-pointconnectionor in limitedmulti-pointor multi-drop backplanes.The outputstransmitdata when the enablepin(DEN) ishigh,PWRDN = high,and SYNC1 and SYNC2 arelow.When DEN isdrivenlow,theSerializeroutputpinswillentertri-state. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com When the Deserializersynchronizesto the Serializer,the LOCK pin is low.The Deserializerlocksto the embedded clockand uses ittorecovertheserializeddata.ROUT dataisvalidwhen LOCK islow.Otherwise ROUT0 –ROUT9 isinvalid. The ROUT0-ROUT9 pinsuse theRCLK pinas thereferencetodata.The polarityoftheRCLK edge iscontrolled by theRCLK_R/ F input.See Figure14. ROUT(0-9),LOCK and RCLK outputswilldrivea maximum ofthreeCMOS inputgates(15 pF load)witha 80 MHz clock. Resynchronization When theDeserializerPLL lockstotheembedded clockedge,theDeserializerLOCK pinassertsa low.Ifthe Deserializerloseslock,theLOCK pinoutputwillgo highand theoutputs(includingRCLK) willentertri-state. The user'ssystem monitorstheLOCK pintodetecta lossofsynchronization.Upon detection,thesystem can arrangetopulsetheSerializerSYNC1 or SYNC2 pintoresynchronize.Multipleresynchronizationapproaches are possible.One recommendationistoprovidea feedbackloopusingtheLOCK pinitselftocontrolthesync requestoftheSerializer(SYNC1 or SYNC2). Dual SYNC pinsare providedformultiplecontrolina multi-drop application.Sending sync patternsforresynchronizationisdesirablewhen locktimeswithina specifictimeare critical.However,theDeserializercan locktorandom data,whichisdiscussedinthenextsection. Random Lock Initializationand Resynchronization The initializationand resynchronizationmethods describedintheirrespectivesectionsare the fastestways to establishthelinkbetween theSerializerand Deserializer.However,theSCAN921226H can attainlocktoa data streamwithoutrequiringtheSerializertosend specialSYNC patterns.ThisallowstheSCAN921226H tooperate in“open-loop” applications.EquallyimportantistheDeserializer'sabilitytosupporthotinsertionintoa running backplane.Intheopen looporhotinsertioncase,we assume thedatastreamisessentiallyrandom.Therefore, because lock time variesdue to data stream characteristics,we cannot possiblypredictexact lock time. However, please see Table 1 forsome generalrandom locktimes under specificconditions.The primary constrainton the “random” locktimeisthe initialphase relationbetween the incomingdata and the REFCLK when theDeserializerpowers up.As describedinthenextparagraph,thedatacontainedinthedatastreamcan alsoaffectlocktime. Ifa specificpatternisrepetitive,theDeserializercouldenter“falselock”-falselyrecognizingthedatapatternas theclockingbits.We refertosuch a patternas a repetitivemulti-transition,RMT. Thisoccurswhen more than one Low-Hightransitiontakesplaceina clockcycleovermultiplecycles.Thisoccurswhen any bit,exceptDIN 9, isheld at a low stateand the adjacentbitisheld high,creatinga 0-1 transition.In the worstcase,the Deserializercouldbecome lockedtothedatapatternratherthantheclock.CircuitrywithintheSCAN921226H can detectthatthepossibilityof“falselock” exists.The circuitryaccomplishesthisby detectingmore thanone potentialpositionforclockingbits.Upon detection,the circuitrywillpreventthe LOCK outputfrom becoming activeuntilthe potential“falselock” patternchanges. The falselockdetectcircuitryexpectsthe data will eventuallychange,causingtheDeserializertoloselocktothedatapatternand thencontinuesearchingforclock bitsintheserialdatastream.GraphicalrepresentationsofRMT are shown inFigure2.PleasenotethatRMT onlyappliestobitsDIN0-DIN8. Powerdown When no data transferoccurs,you can use the Powerdown state.The Serializerand Deserializeruse the Powerdown state,a low power sleepmode, toreducepower consumption.The DeserializerentersPowerdown when you drivePWRDN and REN low.The SerializerentersPowerdown when you drivePWRDN low.In Powerdown, the PLL stopsand the outputsentertri-state,which disablesload currentand reduces supply currenttothemilliampererange.To exitPowerdown, you must drivethePWRDN pinhigh. Beforevaliddataexchanges between theSerializerand Deserializer,you must reinitializeand resynchronizethe devicestoeach other.InitializationoftheSerializertakes510 TCLK cycles.The Deserializerwillinitializeand assertLOCK highuntillocktotheBus LVDS clockoccurs.
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 Tri-state The Serializerenterstri-statewhen theDEN pinisdrivenlow.Thisputsbothdriveroutputpins(DO+ and DO −) intotri-state.When you driveDEN high,theSerializerreturnstothepreviousstate,as longas allothercontrol pinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). When you drivethe REN pin low,the Deserializerenterstri-state.Consequently,the receiveroutputpins (ROUT0 –ROUT9) and RCLK willentertri-state.The LOCK outputremainsactive,reflectingthestateofthePLL. Table1. Random Lock Times fortheSCAN921226H (1)
80 MHz Units
Maximum 18 μs Mean 3.0 μs Minimum 0.43 μs Conditions: PRBS 215,VCC = 3.3V (1) Differenceinlocktimesaredue todifferentstartingpointsinthedatapatternwithmultipleparts. TestModes InadditiontotheIEEE 1149.1testaccesstothedigitalTTL pins,theSCAN921025H and SCAN921226H have two instructionstotesttheLVDS interconnects.The firstisEXTEST. ThisisimplementedatLVDS levelsand is onlyintendedas a go no-gotest(e.g.missingcables).The second method istheRUNBIST instruction.Itisan "at-system-speed"interconnecttest.Itisexecutedinapproximately28mS witha system clockspeed of80MHz. There are two bitsinthe RX BIST data registerfornotificationof PASS/FAIL and TEST_COMPLETE. Pass indicatesthattheBER (Bit-Error-Rate)isbetterthan10-7. An importantdetailis thatonce both deviceshave the RUNBIST instructionloaded intotheirrespective instructionregisters,bothdevicesmust move intotheRTI statewithin4K system clocks(Ata SCLK of66Mhz and TCK of1MHz thisallowsfor66 TCK cycles).Thisisnota concernwhen bothdevicesareon thesame scan chainor LSP, however,itcan be a problemwithsome multi-dropdevices.Thistestmode has been simulated and verifiedusingTI'sSCANSTA111. DIN0 Held Low-DIN1 Held High Createsan RMT Pattern DIN4 Held Low-DIN5 Held High Createsan RMT Pattern Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com DIN8 Held Low-DIN9 Held High Createsan RMT Pattern Figure2. RMT PatternsSeen on theBus LVDS SerialOutput These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VCC +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VCC +0.3V) Bus LVDS ReceiverInputVoltage −0.3Vto+3.9V Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuitDuration 10mS JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature (Soldering,4 seconds) +220°C Maximum Package Power DissipationCapacity 49L NFBGA 1.47W@ 25°C Package: Package Derating: 49L NFBGA 11.8mW/ °C above +25°C θja 85°C/W HBM >2kV ESD Rating MM > 250V (1) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation. Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +125 °C ReceiverInputRange 0 2.4 V SupplyNoiseVoltage(VCC ) 100 mV P-P
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytoDIN0-9,TCLK, PWRDN, TCLK_R/ F,SYNC1, SYNC2, DEN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA -0.86 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +10 μA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytopinsPWRDN, RCLK_R/ F,REN, REFCLK = inputs;applytopins ROUT, RCLK, LOCK = outputs) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −0.62 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +15 μA VOH HighLevelOutputVoltage IOH = −9 mA 2.2 3.0 VCC V VOL Low LevelOutputVoltage IOL = 9 mA GND 0.25 0.5 V IOS OutputShortCircuitCurrent VOUT = 0V −15 −47 −85 mA IOZ Tri-stateOutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 ±0.1 +10 μA SERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsDO+ and DO −) VOD OutputDifferentialVoltage RL = 27Ω,Figure18 200 290 mV(DO+)–(DO −) ΔVOD OutputDifferentialVoltageUnbalance 35 mV VOS OffsetVoltage 1.05 1.1 1.3 V ΔVOS OffsetVoltageUnbalance 4.8 35 mV IOS D0 = 0V,DIN = High,PWRDN and DEN =OutputShortCircuitCurrent −56 −90 mA2.4V IOZ Tri-stateOutputCurrent PWRDN orDEN = 0.8V,DO = 0V orVCC −10 ±1 +10 μA IOX Power-OffOutputCurrent VCC = 0V,DO=0V or3.6V −20 ±1 +30 μA DESERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsRI+ and RI−) VTH DifferentialThresholdHighVoltage +6 +50 mV VCM = +1.1V VTL DifferentialThresholdLow Voltage −50 −12 mV IIN VIN = +2.4V,VCC = 3.6Vor0V −10 ±1 +10 μA InputCurrent VIN = 0V,VCC = 3.6Vor0V −10 ±0.05 +10 μA SERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCD SerializerSupplyCurrent RL = 27Ω f= 20 MHz 45 60 mA WorstCase Figure3 f= 80 MHz 90 105 mA ICCXD SerializerSupplyCurrentPowerdown PWRDN = 0.8V,f= 80MHz 0.2 2.0 mA DESERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCR DeserializerSupplyCurrent C L = 15 pF f= 20 MHz 50 75 mA WorstCase Figure4 f= 80 MHz 100 120 mA ICCXR DeserializerSupplyCurrent PWRDN = 0.8V,REN = 0.8V 0.36 1.0 mAPowerdown SCAN CIRCUITRY DC SPECIFICATIONS, SERIALIZER AND DESERIALIZER (appliestoSCAN pinsas noted) VIH VCC = 3.0to3.6V,pinsTCK, TMS, TDI,andHighLevelInputVoltage 2.0 VCC VTRST VIL VCC = 3.0to3.6V,pinsTCK, TMS, TDI,andLow LevelInputVoltage GND 0.8 VTRST VCL VCC = 3.0V,ICL = −18 mA, pinsTCK, TMS,InputClamp Voltage −0.85 −1.5 VTDI,and TRST IIH VCC = 3.6V,VIN = 3.6V,pinsTCK, TMS, TDI,InputCurrent 1 +10 μAand TRST IIL InputCurrent VCC = 3.6V,VIN = 0.0V,TCK Input -10 -1 μA Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units IILR VCC = 3.6V,VIN = 0V,pinsTMS, TDI,andInputCurrent -20 -10 μATRST VOH HighLevelOutputVoltage VCC = 3.0V,IOH = −12 mA, TDO output 2.2 2.6 V VOL Low LevelOutputVoltage VCC = 3.0V,IOL = 12 mA, TDO output 0.3 0.5 V IOS OutputShortCircuitCurrent VCC = 3.6V,VOUT = 0.0V,TDO output -15 -90 -120 mA IOZ Tri-stateOutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 0 +10 μA SerializerTiming Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tTCP TransmitClockPeriod 12.5 T 50.0 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime 3 6 ns tJIT psTCLK InputJitter 150 (RMS) SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tLLHT Bus LVDS Low-to-High 0.2 0.4 nsR L = 27ΩTransitionTime C L=10pF toGND tLHLT Bus LVDS High-to-Low Figure5(1) 0.25 0.4 nsTransitionTime tDIS DIN (0-9)SetuptoTCLK R L = 27Ω, 0 ns C L=10pF toGNDtDIH DIN (0-9)HoldfromTCLK 4.0 nsFigure8 tHZD DO ± HIGH to 3 10 nsTri-stateDelay tLZD DO ± LOW toTri-state 3 10 nsR L = 27Ω,Delay C L=10pF toGND tZHD DO ± Tri-statetoHIGH Figure9(2) 5 10 nsDelay tZLD DO ± Tri-statetoLOW 6.5 10 nsDelay tSPW SYNC PulseWidth 5*tTCP nsR L = 27Ω Figure11tPLD SerializerPLL Lock Time 510*tTCP 513*tTCP ns tSD SerializerDelay R L = 27Ω,Figure12 tTCP + 1.0 tTCP + 2.5 tTCP + 3.5 ns tDJIT 20MHz -330 140 psR L = 27Ω,DeterministicJitter C L=10pF -130 -40 +60 ps 80MHztoGND (3) tRJIT Random Jitter 6 10 ps (RMS) (1) tLLHT and tLHLT specificationsareGuaranteedBy Design(GBD) usingstatisticalanalysis. (2) Because theSerializerisintri-statemode, theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer. (3) tDJIT specificationsareGuaranteedBy Designusingstatisticalanalysis.
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 DeserializerTiming Requirements forREFCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 12.5 T 50.0 ns tRFDC REFCLK DutyCycle 30 50 70 % tRFCP / RatioofREFCLK toTCLK 95 1 105tTCP tRFTT REFCLK TransitionTime 3 6 ns DeserializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP ReceiveroutClock tRCP = tTCP RCLK 12.5 50.0 nsPeriod Figure12 tCLH CMOS/TTL Low-to-High 1.2 4 nsRout(0-9),TransitionTime CL = 15 pF LOCK,Figure6tCHL CMOS/TTL High-to-Low RCLK 1.1 4 nsTransitionTime tROS RCLK 0.4*tRCP 0.5*tRCP ns20MHzROUT Data Validbefore Figure14RCLK RCLK 0.35*tRCP 0.5*tRCP ns80MHz tROH 20MHz -0.4*tRCP -0.5*tRCP nsROUT Data Validafter Figure14RCLK 80MHz -0.35*tRCP -0.5*tRCP ns tRDC RCLK DutyCycle 45 50 55 % tHZR HIGH toTri-stateDelay 2.8 10 ns tLZR LOW toTri-stateDelay 2.8 10 ns Figure15 Rout(0-9) tZHR Tri-statetoHIGH Delay 4.2 10 ns tZLR Tri-statetoLOW Delay 4.2 10 ns tDSR1 DeserializerPLL Lock 20MHz 1.7 3.5 μs Time fromPWRDWN 80MHz 1.0 2.5 μs(withSYNCPAT) Figure16tDSR2 20MHz 0.65 1.5 μsDeserializerPLL Lock Figure17(1) timefromSYNCPAT 80MHz 0.29 0.8 μs tZHLK Tri-statetoHIGH Delay LOCK 3.7 12 ns(power-up) tRNMI-R VCC = 3.15to3.6V +335 80MHz psIdealNoiseMarginRight VCC = 3.0V +215Figure21 20MHz +1 ns tRNMI-L VCC = 3.15to3.6V -395 80MHz psIdealNoiseMarginLeft VCC = 3.0V -520Figure21 20MHz -1 ns (1) ForthepurposeofspecifyingdeserializerPLL performance,tDSR1 and tDSR2 arespecifiedwiththeREFCLK runningand stable,and withspecificconditionsfortheincomingdatastream(SYNCPATs). Itisrecommended thatthederserializerbe initializedusingeither tDSR1 timingortDSR2 timing.tDSR1 isthetimerequiredforthedeserializertoindicatelockupon power-uporwhen leavingthepower- down mode. Synchronizationpatternsshouldbe senttothedevicebeforeinitiatingeithercondition.tDSR2 isthetimerequiredtoindicate lockforthepowered-upand enableddeserializerwhen theinput(RI+and RI-)conditionschange fromnotreceivingdatatoreceiving synchronizationpatterns(SYNCPATs). Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com SCAN CircuitryTiming Requirements Symbol Parameter Conditions Min Typ Max Units fMAX Maximum TCK Clock 25.0 50.0 MHzFrequency tS TDI toTCK, H orL 1.0 ns tH TDI toTCK, H orL 2.0 ns tS TMS toTCK, H orL 2.5 ns R L = 500Ω,C L = 35 pF tH TMS toTCK, H orL 1.5 ns tW TCK PulseWidth,H orL 10.0 ns tW TRST PulseWidth,L 2.5 ns tREC RecoveryTime,TRST to 2.0 nsTCK
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 AC Timing Diagrams and TestCircuits Figure3. “Worst Case ” SerializerICC TestPattern Figure4. “Worst Case ” DeserializerICC TestPattern Figure5. SerializerBus LVDS Output Load and TransitionTimes Figure6. DeserializerCMOS/TTL Output Load and TransitionTimes Figure7. SerializerInputClock TransitionTime Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com Timingshown forTCLK_R/ F = LOW Figure8. SerializerSetup/HoldTimes Figure9. SerializerTri-stateTestCircuitand Timing Figure10. SerializerPLL Lock Time,and PWRDN Tri-stateDelays
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 Figure11. SYNC Timing Delays Figure12. SerializerDelay Figure13. DeserializerDelay Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com Timingshown forRCLK_R/ F = LOW DutyCycle(tRDC )= Figure14. DeserializerData ValidOut Times Figure15. DeserializerTri-stateTestCircuitand Timing
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 Figure16. DeserializerPLL Lock Times and PWRDN Tri-stateDelays Figure17. DeserializerPLL Lock Time from SyncPAT Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com VOD = (DO +)–(DO −). Differentialoutputsignalisshown as (DO+)–(DO −),deviceinData Transfermode. Figure18. VOD Diagram
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013
APPLICATION INFORMATION
USING THE SCAN921025H AND SCAN921226H The Serializerand Deserializerchipsetisan easy to use transmitterand receiverpairthatsends 10 bitsof parallelLVTTL dataovera serialBus LVDS linkup to800 Mbps. An on-boardPLL serializestheinputdataand embeds two clockbitswithinthedatastream.The Deserializeruses a separatereferenceclock(REFCLK) and an onboard PLL toextracttheclockinformationfrom theincomingdatastreamand thendeserializethedata. The Deserializermonitorstheincomingclockinformation,determineslockstatus,and assertstheLOCK output highwhen lossoflockoccurs. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Inaddition,the constantcurrentsource natureof the Bus LVDS outputsminimizesthe slopeof the speed vs.ICC curve of conventionalCMOS designs. POWERING UP THE DESERIALIZER The SCAN921226H can be powered up atany timeby followingthepropersequence.The REFCLK inputcan be runningbeforetheDeserializerpowers up,and itmust be runninginorderfortheDeserializertolocktoincoming data.The Deserializeroutputswillremainintri-stateuntiltheDeserializerdetectsdatatransmissionatitsinputs and lockstotheincomingdatastream. TRANSMITTING DATA Once you power up theSerializerand Deserializer,theymust be phase lockedtoeach othertotransmitdata. Phase lockingoccurswhen theDeserializerlockstoincomingdataor when theSerializersends patterns.The Serializersends SYNC patternswhenever the SYNC1 or SYNC2 inputsare high.The LOCK outputof the Deserializerremainshighuntilithas lockedto the incomingdata stream.ConnectingtheLOCK outputof the Deserializerto one of the SYNC inputsof the Serializerwillensure thatenough SYNC patternsare sentto achieveDeserializerlock. The Deserializercan alsolocktoincomingdataby simplypoweringup thedeviceand allowingthe“random lock” circuitrytofindand locktothedatastream. WhiletheDeserializerLOCK outputislow,dataattheDeserializeroutputs(ROUT0-9) isvalid,exceptforthe specificcase oflossoflockduringtransmissionwhich isfurtherdiscussedintheRECOVERING FROM LOCK LOSS sectionbelow. NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyreceivedata.Variousenvironmentaland systematicfactorsinclude: Serializer:TCLK jitter,VCC noise(noisebandwidthand out-of-bandnoise) Media:ISI,LargeVCM shifts Deserializer:VCC noise RECOVERING FROM LOCK LOSS In the case where the Deserializerloseslockduringdata transmission,up to 3 cyclesof data thatwere previouslyreceivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuit requiresthatinvalidclockinformationbe received4 times in a row to indicatelossof lock.Since clock informationhas been lost,itis possiblethatdata was also lostduringthese cycles.Therefore,afterthe Deserializerrelockstotheincomingdatastreamand theDeserializerLOCK pingoes low,atleastthreeprevious datacyclesshouldbe suspectforbiterrors. The Deserializercan relockto the incomingdata stream by making the Serializerresend SYNC patterns,as describedabove, or by random locking,which can take more time,depending on the data patternsbeing received. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com HOT INSERTION Allthe BLVDS devicesare hot pluggableifyou followa few rules.When inserting,ensure the Ground pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround.Random lockhotinsertionisillustratedinFigure22. PCB CONSIDERATIONS The Bus LVDS Serializerand Deserializershouldbe placedas closeto the edge connectoras possible.In multipleDeserializerapplications,thedistancefrom theDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longer stubslowertheimpedance ofthebus,increasetheloadon theSerializer,and lowerthethresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedmuch lessthan one inchfrom slotconnectors.Because transitiontimesare very faston the SerializerBus LVDS outputs,reducingstublengthsas much as possibleisthebestmethod toensuresignalintegrity. TRANSMISSION MEDIA The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationofa backplane,througha PCB trace,or throughtwistedpaircable.In point-to-pointconfiguration,the transmissionmedia need only be terminatedat the receiverend. Please note thatin point-to-pointconfiguration,the potentialof offsettingthe ground levelsof the Serializervs.the Deserializermust be considered.Also,Bus LVDS providesa +/− 1.2V common mode rangeatthereceiverinputs. FAILSAFE BIASING FOR THE SCAN921226H The SCAN921226H has an improved inputthresholdsensitivityof +/− 50mV versus +/− 100mV forthe DS92LV1210 orDS92LV1212. ThisallowsforgreaterdifferentialnoisemarginintheSCAN921226H. However, incases where thereceiverinputisnotbeingactivelydriven,theincreasedsensitivityoftheSCAN921226H can pickupnoiseas a signaland cause unintentionallocking.For example,thiscan occurwhen theinputcableis disconnected. Externalresistorscan be added tothereceivercircuitboardtopreventnoisepick-up.Typically,thenon-inverting receiverinputispulledup and theinvertingreceiverinputispulleddown by highvalueresistors.thepull-upand pull-downresistors(R1 and R 2) providea currentpath throughthe terminationresistor(RL) which biasesthe receiverinputswhen theyarenotconnectedtoan activedriver.The valueofthepull-upand pull-downresistors shouldbe chosen so thatenough currentisdrawn to providea +15mV drop acrossthe terminationresistor. Pleasesee Figure19 fortheFailsafeBiasingSetup. USING tDJIT AND tRNM TO VALIDATE SIGNAL QUALITY The parametertRNM iscalculatedby firstmeasuringhow much of the idealbitthe receiverneeds to ensure correctsampling.Afterdeterminingthisamount, what remains of the idealbitthatisavailableforexternal sourcesofnoiseiscalledtRNM .tRNM includestransmitterjitter. PleaserefertoFigure20 and Figure21 fora graphicrepresentationoftDJIT and tRNM .Also,fora more detailed explanationof tRNM , pleasesee the ApplicationNote titled'How to ValidateBLVDS SER/DES SignalIntegrity Usingan Eye Mask'(SNLA053 ). The verticallimitsofthemask aredeterminedby theSCAN921226H receiverinputthresholdof+/− 50mV. Figure19. FailsafeBiasingSetup
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 Figure20. DeterministicJitterand IdealBitPosition tRNMI-L istheidealnoisemarginon theleftofthefigure,itisa negativevaluetoindicateearlywithrespecttoideal. tRNMI-R istheidealnoisemarginon therightoftheabove figure,itisa positivevaluetoindicatelatewithrespectto ideal. Figure21. IdealDeserializerNoise Margin (tRNMI )and Sampling Window Figure22. Random Lock Hot Insertion Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com Pin Diagrams Figure23. SCAN921025HSM -Serializer(Top View) Figure24. Figure25. SCAN921226HSM -Deserializer(Top View)
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013 SerializerPin Descriptions Pin Name I/O BallId. Description DIN I A3,B1,C1, D1, Data Input.LVTTL levelsinputs.Data on thesepinsareloadedintoa 10-bit D2, D3, E1,E2, inputregister. F2,F4 TCLKR/ F I G3 TransmitClockRising/Fallingstrobeselect.LVTTL levelinput.Selects TCLK activeedge forstrobingofDIN data.Highselectsrisingedge.Low selectsfallingedge. DO+ O D7 + SerialData Output.Non-invertingBus LVDS differentialoutput. DO − O D5 − SerialData Output.InvertingBus LVDS differentialoutput. DEN I D6 SerialData OutputEnable.LVTTL levelinput.A lowputstheBus LVDS outputsintri-state. PWRDN I C7 Powerdown. LVTTL levelinput.PWRDN drivenlowshutsdown thePLL and tri-statesoutputsputtingthedeviceintoa lowpower sleepmode. TCLK I E4 TransmitClock.LVTTL levelinput.Inputfor20MHz – 80MHz systemclock. SYNC I A4,B3 AssertionofSYNC (high)foratleast1024 synchronizationsymbolstobe transmittedon theBus LVDS serialoutput.Synchronizationsymbols continuetobe sentifSYNC continuestobe asserted.TTL levelinput.The two SYNC pinsareORed. DVCC I C3, C4, E5 DigitalCircuitpower supply. DGND I A1,C2, F5,E6, DigitalCircuitground. AVCC I A5,A6,B4,B7, Analogpower supply(PLL and AnalogCircuits). AGND I B5,B6,C6, E7, Analogground(PLL and AnalogCircuits). TDI I F1 TestData InputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. TDO O G1 TestData OutputtosupportIEEE 1149.1 TMS I E3 TestMode SelectInputtosupportIEEE 1149.1.Thereisan internalpullup resistorthatdefaultsthisinputtohighperIEEE 1149.1. TCK I F3 TestClockInputtosupportIEEE 1149.1 TRST I G2 TestResetInputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. N/C N/A A2,A7,B2,C5, Leave open circuit,do notconnect D4, F6,G6, G7 Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SCAN921025H SCAN921226H
SCAN921025H,SCAN921226H SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com DeserializerPin Descriptions Pin Name I/O BallId. Description ROUT O A5,B4,B6,C4, Data Output.±9 mA CMOS leveloutputs. C7, D6, F5,F7, G4, G5 RCLKR/ F I B3 RecoveredClockRising/Fallingstrobeselect.TTL levelinput.Selects RCLK activeedge forstrobingofROUT data.Highselectsrisingedge.Low selectsfallingedge. RI+ I D2 + SerialData Input.Non-invertingBus LVDS differentialinput. RI− I C1 − SerialData Input.InvertingBus LVDS differentialinput. PWRDN I D3 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and tri-statesoutputsputtingthedeviceintoa lowpower sleepmode. LOCK O E1 LOCK goes lowwhen theDeserializerPLL locksontotheembedded clock edge.CMOS leveloutput.Totem poleoutputstructure,does notdirectly supportwiredOR connections. RCLK O E2 RecoveredClock.Paralleldatarateclockrecoveredfromembedded clock. Used tostrobeROUT, CMOS leveloutput. REN I D1 OutputEnable.TTL levelinput.When drivenlow,tri-statesROUT0 –ROUT9 and RCLK. DVCC I A7,B7,C5, C6, DigitalCircuitpower supply. DGND I A1,A6,B5,D7, DigitalCircuitground. E4,E7,G3 AVCC I B1,C2, F1,F2, Analogpower supply(PLL and AnalogCircuits). AGND I A4,B2,F3,F4, Analogground(PLL and AnalogCircuits). REFCLK I A3 Use thispintosupplya REFCLK signalfortheinternalPLL frequency. TDI I F6 TestData InputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. TDO O G6 TestData OutputtosupportIEEE 1149.1 TMS I G7 TestMode SelectInputtosupportIEEE 1149.1.Thereisan internalpullup resistorthatdefaultsthisinputtohighperIEEE 1149.1. TCK I E5 TestClockInputtosupportIEEE 1149.1 TRST I E6 TestResetInputtosupportIEEE 1149.1.Thereisan internalpullupresistor thatdefaultsthisinputtohighperIEEE 1149.1. N/C N/A A2,C3, D4, E3 Leave open circuit,do notconnect SPACER DeserializerTruthTable INPUTS OUTPUTS PWRDN REN ROUT 0:9 LOCK (2) RCLK (3)(1) H (4) H Z H Z H H Active L Active L X Z Z Z H L Z Active Z (1) ROUT and RCLK aretri-statedwhen LOCK isassertedHigh. (2) LOCK ActiveindicatestheLOCK outputwillreflectthestateoftheDeserializerwithregardtotheselecteddatastream. (3) RCLK ActiveindicatestheRCLK willbe runningiftheDeserializerislocked.The TimingofRCLK withrespecttoROUT isdetermined by RCLK_R/ F. (4) DuringPower-up.
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SCAN921025H,SCAN921226H www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013
REVISION HISTORY
Changes from RevisionB (May 2013)toRevisionC Page Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SCAN921025H SCAN921226H
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SCAN921025HSM NRND Production NFBGA (NZA) | 49 416 | JEDEC TRAY (10+1) No SNPB Level-3-235C-168 HR -40 to 125 SCAN921025 HSM SCAN921025HSM.A NRND Production NFBGA (NZA) | 49 416 | JEDEC TRAY (10+1) No SNPB Level-3-235C-168 HR -40 to 125 SCAN921025 HSM SCAN921025HSM/NOPB Active Production NFBGA (NZA) | 49 416 | EIAJ TRAY (5+1) Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921025 HSM SCAN921025HSM/NOPB.A Active Production NFBGA (NZA) | 49 416 | EIAJ TRAY (5+1) Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921025 HSM SCAN921025HSMX/NO.A Active Production NFBGA (NZA) | 49 2000 | LARGE T&R Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921025 HSM SCAN921025HSMX/NOPB Active Production NFBGA (NZA) | 49 2000 | LARGE T&R Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921025 HSM SCAN921226HSM NRND Production NFBGA (NZA) | 49 416 | EIAJ TRAY (10+1) No SNPB Level-3-235C-168 HR -40 to 125 SCAN921226 HSM SCAN921226HSM.A NRND Production NFBGA (NZA) | 49 416 | EIAJ TRAY (10+1) No SNPB Level-3-235C-168 HR -40 to 125 SCAN921226 HSM SCAN921226HSM/NOPB Active Production NFBGA (NZA) | 49 416 | EIAJ TRAY (10+1) Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921226 HSM SCAN921226HSM/NOPB.A Active Production NFBGA (NZA) | 49 416 | EIAJ TRAY (10+1) Yes SNAGCU Level-4-260C-72 HR -40 to 125 SCAN921226 HSM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
www.ti.com 7-Oct-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SCAN921025HSMX/ NOPB Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SCAN921025HSMX/NOPB NFBGA NZA 49 2000 356.0 356.0 36.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) SCAN921025HSM/ NOPB SCAN921025HSM/ NOPB.A SCAN921226HSM/ NOPB SCAN921226HSM/ NOPB.A Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE 7.1 6.9 7.1 6.9 1.5 1.3 0.41 0.31
4.8 TYP
0.8 TYP
49X 0.51 0.41 (1.1) TYP (1.1) TYP NFBGA - 1.5 mm max heightNZA0049A BALL GRID ARRAY 4220034/A 01/2025 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SYMM SYMM BALL A1 CORNER SEATING PLANE 1 2 3 4 5 6 7 A B C D E F G
0.15 C A B
0.08 C AB C
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
49X ( 0.4) (0.8) TYP (0.8) TYP NFBGA - 1.5 mm max heightNZA0049A BALL GRID ARRAY 4220034/A 01/2025 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). SYMM SYMM 1 2 3 4 5 6 7 A B C D E F G LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 49X ( 0.4) (0.8) TYP (0.8) TYP NFBGA - 1.5 mm max heightNZA0049A BALL GRID ARRAY 4220034/A 01/2025 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 15X SYMM SYMM 1 2 3 4 5 6 7 A B C D E F G
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