SCAN90CP02 NSC | Alldatasheet
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Features
n 1.5 Gbps per channel n Low power: 70 mA in dual repeater mode @1.5 Gbps n Low output jitter n Configurable 0/25/50/100% pre-emphasis drives lossy backplanes and cables n Non-blocking architecture allows 1:2 splitter, 2:1 mux, crossover, and dual buffer configurations n Flow-through pinout n LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs n IEEE 1149.1 and 1149.6 compliant n Single 3.3V supply n Separate control of inputs and outputs allows for power savings n Industrial -40 to +85˚C temperature range n 28-lead LLP package, or 32-lead LQFP package Block Diagram 20071401 FIGURE 1. SCAN90CP02 Block Diagram
I/O, Type Description DIFFERENTIAL INPUTS COMMON TO ALL MUXES IN0+ IN0− I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. IN1+ IN1− I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SWITCHED DIFFERENTIAL OUTPUTS OUT0+ OUT0− O, LVDS Inverting and non-inverting differential outputs. OUT0 ± can be connected to any one pair IN0 ±,o rI N 1±. LVDS compatible (Note 2). OUT1+ OUT1− O, LVDS Inverting and non-inverting differential outputs. OUT1 ± can be connected to any one pair IN0 ±,o rI N 1±. LVDS compatible (Note 2). DIGITAL CONTROL INTERFACE SEL0, SEL1 I, LVTTL Select Control Inputs EN0, EN1 I, LVTTL Output Enable Inputs PEM00, PEM01 I, LVTTL Channel 0 Output Pre-emphasis Control Inputs PEM10, PEM11 I, LVTTL Channel 1 Output Pre-emphasis Control Inputs TDI 19 22 I, LVTTL Test Data Input to support IEEE 1149.1 features TDO 20 23 O, LVTTL Test Data Output to support IEEE 1149.1 features TMS 18 21 I, LVTTL Test Mode Select to support IEEE 1149.1 features TCK 17 19 I, LVTTL Test Clock to support IEEE 1149.1 features TRST 21 24 I, LVTTL Test Reset to support IEEE 1149.1 features N/C 8, 28 Not Connected POWER V DD 11, 14, 16, 22, 12, 16, 18, 25, I, Power V DD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from VDD to GND plane. GND (Note 1) 5, 11, 15, 20, 26, Ground reference to LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package. Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized for point-to-point backplane and cable applications. SCAN90CP02 www.national.com 2
DAP = GND 20071404 LQFP Top View Configuration Select Truth Table SEL0 SEL1 EN0 EN1 OUT0 OUT1 Mode
0000 I N 0 I N 0 1 : 2 Splitter (IN1 powered down)
0100 I N 0 I N 1 Dual Channel Repeater
1000 I N 1 I N 0 Dual Channel Switch
1100 I N 1 I N 1 1 : 2 Splitter (IN0 powered down)
0101 I N 0 P D Single Channel Repeater (Channel 1 powered down)
1101 I N 1 P D Single Channel Switch (IN0 and OUT1 powered down)
0010 P D I N 0 Single Channel Switch (IN1 and OUT0 powered down)
0110 P D I N 1 Single Channel Repeater (Channel 0 powered down)
X X 1 1 PD PD Both Channels in Power Down Mode
0001 Invalid State*
1001 Invalid State*
1010 Invalid State*
1110 Invalid State*
PD = Power Down mode to minimize power consumption X = Don’t Care * Entering these states is not forbidden, however device operation is not defined in these states. Pre-emphasis The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per the Pre- emphasis Control Selection Table. Output Characteristics The output characteristics of the SCAN90CP02 device have been optimized for point-to-point backplane and cable appli- cations. Pre-emphasis Control Selection Table Channel 0 Channel 1 Pre-emphasis PEM01 PEM00 PEM11 PEM10 0000 0 % 0 1 0 1 25% 1 0 1 0 50% 1 1 1 1 100% SCAN90CP02 www.national.com3
FIGURE 2. SCAN90CP02 Configuration Select Decode
Absolute Maximum Ratings(Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD) −0.3V to +4.0V CMOS Input Voltage −0.3V to (V DD +0.3V) LVDS Receiver Input Voltage −0.3V to +3.6V LVDS Driver Output Voltage −0.3V to +3.6V LVDS Output Short Circuit Current 40mA Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4sec.) +260˚C Maximum Package Power Dissipation at 25˚C LLP-28 4.31 W LQFP-32 1.47W Derating above 25˚C LLP-28 34.5 mW/˚C LQFP-32 11.8 mW/˚C Thermal Resistance, θ JA LLP-28 29˚C/W LQFP-32 85˚C/W ESD Rating HBM, 1.5 kΩ, 100 pF 6.5 kV EIAJ, 0Ω, 200 pF >250V Recommended Operating Conditions Min Typ Max Unit Supply Voltage (VDD– GND) 3.0 3.3 3.6 V Receiver Input Voltage 0 3.6 V Operating Free Air Temperature −40 25 85 ˚C Junction Temperature 150 ˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 4) Max Units LVTTL DC SPECIFICATIONS(SEL0, SEL1, EN1, EN2, PEM00, PEM01, PEM10, PEM11, TDI, TCK, TMS, TRST) VIH High Level Input Voltage 2.0 V DD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current V IN =V DD =V DDMAX −10 +10 µA IIL Low Level Input Current V IN =V SS,V DD =V DDMAX −10 +10 µA IILR Low Level Input Current TDI, TMS, TRST -40 -200 µA CIN1 Input Capacitance Any Digital Input Pin to V SS 3.5 pF COUT1 Output Capacitance Any Digital Output Pin to V SS 5.5 pF VCL Input Clamp Voltage I CL = −18 mA −1.5 −0.8 V VOH High Level Output Voltage (TDO) IOH = −12 mA, V DD = 3.0 V 2.4 V IOH = −100 µA, V DD = 3.0 V V DD-0.2 V VOL Low Level Output Voltage (TDO) IOL = 12 mA, V DD = 3.0 V 0.5 V IOL = 100 µA, V DD = 3.0 V 0.2 V IOS Output Short Circuit Current TDO -15 -125 mA LVDS INPUT DC SPECIFICATIONS(IN0±, IN1±) VTH Differential Input High Threshold (Note 5) VCM = 0.8V or 1.2V or 3.55V, V DD = 3.6V 05 0 m V VTL Differential Input Low Threshold V CM = 0.8V or 1.2V or 3.55V, V DD = 3.6V −50 0 mV VID Differential Input Voltage V CM = 0.8V to 3.55V, V DD = 3.6V 100 mV VCMR Common Mode Voltage Range V ID = 150 mV, V DD = 3.6V 0.05 3.55 V CIN2 Input Capacitance IN+ or IN− to V SS 3.5 pF IIN Input Current V IN = 3.6V, VDD =V DDMAX or 0V −10 +10 µA VIN = 0V, VDD =V DDMAX or 0V −10 +10 µA SCAN90CP02 www.national.com5
Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 4) Max Units LVDS OUTPUT DC SPECIFICATIONS(OUT0±, OUT1±) VOD Differential Output Voltage, 0% Pre-emphasis (Note 5) RL = 100Ω between OUT+ and OUT− 250 400 575 mV ∆VOD Change in VOD between Complementary States −35 35 mV VOS Offset Voltage (Note 6) 1.09 1.25 1.475 V ∆VOS Change in VOS between Complementary States −35 35 mV IOS Output Short Circuit Current, One Complementary Output OUT+ or OUT− Short to GND −15 -40 mA OUT+ or OUT− Short to V DD 15 40 mA IOSB Output Short Circuit Current, both Complementary Outputs OUT+ and OUT− Short to GND −15 -30 mA OUT+ and OUT− Short to V CM 15 30 mA COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 pF SUPPLY CURRENT (Static) ICC0 Supply Current All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. 42 60 mA I CC1 Supply Current - one channel powered down Single channel crossover switch or single channel repeater modes (1 channel active, one channel in power down mode) 22 30 mA I CC2 Supply Current - one input powered down Splitter mode (One input powered down, both outputs active) 30 40 mA ICCZ TRI-STATE Supply Current Both input/output Channels in Power Down Mode 1.4 2.5 mA SWITCHING CHARACTERISTICS — LVDS OUTPUTS(Figures 3, 4) tLHT Differential Low to High Transition Time Use an alternating 1 and 0 pattern at
200 Mb/s, measure between 20% and
80% of V OD. 70 150 215 ps tHLT Differential High to Low Transition Time 50 135 180 ps tPLHD Differential Low to High Propagation Delay Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V OD
between input to output. 0.5 2.4 3.5 ns tPHLD Differential High to Low Propagation Delay 0.5 2.4 3.5 ns tSKD1 Pulse Skew |t PLHD–tPHLD| 55 120 ps tSKCC Output Channel to Channel Skew Difference in propagation delay (t PLHD or tPHLD) among all output channels in Splitter mode (any one input to all outputs). 0 130 315 ps t JIT tON Jitter (0% Pre-emphasis) (Note 7) RJ - Alternating 1 and 0 at 750 MHz 1.4 2.5 psrms DJ - K28.5 Pattern LQFP 110 140 psp-p
1.5 Gbps LLP 42 75 psp-p
TJ - PRBS 2 23-1 Pattern LQFP 125 160 psp-p
1.5 Gbps LLP 105 140 psp-p
LVDS Output Enable Time Time from ENx to OUT ± change from TRI-STATE to active. 50 110 150 ns tOFF LVDS Output Disable Time Time from ENx to OUT ± change from active to TRI-STATE. 51 2 n s SCAN90CP02 www.national.com 6
Over recommended operating supply and temperature ranges unless other specified.
25.0 MHz
should be operated at these limits. Note 4: Typical parameters are measured at V DD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 5: Differential output voltage V OD is defined as ABS(OUT+–OUT−). Differential input voltage V ID is defined as ABS(IN+–IN−). Note 6: Output offset voltage V OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. sample size of 350 hits. Total Jitter is measured peak to peak with a histogram including 3500 window hits. FIGURE 3. LVDS Signals
1.5 Gbps data rate, 0% Pre-emphasis
FIGURE 7. Typical Performance Characteristics
Design-For-Test (DfT) Features IEEE 1149.1 SUPPORT The SCAN90CP02 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. The TAP also provides access to the IEEE 1149.6 test features if AC-coupled interconnects are used. Refer to the BSDL file located on National’s website for the details of the SCAN90CP02 IEEE 1149.1 implementation. IEEE 1149.6 SUPPORT AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and meth- ods are intended to test static (DC-coupled), single ended networks. It is unable to test dynamic (AC-coupled) digital networks because the AC-coupling blocks static signals. The SCAN90CP02 - which is intended for use in up to 1.5 Gbps data paths - has been designed with IEEE 1149.6 support to enable test of AC-coupled interconnects. FAULT INSERTION StuckAt is a feature that enables the user to override logic values on any of the external pins during normal operation. StuckAt can be thought of as having the same capabilities as the IEEE-1149.1 EXTEST instruction but on a per pin bases. Because this feature occurs on a per-pin basis, normal device operation (mission mode) is possible with the excep- tion of the desired faults. For more information on any of these features, refer to Features. SCAN90CP02 www.national.com 10
Physical Dimensions inches (millimeters) unless otherwise noted LLP, Plastic, QUAD, Order Number SCAN90CP02SP (1000 piece Tape and Reel), SCAN90CP02SPX (4500 piece Tape and Reel) SCAN90CP02 www.national.com11
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LQFP, Plastic, Quad Order Number SCAN90CP02VY (250 piece Tray) SCAN90CP02VYX (1000 piece Tape and Reel) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6