SCAN50C400A

SCAN50C400A NSC | Alldatasheet

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Technical content

Features

■ Quad Backplane SERDES transceiver ■ Multiple data rates at 1.25, 2.5 or 5 Gbps ■ 40 Gbps total full duplex throughput ■ Better than 10−15 bit error rate ■ Test Modes: On-chip at-speed BIST circuitry, Loopbacks ■ On-chip LVDS and CML terminations ■ High-speed CML driver with optional signal conditioning ■ 4-bit differential source synchronous LVDS parallel I/O ■ Low-jitter PLL reference to external differential HSTL clock at 125 MHz ■ Designed for use with low cost FR4 backplane ■ TIA/EIA 644-A compatible LVDS IO ■ IEEE Draft P802.3ae D4.0 - MDIO management interface protocol compatible ■ IEEE 1149.1 (JTAG) compliant test mode ■ 1.35V for core, high-speed circuitry and MDIO ■ 3.3V ±5% for LVDS IO, Control and JTAG interface ■ Low power, 4.5W (TYP) ■ 23 mm x 23 mm thermally enhanced BGA package Typical Application 20046101 © 2007 National Semiconductor Corporation 200461 www.national.com SCAN50C400A 1.25/2.5/5.0 Gbps Quad Multi-rate Backplane Transceiver

Equivalent Functional Diagram 20046102

Ordering Information

NSID / Marking Data Rate Support (logo) # SCAN50C400AUT Lot#, Wafer# 1.25/2.5/5.0 Gbps Operation www.national.com 2 SCAN50C400A

Order Number SCAN50C400AUT See NS Package Number UFJ440A 3 www.national.com SCAN50C400A

Number I/O, Type Description HIGH-SPEED DIFFERENTIAL I/O HT1+ HT1− L22 L21 O, CML Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 1. Data is sourced from T1_1±, T1_2±, T1_3± and T1_4±. On-chip 50Ω termination resistors connect from HT1+ and HT1− to VDDHS. HT2+ HT2− J22 J21 O, CML Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 2. Data is sourced from T1_5±, T1_6±, T1_7± and T1_8±. On-chip 50Ω termination resistors connect from HT2+ and HT2− to VDDHS. HT3+ HT3− G22 G21 O, CML Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 3. Data is sourced from T2_1±, T2_2±, T2_3± and T2_4±. On-chip 50Ω termination resistors connect from HT3+ and HT3− to VDDHS. HT4+ HT4− E22 E21 O, CML Inverting and non-inverting high-speed CML differential outputs of the serializer, channel 4. Data is sourced from T2_5±, T2_6±, T2_7± and T2_8±. On-chip 50Ω termination resistors connect from HT4+ and HT4− to VDDHS. HR1+ HR1− N22 N21 I, CML Inverting and non-inverting high-speed differential inputs of the deserializer, channel 1. Data is de-serialized and output at R1_1±, R1_2±, R1_3± and R1_4±. On-chip 50Ω termination resistors connect from HR1+ and HR1− to an internal bias. HR2+ HR2− R22 R21 I, CML Inverting and non-inverting high-speed differential inputs of the deserializer, channel 2. Data is de-serialized and output at R1_5±, R1_6±, R1_7± and R1_8±. On-chip 50Ω termination resistors connect from HR2+ and HR2− to an internal bias. HR3+ HR3− U22 U21 I, CML Inverting and non-inverting high-speed differential inputs of the deserializer, channel 3. Data is de-serialized and output at R2_1±, R2_2±, R2_3± and R2_4±. On-chip 50Ω termination resistors connect from HR3+ and HR3− to an internal bias. HR4+ HR4− W22 W21 I, CML Inverting and non-inverting high-speed differential inputs of the deserializer, channel 4. Data is de-serialized and output at R2_5±, R2_6±, R2_7± and R2_8±. On-chip 50Ω termination resistors connect from HR4+ and HR4− to an internal bias. REFERENCE CLOCK SCLK+ SCLK− A16 B16 I, HSTL Inverting and non-inverting differential reference clock to the PLL for generating internal high- speed clocks. A low jitter 125 MHz ±100 ppm clock should be connected to SCLK±. All four serializers and deserializers are frequency-locked to SCLK±. A 50 Ω termination to Ground is present on each input pin. TRANSMIT INPUT DATA T1_1+ T1_1− T1_2+ T1_2− T1_3+ T1_3− T1_4+ T1_4− I, LVDS Differential transmit input data for channel 1. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T1[1–4]± are synchronous to clock T1_CLK±. Data at T1[1–4]± are serialized and output at HT1±. T1_1 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T1_CLK±. T1_5+ T1_5− T1_6+ T1_6− T1_7+ T1_7− T1_8+ T1_8− I, LVDS Differential transmit input data for channel 2. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T1[5–8]± are synchronous to clock T1_CLK±. Data at T1[5–8]± are serialized and output at HT2±. T1_5 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T1_CLK±. T1_CLK+ T1_CLK− I, LVDS Differential 625 MHz transmit nibble clock for channels 1 and 2. Data at T1[1–4]± and T1[5–8] ± are strobed-in at both rising and falling edges of T1_CLK±, forming an 8-bit input data bus at 1.25 Gbps. T1_CLK± should be frequency-locked to reference clock SCLK±. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. www.national.com 4 SCAN50C400A

Number I/O, Type Description T2_1+ T2_1− T2_2+ T2_2− T2_3+ T2_3− T2_4+ T2_4− A10 B10 I, LVDS Differential transmit input data for channel 3. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T2[1–4]± are synchronous to clock T2_CLK±. Data at T2[1–4]± are serialized and output at HT3±. T2_1 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T2_CLK±. T2_5+ T2_5− T2_6+ T2_6− T2_7+ T2_7− T2_8+ T2_8− C11 D11 C12 D12 A13 B13 A14 B14 I, LVDS Differential transmit input data for channel 4. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. T2[5–8]± are synchronous to clock T2_CLK±. Data at T2[5–8]± are serialized and output at HT4±. T2_5 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of T2_CLK±. T2_CLK+ T2_CLK− I, LVDS Differential 625 MHz transmit nibble clock for channels 3 and 4. Data at T2[1–4]± and T2[5–8] ± are strobed-in at both rising and falling edges of T2_CLK±, forming an 8-bit input data bus at 1.25 Gbps. T2_CLK± should be frequency-locked to reference clock SCLK±. An on-chip 100 Ω resistor is connected between each pair of complimentary inputs. RECEIVE OUTPUT DATA R1_1+ R1_1− R1_2+ R1_2− R1_3+ R1_3− R1_4+ R1_4− O, LVDS Channel 1 deserialized recovered data. Data at HR1± is de-serialized and output at R1[1–4]±, clocked by both rising and falling edges of R1_CLK±. R1_5+ R1_5− R1_6+ R1_6− R1_7+ R1_7− R1_8+ R1_8− O, LVDS Channel 2 deserialized recovered data. Data at HR2± is de-serialized and output at R1[5–8]±, clocked by both rising and falling edges of R1_CLK±. R1_CLK+ R1_CLK− O, LVDS Differential recovered nibble clock for channel 1 and 2. R1_CLK± is a 625 MHz clock sourced from the clock recovery PLL. R1_CLK±, together with R1[1–4]± and R1[5–8]±, form a source synchronous 8-bit output data bus at 1.25 Gbps. R2_1+ R2_1− R2_2+ R2_2− R2_3+ R2_3− R2_4+ R2_4− AB7 AA7 AB9 AA9 AB10 AA10 O, LVDS Channel 3 deserialized recovered data. Data at HR3± is de-serialized and output at R2[1–4]±, clocked by both rising and falling edges of R2_CLK±. 5 www.national.com SCAN50C400A

Number I/O, Type Description R2_5+ R2_5− R2_6+ R2_6− R2_7+ R2_7− R2_8+ R2_8− Y11 W11 Y12 W12 AB13 AA13 AB14 AA14 O, LVDS Channel 4 deserialized recovered data. Data at HR4± is de-serialized and output at R2[5–8]±, clocked by both rising and falling edges of R2_CLK±. R2_CLK+ R2_CLK− O, LVDS Differential recovered nibble clock for channel 3 and 4. R2_CLK± is a 625 MHz clock sourced from the clock recovery PLL. R2_CLK±, together with R2[1–4]± and R2[5–8]±, form a source synchronous 8-bit output data bus at 1.25 Gbps. SERIAL INTERFACE — 1.35V Levels (1.5V Tolerant) MDC AA3 I, LVCMOS Synchronous clock to the management serial data input/output interface. The clock rate can be 0 MHz–2.5 MHz. MDC can be asynchronous to transmit or receive clocks (SCLK±, T1_CLK ±, T2_CLK±, R1_CLK±, R2_CLK±). This pin includes an internal 30kΩ pull-up to the 1.35V rail. MDIO AA4 IO, LVCMOS Bi-directional management data line where control data is transferred between station management and SCAN50C400A transceiver. This pin includes an internal 30 kΩ pull-up resistor to the 1.35V rail. An external pull-up resistor is typically connected from MDIO to the 1.35V rail. PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 AB6 AB3 AB4 AB5 AA5 I, LVCMOS PHYAD0–4 define the 5-bit PHY address to the SCAN50C400A transceiver. PHYAD4 is the MSB. These pins include an internal 30kΩ pull-up to the 1.35V rail. CONTROL INTERFACE — 3.3V Levels RESETB Y4 I,LVCMOS A logic low at RESETB initiates hardware reset function. RESETB must be low for more than 1ms with SCLK running. This pin includes an internal pull-up. LSLB A5 I, LVCMOS A logic low at LSLB enables LVDS loopback test mode for all four channels. The serialized bit stream is internally connected to the high-speed serial input of each channel's deserializer. It forms a diagnosis data path from the LVDS parallel transmit inputs (T1[1-8]±, T2[1-8]±), through the SCAN50C400A, and back to the LVDS parallel LVDS outputs (R1[1-8]±, R2[1-8]±). The data inputs at HR± are ignored, but the input terminations at HR+ and HR− remain active. During normal operation, LSLB should be tied high. See Figure 6. This pin includes an internal pull-up. LSLB HSLB 1 1 Normal SERDES mode. 1 0 High-Speed Loopback enabled. 0 1 LVDS Loopback enabled. 0 0 Not recommended. SCAN50C400A defaulted to LVDS loopback. HSLB B5 I, LVCMOS A logic low at HSLB enables High-speed loopback test mode for all four channels. The deserialized data at the LVDS side are internally connected to the transmit input data of each channel's serializer. It forms a diagnosis data path from the high-speed serial inputs (HR±), through the SCAN50C400A, and back to the high-speed serial outputs (HT±). The data inputs at T1[1-8]± and T2[1-8]± are ignored, but the on-chip differential terminations remain active. During normal operation, HSLB should be tied high. See Figure 7 and truth table in LSLB description. This pin includes an internal pull-up. MODE0 MODE1 AA6 I, LVCMOS MODE0–1 selects the line data rate. These pins include internal pull-ups. MODE1 MODE0 0 0 Serializer outputs at 5 Gbps, Deserializer inputs at 5 Gbps. 1 0 Serializer outputs at 2.5 Gbps, Deserializer inputs at 2.5 Gbps. 0 1 Serializer outputs at 1.25 Gbps, Deserializer inputs at 1.25 Gbps. 1 1 Serializer outputs at 5 Gbps, Deserializer inputs at 5 Gbps. www.national.com 6 SCAN50C400A

Number I/O, Type Description PDNB Y5 I, LVCMOS A logic low at PDNB activates the hardware power down mode. In power down mode, the MDIO Management interface is not functioning. This pin includes an internal pull-down (default is OFF). SCAN INTERFACE — 3.3V Levels TRSTB A6 I, LVCMOS Test Reset Input per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. Test Reset is active low. TMS B4 I, LVCMOS Test Mode Select per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. TDI A4 I, LVCMOS Test Data Input per IEEE 1149.1. There is an internal pull-up that defaults this input to a logic high. TCK B3 I, LVCMOS Test Clock Input per IEEE 1149.1. There is an internal weak pull-down on this pin. TDO A3 O, LVCMOS Test Data Output per IEEE 1149.1. Default is TRI-STATE. RESERVED / TEST PINS RES0 RES1 RES2 RES3 RES4 RES5 B19 L19 P19 W16 AA16 AB19 Reserved for testing purposes. Do not connect. POWER VDDIO I, Power VDDIO = 3.3V ±5%. It powers the LVDS parallel IO interface, LVCMOS control logic and SCLK input stage. VDDHS I, Power VDDHS = 1.35V. It powers the high-speed CML I/O circuitry and MDIO serial control logic. GND I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path. GND and GND_PLL should both be at the same potential. VDDPLL I, Power VDDPLL− GND_PLL = 1.35V. It powers PLL circuitry of the device. GND_PLL I, Power Ground reference to PLL circuitry. GND_PLL should be tied to a solid plane through a low inductance path. GND and GND_PLL should both be at the same potential. NO CONNECT NC Not used by SCAN50C400A. 7 www.national.com SCAN50C400A

Pin Descriptions - Power Pin / Type / Ball Number Pin Name Voltage Ball Numbers VDDIO 3.3V E5, E6, E7, E8, F5, G5, H5, J5, K5, L5, M5, N5, P5, R5, T5, U5, V5, V6, V7, V8 VDDPLL 1.35V G18, H18, J18, K18, L18, M18, N18, P18, R18, T18 VDDHS 1.35V E10, E11, E12, E13, E14, E15, E16, E17, E18 V10, V11, V12, V13, V14, V15, V16, V17, V18, T4 D14, D17, D19, F19, H19, K19, W14, D21, F21, H21, P21, T21, V21 GND 0V E1, F1, J1, L1, M1, P1, U1, V1 C3, D3, H3, L3, M3, R3, T3, W3, Y3 C5, C7, Y7, A8, AB8, Y9, C10, Y10, A12, AB12, C13, Y13 D15, Y15, AB15, B18, Y18, AB18, D22, F22, H22, K22, M22, P22, T22, V22, Y22 G7, H7, J7, K7, L7, M7, N7, P7, R7, T7 G8, H8, J8, K8, L8, M8, N8, P8, R8, T8 G9, H9, J9, K9, L9, M9, N9, P9, R9, T9 G10, H10, J10, K10, L10, M10, N10, P10, R10, T10 G11, H11, J11, K11, L11, M11, N11, P11, R11, T11 G12, H12, J12, K12, L12, M12, N12, P12, R12, T12 G13, H13, J13, K13, L13, M13, N13, P13, R13, T13 GND_PLL 0V G14, H14, J14, K14, L14, M14, N14, P14, R14, T14 G15, H15, J15, K15, L15, M15, N15, P15, R15, T15 G16, H16, J16, K16, L16, M16, N16, P16, R16, T16 NC Float A1, B1, AA1, AB1, A2, B2, E2, F2, J2, L2, M2, P2, U2, V2, AA2, AB2 G3, C4, D4, G4, H4, L4, M4, R4, W4, D5, W5, D7, W7, B8, AA8 C9, D9, E9, V9, W9, D10, W10, A11, B11, AA11, AB11, B12, AA12, D13, W13 C14, Y14, A15, B15, C15, W15, AA15 C16, D16, Y16, AB16, A17, B17, C17, W17, Y17, AA17 A18, C18, D18, F18, U18, W18, AA18 A19, C19, E19, G19, J19, M19, N19, R19, T19, U19, V19, W19, Y19, AA19 A20, B20, C20, D20, E20, F20, G20, H20, J20, K20, L20, M20, N20, P20, R20, T20, U20, V20, W20, Y20, AA20, AB20 A21, B21, C21, K21, M21, Y21, AA21, AB21 A22, B22, C22, AA22, AB22 AB17 Note: I = Input O = Output IO = Input/Output www.national.com 8 SCAN50C400A

FIGURE 1. SCLK± Driven by HSTL Clock Driver / Crystals

DATA RATE / DEVICE CONFIGURATION SCAN50C400A supports multiple data rates at 1.25, 2.50 or 5.0 Gbps selected by two control pins, MODE0 and MODE1. SCLK± is fixed at 125 MHz, and the transfer rate at the parallel LVDS side is also fixed at 1.25 Gbps, regardless of the line data rate selected. The SCAN50C400A is a selectable 1:1, 2:1 or 4:1 serializer/deserializer at line data rate of 1.25, 2.5, or 5.0 Gbps. See Figure 2. Mode control is set at power-up via the MODE0 and MODE1 pins. These pins include internal pull-up devices, thus default to (1,1) 5 Gbps Mode if undriven. After power-up the mode of the device may be changed at any time. When mode is changed data integrity is not guaranteed until after each ac- tive channel has re-locked. Lock time is dependant upon the data pattern. MODE1 MODE0 Description

5.0 Gbps, 4:1 Serializer/Deserializer

T1[1-4]± to HT1±. LSB T1_1± is the first bit transmitted. T1[5-8]± to HT2±. LSB T1_5± is the first bit transmitted. T2[1-4]± to HT3±. LSB T2_1± is the first bit transmitted. T2[5-8]± to HT4±. LSB T2_5± is the first bit transmitted. HR1± to R1[1-4]±. LSB R1_1± is the first bit received. HR2± to R1[5-8]±. LSB R1_5± is the first bit received. HR3± to R2[1-4]±. LSB R2_1± is the first bit received. HR4± to R2[5-8]±. LSB R2_5± is the first bit received. 1 0 2.5 Gbps, 2:1 Serializer/Deserializer (T1_1±, T1_3±) to HT1±. LSB T1_1± is the first bit transmitted. T1_2± and T1_4± are ignored. (T1_5±, T1_7±) to HT2±. LSB T1_5± is the first bit transmitted. T1_6± and T1_8± are ignored. (T2_1±, T2_3±) to HT3±. LSB T2_1± is the first bit transmitted. T2_2± and T2_4± are ignored. (T2_5±, T2_7±) to HT4±. LSB T2_5± is the first bit transmitted. T2_6± and T2_8± are ignored. HR1± to (R1_1±, R1_3±). LSB R1_1± is the first bit received. HR2± to (R1_5±, R1_7±). LSB R1_5± is the first bit received. HR3± to (R2_1±, R2_3±). LSB R2_1± is the first bit received. HR4± to (R2_5±, R2_7±). LSB R2_5± is the first bit received. 0 1 1.25 Gbps, Feed-through 1:1 Serializer/Deserializer. T1_1± to HT1±. T1[2-4]± are ignored. T1_5± to HT2±. T1[6-8]]± are ignored. T2_1± to HT3±. T2[2-4]± are ignored. T2_5± to HT4±. T2[6-8]± are ignored. HR1± to R1_1±. R1[2-4]± replicate R1_1±. HR2± to R1_5±. R1[6-8]± replicate R1_5±. HR3± to R2_1±. R2[2-4]± replicate R2_1±. HR4± to R2_5±. R2[6-8]± replicate R2_5±. www.national.com 10 SCAN50C400A

FIGURE 2. SCAN50C400A at 5, 2.5 and 1.25 Gbps Modes, Channel 1 Shown (x = don't care)

FIGURE 4. High-Speed CML Output Waveforms with signal conditioning enabled

diagram of the recovered LVDS data bus. FIGURE 5. High-Speed IO, AC Coupled

with LVDS loopback test mode, activated by pulling LSLB low. and defaults to normal SERDES mode. FIGURE 6. SCAN50C400A in LVDS Loopback (Channel 1 at 5 Gbps Shown) puts of the serializer and output at the CML outputs HT±. mote loopback, or line loopback. For normal operation, HSLB and LSLB should be driven high. pull-up and defaults to normal SERDES mode.

FIGURE 7. SCAN50C400A in High-Speed Loopback (5 Gbps Shown) 0 0 Not Recommended. Defaults to LVDS Loopback Mode. default values, and the MDIO management bus is inhibited. Interface. See Control Register 1 (offset=30.1) for details. functional, but all registers are preset to their default values. both LSLB and HSLB are at a logic high..

UN-USED INPUTS AND FAILSAFE CONDITIONS When LVDS inputs are open, internal fail-safe circuitry will force both of them low, and the high-speed CML drivers will output a logic low. (See specific conditions in table below). When CML inputs are open, the internal clock/data recovery circuitry will be frequency-locked to the SCLK clock. The LVDS output drivers will be forced to static logic high. LVCMOS inputs (MODE0, MODE1, LSLB, HSLB, RESETB) have internal pull-up resistors to 3.3V rail. 5 Gbps normal SERDES mode is the default state. LVCMOS input PDNB has an internal pull-down resistors. This must be driven or tied high to enable the device. All Serial Management Interface pins (MDC, MDIO, PHYADn) have internal pull-high resistors. Typical pull-up is 30 kΩ to the 1.35V rail. Failsafe Condition Table—Serializer INPUTS OUTPUTS SCLK TCLK LVDS DATA INPUTS CML OUTPUTS NotesTn+ Tn− HTn+ HTn− running running floating floating Low High Logic Low running floating since power-up X X Low High Logic Low running Static since power-up X X Low High Logic Low running Running, then float or static X X Last valid state Last valid state Logic High or Low floating X X X High High Both High, 0V Differential X = either High or Low Failsafe Condition Table—Deserializer INPUTS OUTPUTS SCLK CML INPUTS LVDS DATA OUTPUTS Rn-CLK NotesHR+ HR− Rn+ Rn− running floating floating High Low Running (625 MHz) Logic High floating X X High Low Running (<600 MHz) Logic High X = either High or Low JTAG - IEEE 1149.1 The TDI, TDO, TMS, TCK, and TRSTB pins provide the JTAG interface. Per IEEE 1149.1 TDI, TMS, and TRSTB include in- ternal pull-up devices. TCK pin provides a weak pull-down device. All JTAG inputs are 3.3V compatible. The TDO pin default state is TRI-STATE. Additional JTAG details can be found in the device BSDL file. Please contact your local rep- resentative to get a copy of this file.. 17 www.national.com SCAN50C400A

SCAN50C400A as the Deserializer (RX). amble of continuous zero's or continuous one's. Interface section of this datasheet.

1. Select and or customize the test pattern
2. Enable both the Serializer and Deserializer BIST
3. Run the test for a user-defined amount of time
4. Disable the Serializer and Deserializer BIST functions
5. Read result of the test from the BIST Status Registers

trolled by the time duration between step #2 and #5 above. 20,000 seconds is required (almost 6 hours). ception of LVDS IO and high-speed IO. [CCCC’h] represents a maximum transition 2.5 Gbps pattern. burden of processing data for test purposes. FIGURE 8. At-speed BIST Modes Used with Local Loopback

SERIAL CONTROL INTERFACE (MDIO) The serial control interface allows communication between a station management controller and the SCAN50C400A de- vices. It can be used to configure the CML drivers' output level, enable BIST and obtain test results from BIST. It is pro- tocol compatible to the station management bus defined in IEEE Draft P802.3ae/D4.0. The serial control interface con- sists of two pins, the data clock MDC and bi-directional data MDIO. MDC has a maximum clock rate of 2.5 MHz and no minimum limit. The MDIO is bi-directional and can be shared by up to 32 PHY's. Note that with many SCAN50C400A devices in parallel, the internal pull-up will be in the range of 937 Ω (30kΩ/32). The parallel equivalence of the internal resistance and the exter- nal pull up should not be less than 250Ω. Signal quality on the net should provide incident wave switching. It may be desir- able to control the edge rate of MDC and MDIO from the station management controller to optimize signal quality de- pending upon the trace net and any resulting stub lengths. The MDIO pin typically uses an external pull-up resistor (5 k Ω), which during IDLE and bus turn-around, will pull MDIO high. In order to initialize the MDIO interface, the station management sends a sequence of 32 contiguous logic ones on MDIO with MDC clocking. This preamble may be gener- ated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO high for 32 MDC clock cycles. A preamble is required for every operation (64-bit frames, do not suppress preambles). MDC is an aperiodic signal. Its high or low duration is 160 ns minimum and has no maximum limit. Its period is 400 ns max- imum. MDC can be asynchronous to SCLK±, T1_CLK±, Table 1 shows the management frame structure in according to IEEE Draft P802.3ae/D4.0. <1…1> is a sequence of 32 contiguous one's at MDIO used as Preamble for synchronization purpose. <PPPPP> is the PHY address of the device, defined by the logic states of PHYAD0-4. The MSB bit is the first bit trans- mitted or received. The PHY address is read at power-up or after a RESET event. <EEEEE> is the device (register) address. The MSB bit is the first bit transmitted or received. SCAN50C400A supports de- vice address of 30 for accessing vendor specific registers (<EEEEE>=30 decimal, 1E hex). <AAAA AAAA AAAA AAAA> is the 16-bit address field of the register to be accessed. The first bit transmitted or received is bit 15. <DDDD DDDD DDDD DDDD> is the 16-bit data field. It is the data to be written into the SCAN50C400A when performing a Write operation. During the Read or Read-Increment-Address operation, it is the read-back data from the SCAN50C400A. The first bit transmitted or received is bit 15. The MDIO Interface is not active when the SCAN50C400A is in hardware RESET mode or powerdown mode. 19 www.national.com SCAN50C400A

TABLE 1. Protocol of Management Bus

• Correct PHY ADD, Correct DEV ADD — expected content
• Incorrect PHY ADD, Correct DEV ADD — FFFF’h
• Correct PHY ADD, Incorrect DEV ADD — 0000’h
• RESETB = Low — FFFF’h Additional information on the Serial Control Interface is pro- vided in National’s Application Note AN-1242. REGISTERS The SCAN50C400A implements the Device Identifier and its device-specified features in the vendor specific registers. Table 2 shows the user registers implemented in the SCAN50C400A. There are also reserved registers not listed which are used for in- house testing on the SCAN50C400A. To prevent putting the device into unspecified operating states, users must not write to reserved registers not listed in Table 2. The SCAN50C400A will ignore any write to registers not supported, and return 0 for any read from non-supported registers. The SCAN50C400A will also ignore any management access using the Start-code of <01> as as Reg <30.offset>.

TABLE 2. User Registers Implemented in the SCAN50C400A and Defaults 30.2 RO Device Identifier Register 1. 30.3 RO Device Identifier Register 2. 30.4 RW Loopback Control Register. 30.5 RW TX Signal Conditioning Control Register 1. 30.6 RW TX Signal Conditioning Control Register 2. 30.11 RW Control Register 2. 30.12 RW BIST TX Control Register. 30.13 RW BIST RX Control Register. 30.14 RO Package Identifier (Copy of 30.2). 30.15 RO Package Identifier (Copy of 30.3). 30.16-31 RW TX BIST Fixed Pattern Registers. 30.32-47 RW RX BIST Fixed Pattern Registers. 30.49 RW TX CML VOD Control Register. 30.57 RO BIST Status Register for Channel 1. 30.58 RO BIST Status Register for Channel 2. 30.59 RO BIST Status Register for Channel 3. 30.60 RO BIST Status Register for Channel 4.

Control Register 1 (Offset=30.1) Bit Bit Name Access Default Description 15:8 SW_PDNB RW FF ′h SW_PDNB is the active low software power-down for individual serializers or deserializers. During software power-down, the MDIO serial interface remains functional. The user must program SW_PDNB HIGH to exit power-down mode. The PDNB pin overrides SW_PWDNB. D15=0: Activates software power-down on Channel 4 Deserializer. D14=0: Activates software power-down on Channel 3 Deserializer. D13=0: Activates software power-down on Channel 2 Deserializer. D12=0: Activates software power-down on Channel 1 Deserializer. D11=0: Activates software power-down on Channel 4 Serializer. D10=0: Activates software power-down on Channel 3 Serializer. D9=0: Activates software power-down on Channel 2 Serializer. D8=0: Activates software power-down on Channel 1 Serializer. 7:0 SW_RSTB RW FF ′h SW_RSTB is the active low software reset for individual serializers or deserializers. SW_RSTB should be LOW for more than 10us. During software reset, the MDIO serial interface remains functional. Software reset can be activated only during normal operating mode (i.e. LSLB and HSLB are both HIGH). The user is required to program SW_RSTB high to exit software reset. The RESETB pin overrides SW_RSTB. D7=0: Activates software reset on Channel 4 Deserializer. D6=0: Activates software reset on Channel 3 Deserializer. D5=0: Activates software reset on Channel 2 Deserializer. D4=0: Activates software reset on Channel 1 Deserializer. D3=0: Activates software reset on Channel 4 Serializer. D2=0: Activates software reset on Channel 3 Serializer. D1=0: Activates software reset on Channel 2 Serializer. D0=0: Activates software reset on Channel 1 Serializer. Device Identifier Register 1 (Offset=30.2) Package Identifier Register 1 (Offset=30.14) Bit Bit Name Access Default Description 15:0 ID_MSB RO A000 ′h Bits 3 to 18 of the ID are stored in bits 15 to 0 of this register. National's ID is 080017 ′h 21 www.national.com SCAN50C400A

Device Identifier Register 2 (Offset=30.3) Package Identifier Register 2 (Offset=30.15) Bit Bit Name Access Default Description 15:10 ID_LSB RO 01 0000 ′b ID_LSB Bits 19 to 24 of the ID are mapped to bits 15 to 10 of this register. 9:4 VNDR_MDL RO 10 0000 ′b Vendor Model Number Bits 9 to 4 contain the 6-bit vendor model number. Bit 9 is the MSB. 3:0 REV_NUM RO 1010 ′b Model Revision Number Bits 3 to 0 contain the 4-bit model revision number. This field will be incremented for all major device changes. Loopback Control Register (Offset=30.4) Bit Bit Name Access Default Description 15:2 Reserved NA Reserved 1:0 LP_BK RW 11 ′b Software control for internal loopback test modes. D1 D0 1 1 Normal operating mode. 1 0 LVDS loopback (also called Local serial loopback). 0 1 High-speed loopback (also called Line Loopback). 0 0 Not recommended, defaulted to the LVDS loopback. The user is required to set LP_BK to high to exit loopback mode and return to the normal operating mode. The LSLB and HSLB pins override the software loopback control bits. TX Signal Conditioning Control Register 1,2 (Offset=30.5, 30.6) Register 30.5 Register 30.6 De-emphasis (in dB) VODSB (mVP-P) VODS2 (mVP-P) 0000’h 0000’h 0 (Default) 1100 1100 F224’h 0D44’h −1.6 715 590 F234’h 0A46’h −3.5 710 470 F040’h 0808’h −6.5 880 420 F448’h 0688’h −8.5 850 320 Status Register (Offset=30.8) Bit Bit Name Access Default Description 15:14 DEV_PRESENT RO 8000 ′h D15 D14 1 0 Device responding at this address. 1 1 No device responding. 0 1 No device responding. 0 0 No device responding. 13:0 Reserved Do not Access www.national.com 22 SCAN50C400A

Control Register 2 (Offset=30.11) Bit Bit Name Access Default Description 15:12 DISABLE_LVDS RW 0 ′h Disable the LVDS output stages of individual deserializer, during which the LVDS outputs are held at logic high (+VOD). D15=1: Disable LVDS outputs of CH 4 DES (R2[5–8]±). D14=1: Disable LVDS outputs of CH 3 DES (R2[1–4]±). D13=1: Disable LVDS outputs of CH 2 DES (R1[5–8]±). D12=1: Disable LVDS outputs of CH 1 DES(R1[1–4]±). The user is required to set D15:12 to 0’h for normal operating mode. 11:8 DISABLE_HT RW 0 ′h Disable the high-speed CML output stage of individual serializer, during which both the high-speed outputs HT+ and HT− are forced to static high. During LVDS loopback (local loopback) test mode, DISABLE_HT is the default mode. When EN_BIST_TX is activated, DISABLE_HT is automatically overridden. D11=1: Disable high-speed CML outputs of CH 4 SER (HT4±). D10=1: Disable high-speed CML outputs of CH 3 SER (HT3±). D9=1: Disable high-speed CML outputs of CH 2 SER (HT2±). D8=1: Disable high-speed CML outputs of CH 1 SER (HT1±). The user must set D11:8 to 0’h for normal operating mode. 7:4 EN_BIST_RX RW 0 ′h Enables built-in-self-test (BIST) of individual deserializer. The receiver will start looking for a synchronization header from the incoming bit stream. When header is detected, the error detection function is activated. Any error detected will be reported to bits 7:0 of BIST Status Registers. It is important for the user to de-activate the BIST mode of the deserializer (de-assert EN_BIST_RX), then de-activate the BIST mode of the serializer (de-assert EN_BIST_TX) in order to properly exit from self-test. Duration (total bits sent) is controlled by the user and is calculated based on operating data rate and duration of test. For more details, please see Application Note AN-1328. Note - the BIST function overrides output enable controls. D7=1: Enables BIST for Channel 4 Deserializer. D6=1: Enables BIST for Channel 3 Deserializer. D5=1: Enables BIST for Channel 2 Deserializer. D4=1: Enables BIST for Channel 1 Deserializer. The user is required to set EN_BIST_RX to 0’h for normal operating mode. 3:0 EN_BIST_TX RW 0 ′h Enables built-in-self-test (BIST) of individual serializer. The selected test pattern will be sent out at HT± of the serializer. When EN_BIST_TX is de-asserted, the last data word is sent out before terminating the self- test test mode. Duration (total bits sent) is controlled by the user and is calculated based on operating data rate and duration of test. Please see the EN_BIST_RX section for the appropriate steps to properly synchronize the serializer and deserializer. Note - the BIST function overrides output enable controls. D3=1: Enable BIST of Channel 4 Serializer. D2=1: Enable BIST of Channel 3 Serializer. D1=1: Enable BIST of Channel 2 Serializer. D0=1: Enable BIST of Channel 1 Serializer. The user is required to set EN_BIST_TX to 0’h for normal operating mode. BIST TX Control Register (Offset=30.12) BIST RX Control Register (Offset=30.13) 23 www.national.com SCAN50C400A

Bit 15:0 Description 3FF1 ′h Selects PRW7 test pattern. 3FF5 ′h Selects PRW13 test pattern. 3FF3 ′h Selects ONE-PRW7-ZERO pattern. 3FF2 ′h Selects ZERO-PRW7-ONE pattern. 3FF0 ′h Selects Memory-based test pattern defined by registers 30.16 to 30.31. www.national.com 24 SCAN50C400A

TX Fixed Pattern Registers (Offset=30.16–30.31) Bit Bit Name Access Default Description 15:0 TX_PAT RW AAAA ′h There are 16 registers (30.16 to 30.31) for users to store 256 bits of user-defined data bits to be transmitted at HT when the serializer's built- in-self-test mode is turned on. All 256 bits are transmitted sequentially. D0 of register 30.16 is the first bit transmitted. After the last bit (D15 of register 30.31) is transmitted, the SCAN50C400A will loop the test pattern and restart at D0 of register 30.16, forming a repeating fix pattern. RX Fixed Pattern Registers (Offset=30.32–30.47) Bit Bit Name Access Default Description 15:0 RX_PAT RW AAAA ′h There are 16 registers (30.32 to 30.47) for users to store 256 bits of user-defined data bits that are used as the expected received bits for the incoming bit stream. When the deserializer's BIST mode is turned on and fix pattern is selected, the on-chip BIST Error Detector will compare the recovered data bits against the user-defined expected data stored in registers 30.32–30.47, once a valid synchronization header is detected. D0 of register 30.32 is the first bit compared. TX CML VOD Control Register (Offset=30.49) Bit Bit Name Access Default Description 15:13 Reserved NA Reserved. 12:10 9:7 6:4 3:1 VOD4 VOD3 VOD2 VOD1 RW RW RW RW 001’b 001’b 001’b 001’b VOD4 is a 3-bit control that selects one of the 8 output levels at HT4. VOD3 is a 3-bit control that selects one of the 8 output levels at HT3. VOD2 is a 3-bit control that selects one of the 8 output levels at HT2. VOD1 is a 3-bit control that selects one of the 8 output levels at HT1. VOD4/ VOD3/ VOD2/ VOD1 Differential output level in mVp-p 000 001 010 011 100 101 110 111 1300 1100 860 840 810 760 700 630 0 Reserved NA Reserved. 25 www.national.com SCAN50C400A

15:12 Reserved. NA Reserved.

11 BIST_HDR RO 0’b Transmitter sends a header and then will stay High until BIST is

10 BIST_ST RO 0 ′b BIST_ST=1 indicates detection of synchronization header.

9 BIST_END RO 0 ′b On receipt of user's command to terminate the deserializer's BIST

8 BIST_OK RO 0 ′b BIST_OK=0 indicates no error has been detected. BIST_OK is valid only after BIST_ST is at a logic 1 state. RX_BIST has been re-started.. BIST_ERR has a value of 0–255. FIGURE 9. Transmit Data Timing

FIGURE 10. Receive Data Timing

Physical Dimensions inches (millimeters) unless otherwise noted Order Number SCAN50C400AUT www.national.com 28 SCAN50C400A

29 www.national.com SCAN50C400A

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