SCAN25100TYA/NOPB

SCAN25100_16 TI1 | Alldatasheet

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 SCAN251002457.6,1228.8,and614.4MbpsCPRISerDeswithAutoRESyncand PrecisionDelayCalibrationMeasurement Check forSamples: SCAN25100 1FEATURES DESCRIPTION The SCAN25100 is a 2457.6,1228.8,and 614.4 2• Exceeds LV and HV CPRI Voltageand Jitter Mbps serializer/deseralizer(SerDes)forhigh-speedRequirements bidirectionalserialdata transmissionover FR-4• 2457.6,1228.8,and 614.4Mbps Operation printedcircuitboard backplanes,balanced cables,

IntegratedDelay CalibrationMeasurement and opticalfiber.The SCAN25100 integrates precisiondelay calibrationmeasurement (DCM)(DCM) DirectlyMeasures T14 and Toffset circuitrythat measures linkdelay components toDelays to≤ ± 800 ps betterthan± 800 ps accuracy.• DCM Also Measures Chip and Other Delays to ≤ ± 1200 ps Accuracy The SCAN25100 featuresindependenttransmitand receivePLLs, on-chiposcillator,and intelligentclock• DeterministicChip Latency management circuitryto automaticallyperform• IndependentTransmitand Receive PLLs for remote radiohead synchronizationand reduce theSeamless RE Synchronization costand complexityofexternalclocknetworks.
Low Noise Recovered Clock Output The SCAN25100 isprogrammable though an MDIO
RequiresNo JitterCleaninginSingle-Hop interfaceas well as through pins, featuring Applications configurable transmitterde-emphasis, receiver equalization,speed rate selection,internalpattern• >8 kV ESD on theCML IO,>7 kV on AllOther generation/verification,and loop back modes. InPins,>2 kV CDM additionto at-speedBIST, the SCAN25100 includes• Hot Plug Protection IEEE 1149.1and 1149.6testability.
LOS, LOF, 8b/10bLineCode Violation, Comma, and ReceiverPLL Lock Reporting
Programmable Hyperframe Length and Startof Hyperframe Character
Programmable TransmitDe-Emphasis and Receive EqualizationWith On-Chip Termination
Advanced TestabilityFeatures – IEEE 1149.1and 1149.6 – At-Speed BIST PatternGenerator/Verifier – MultipleLoopback Modes
1.8Vor 3.3VCompatible ParallelBus Interface
100-pinHTQFP Package withExposed Dap
Industrial–40 to+85° C Temperature Range Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SPMODE[0] PE[0] AVDD18 EQ[0] EQ[1] OPMODE LOOP[0] LOOP[1] PE[1] GND IOVDD CALIGN_EN RXCLKMODE SPMODE[1] TENBMODE SCAN25100 52 53 54 55 56 57 58 59 60 6172 62 63 64 65 66 67 68 69 70 7173 74 25 24 23 22 21 20 19 18 17 16 154 14 13 12 11 10 9 8 7 6 53 2 1 100 DIN[8] DIN[7] DIN[6] DIN[9] GND DIN[3] DIN[2] ROUT[8] ROUT[7] ROUT[3] ROUT[2] DIN[4] DIN[1] GND ROUT[9] ROUT[4] RXCLK IOVDD DIN[5] DIN[0] TXCLK ROUT[6] ROUT[5] ROUT[1] ROUT[0] GND GND GND PVDD33 PVDD33 AVDD33 AVDD18 AVDD18 GND AVDD18 AVDD33 REFCLKN GND GND AVDD33 GND GND GND REFCLKP DOUTN DOUTP RINN RINP SYSCLKP SYSCLKN GND AVDD18 TRSTB GND IOVDD TCK AVDD33 ADD1 ADD2 MDIO MDC TMS TDO AVDD18 ADD0 AVDD18 GND GND TDI GND GND ADD3 ADD4 PVDD33 PVDD33 PIN 101 ON BOTTOM OF PKG DAP / GND ROUT [0:9] PLL Parallel to Serial De- Emphasis DOUT r REFCLK (30.72 MHz) MDIO Rate Select etc. Pin Control Pattern Generator RIN r DIN [0:9] TXCLK RXCLK LOS SYSCLK (30.72 MHz) 8b/10b Encoder Pattern Verifier JTAG Serial to Parrallel CDR 8b/10b Decoder Output FIFO Input FIFO Equalizer Control Local Loop Back Special Line Loop Back Line Loop Back Special Local Loop Back Precision Delay Calibration Measurement Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay Calibration (Enable, Measurement) REFCLK CDR Clock SCAN25100 SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Block Diagram Pin Diagram Figure1. SCAN25100- Top View 100–Pin HTQFP withExposed Ground Pad See Package Drawing PFD0100B

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin # Pin Name I/O,Type Description HIGH SPEED DIFFERENTIAL I/O 12 DOUTP O, CML Invertingand non-invertinghighspeed CML differentialoutputsoftheserializer.On-chip

11 DOUTN terminationresistorsconnectfromDO+ and DO − toan internalreference

18 RINP I,CML Invertingand non-invertinghighspeed differentialinputsofthedeseralizer.On-chip 17 RINN terminationresistorsconnectfromRI+ and RI− toan internalreference.On-chip terminationresistorsareconfiguredforAC-coupledapplications. PARALLEL DATA BUS 65 DIN [0] I,LVTTL or1.8V Transmitdataword.

66 DIN [1] LVCMOS Internal

67 DIN [2] pulldown In10-bitmode, the10-bitcode-groupatDIN [0–9]isserializedwiththeinternal8b/10b

68 DIN [3] encoderdisabled.Bit9 isthemsb.

69 DIN [4]

70 DIN [5] In8-bitmode, DIN [0-7]isfirstconvertedinto10-bitcode-groupby theinternal8b/10b

71 DIN [6] encoderbeforeitisserialized.Bit7 isthemsb. DIN [8]isused as K-codeselectpinand 72 DIN [7] DIN[9]shouldbe tiedLow. When DIN [8]islow,DIN [0-7]ismapped tothe 73 DIN [8] corresponding10-bitD-group.When DIN [8]ishigh,DIN [0-7]ismapped tothe 74 DIN [9] corresponding10-bitK-group. The 8B/10B specificationisdefinedinIEEE 802.3-2000section36.2.2 53 ROUT [0] O, LVTTL or1.8V Deserializedreceivedataword.

54 ROUT [1] LVCMOS Internal

55 ROUT [2] pulldown In10-bitmode, ROUT [0-9]isthedeserializedreceiveddataword in10-bitcode group. 56 ROUT [3] Bit9 isthemsb.

57 ROUT [4]

58 ROUT [5] In8-bitmode, ROUT [0-7]isthedeserializedreceiveddatabyte.Bit7 isthemsb. ROUT 59 ROUT [6] [8]istheK-groupindicator.A lowatROUT [8]indicatesROUT [0-7]belongstotheD- 60 ROUT [7] group,whilea highindicatesitbelongstotheK-group.ROUT [9]isthelinecode 61 ROUT [8] violation(LCV)indicator.ROUT [9]ishighforone ROUT cyclewhen a linecode 62 ROUT [9] violationoccurs. The 8B/10B specificationisdefinedinIEEE 802.3-2000section36.2.2 CLOCK SIGNALS 6 REFCLKP I,LVDS or Invertingand non-invertingdifferentialserializerreferenceclock.A lowjitterclock 7 REFCLKN LVPECL sourceshouldbe connectedtoREFCLKP & REFCLKN. 64 TXCLK I,LVTTL or1.8V Transmitclock.TXCLK must be synchronoustoREFCLK toavoidFIFO over/underflow LVCMOS Internalthoughitmay differinphase. pulldown 52 RXCLK I/O,LVTTL or1.8V Writemode: RXCLK isa recoveredclockoutputpin. LVCMOS Read mode: RXCLK isan inputpin.ROUT [9:0]arelatchedouton RXCLK risingand fallingedges.RXCLK must be synchronoustotheincomingserialdatatoavoidFIFO over/underflow,thoughitmay differinphase.See RXCLKMODE pindescriptionfor more details. 22 SYSCLKP O, LVDS 30.72MHz outputclock.(OPMODE must be low.)

23 SYSCLKN

78 LOS O, LVTTL or1.8V ReceiverCPRI lossofsignal(LOS) status(8-bitmode only). LVCMOS 0 = signaldetected(perCPRI standard) 1 = signallost(perCPRI standard) See LOS DETECTION underFunctionalDescriptionformore details. 77 LOCKB O, LVTTL or1.8V ReceiverPLL lockstatus LVCMOS 0 = ReceiverPLL locked 1 = ReceiverPLL notlocked 79 CDET O, LVTTL or1.8V Comma Detect. LVCMOS 0 = no comma yetdetectedintheincomingserialstreamorreceiverPLL notlocked. 1 = thereceiverPLL islockedand a positiveornegativecomma bitsequence detected intheincomingbitstream.The serialtoparallelconverterisalignedtotheproper10-bit word boundarywhen comma alignmentisenabled(CALIGN_EN = 1). (1) Note:I=input O = output Internalpulldown = inputpinispulledlowby an internalresistor Internalpullup = inputpinis pulledhighby an internalresistor Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (1)(continued) Pin # Pin Name I/O,Type Description CONTROL PINS 82 PE [0] I,LVTTL or1.8V Transmitterde-emphasisconfiguration. 81 PE [1] LVCMOS InternalPullingbothpinslowenablesMDIO control,defaultisno de-emphasis. pulldown PE1 PE0 0 0 No de-emphasis 0 1 Low de-emphasis 1 0 Medium de-emphasis 1 1 Maximum de-emphasis 88 EQ [0] I,LVTTL or1.8V Receiveinputequalizationconfiguration. 89 EQ [1] LVCMOS InternalPullingbothpinslowenablesMDIO control,defaultisno receiveequalization. pulldown EQ1 EQ0 0 0 No receiveequalization 0 1 Low receiveequalization 1 0 Medium receiveequalization 1 1 Maximum receiveequalization 90 TXPWDNB I,LVTTL or1.8V Power down controlsignals.

91 RXPWDNB LVCMOS InternalTXPWDNB

pulldown 0 = Transmitterispowered down and DOUT ± pinsarehighimpedance. 1 = Transmitterispowered up. RXPWDNB 0 = Receiverispowered down and ROUT [9:0]as wellas LOS, LOCKB, CDET, RXCLK, and SYSCLK arehighimpedance. 1 = Receiverispowered up. 92 CALIGN_EN I,LVTTL or1.8V Comma alignmentenable. LVCMOS Internal0 = comma alignmentcircuitrydisabled.Receiverwillnotrealign10-bitdatabased on pulldown incomingcomma characters.CDET pinstillflagscomma detection. 1 = comma detectand alignmentcircuitryenabled.Receiveraligns10-bitdatato incomingcomma characterand flagscomma detectthroughCDET pin. 93 RXCLKMODE I,LVTTL or1.8V Receiverrecoveredclockmode LVCMOS Internal0 = Writemode. RXCLK pinisa recoveredclockoutput. pulldown (RXCLK = outputpin) 1 = Read mode. RXCLK pinisROUT [9:0]bus readinputstrobe. (RXCLK = inputpin) 80 VSEL I,LVTTL or1.8V Selectswhethersingle-endeddataand controlpinsare3.3VLVTTL or1.8VLVCMOS. LVCMOS Internal0 = 1.8VLVCMOS. TieVSEL togroundand power IOVDD at1.8V. pulldown 1 = 3.3VLVTTL. TieVSEL toIOVDD supplyand power IOVDD at3.3V. 94 OPMODE I,LVTTL or1.8V SelectsSerDes mode. LVCMOS Internal pulldown 0 = Base stationmode 1 = Reservedforfutureuse 95 RESETB I,LVTTL or1.8V Hardware SerDes reset.ResetsPLLs and MDIO registers. LVCMOS Internal pulldown 0 = Hardware SerDes reset 1 = Normal operation 96 SPMODE [0] I,LVTTL or1.8V Speed mode configuration.(OPMODE must be low) 97 SPMODE [1] LVCMOS InternalPullingbothpinslowenablesMDIO control. pulldown SPMODE [1] SPMODE [0] 0 0 Rate selectedviaMDIO 0 1 614.4Mbps ratemode 1 0 1228.8Mbps ratemode 1 1 2457.6Mbps ratemode 98 TENBMODE I,LVTTL or1.8V Enable10-bitmode LVCMOS, Internal The 8B/10B specificationisdefinedinIEEE 802.3-2000section36.2.2 pulldown 0 = Selects8-bitmode. Enablestheinternal8b/10bencoderand decoder. 1 = Selects10-bitmode. Bypasses internal8b/10bencoderand decoder.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 PIN DESCRIPTIONS (1)(continued) Pin # Pin Name I/O,Type Description 99 LOOP [0] I,LVTTL or1.8V Loop back configuration. 100 LOOP [1] LVCMOS, InternalPullingbothpinslowenablesMDIO control. pulldown Note:DuringSpecialline(remote)loopback mode, theoutputde-emphasiscontrolis disabled. LOOP [1] LOOP [0] 0 0 Normal mode — no loopback 0 1 Line(remote)loopback mode 1 0 Localloopback mode 1 1 Specialline(remote)loopback mode MDC/MDIO 30 MDC 3.3VLVTTL MDC/MDIO configurationbus. 31 MDIO Internalpullup on ProtocolperIEEE 802.2ae-2002MDC/MDIO Clause45.These pinsare3.3VLVTTL 37 ADD0 ADDR pins compatible,not1.2Vsignalcompatible.

36 ADD1

35 ADD2

34 ADD3

33 ADD4

IEEE 1149.1(JTAG) 45 TDI 3.3VLVTTL JTAG testbus forIEEE 1149.1and 1149.6support.

41 TDO Internalpullup on

44 TMS TDI,TMS, and

43 TCK TRSTB

46 TRSTB

83 RES1 I Reserved. 84 RES2 Tiewith5 KΩ resistortoground. POWER 9,15,20, AVDD18 I,Power 1.8Vanalogsupply. 32,38,47, 8,14,21, AVDD33 I,Power 3.3Vanalogsupply. 1,2,28, PVDD33 I,Power 3.3VPLL supply(minimizesupplynoiseto< 100 mV peak-to-peak). 50,51,76, IOVDD I,Power 1.8Vor3.3VparallelI/Obus and controlpinsupply. 87 See VSEL pindescriptionforadditionalinformation. GROUND 3,4,5,10, GND I,Ground Deviceground. 13,16,19, 24,25,26, 27,39,40, 48,49,63, 75,86 GROUND DAP 101 GND I,Ground Deviceground.Pad must be solderedand contectedtoGND planewitha minimum of8 thermalviastoachievespecifiedthermalperformance. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2)(3) SupplyVoltage(AVDD18 ) −0.3Vto+2.0V SupplyVoltage(PVDD ,IOVDD ) −0.3Vto+3.6V SupplyVoltage(AVDD33 ) −0.3Vto+3.6V LVCMOS InputVoltage −0.3Vto(IOVDD + 0.5V) LVCMOS OutputVoltage −0.3Vto(IOVDD + 0.5V) MDC/MDIO/ADD[0:4],VSEL InputVoltage −0.3Vto(AVDD33 + 0.5V) MDIO OutputVoltage −0.3Vto(AVDD33 + 0.5V) CML ReceiverInputVoltage −0.3Vto(AVDD + 0.3V) CML ReceiverOutputVoltage −0.3Vto(AVDD + 0.3V) JunctionTemperature +125°C StorageTemperature −65°C to+150°C Lead Temperature (Soldering,10–20 sec) 235 °C Lead-free+260°C flowisavailable Maximum Package Power Dissipationat25°C 100-pinHTQFP withExposed Pad 4.16W Deratingabove 25°C 41.6mW/ °C ThermalResistance,θJA (0airflow) 24.0°C/W ESD Rating CML RIN/DOUT Pins HBM, 1.5kΩ,100 pF >8 kV EIAJ,0Ω,200 pF >250V CDM >2 kV AllOtherPins HBM, 1.5kΩ,100 pF >7 kV EIAJ,0Ω,200 pF >250V CDM >2 kV (1) “AbsoluteMaximum Ratings”aretheratingsbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedeviceshouldbe operatedattheselimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Thisisthemaximum HTQFP-100 package power dissipationcapability.ForSCAN25100 power dissipation,see theinformationinthe ElectricalCharacteristicssection. Recommended OperatingConditions Min Typ Max Unit SupplyVoltage AV DD18 1.7 1.8 1.9 V AV DD33 ,PV DD33 3.135 3.3 3.465 V IOVDD (1.8VMode) 1.7 1.8 1.9 V IOVDD (3.3VMode) 3.135 3.3 3.465 V Temperature -40 25 85 °C Junctiontemperature 125 °C SupplyNoise(Peak-to-Peak) <100 mV

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Condition Min Typ (1) Max Units LVCMOS DC SPECIFICATIONS (1.8VI/O) VIH Highlevelinputvoltage 0.65VDD V VIL Low levelinputvoltage 0.35VDD V IIN InputCurrent VIN = 0V or1.9V −10 +50 µA VOH Highleveloutputvoltage IOH = −2 mA 1.2 V VOL Low leveloutputvoltage IOL = 2 mA 0.45 V IOZ Power Down OutputCurrent Power down −20 +20 µA C IO Input/OutputCapacitance Typical 2.8 pF LVCMOS DC SPECIFICATIONS (3.3VI/O) VIH Highlevelinputvoltage 2 V VIL Low levelinputvoltage 0.8 V IIN InputCurrent VIN = 0V or3.465V −10 +50 µA VOH Highleveloutputvoltage IOH = −2 mA 2.4 V VOL Low leveloutputvoltage IOL = 2 mA 0.4 V IOZ Power Down OutputCurrent Power down −20 +20 µA C IO Input/OutputCapacitance Typical 2.8 pF JTAG DC SPECIFICATIONS (3.3VI/O) VIH Highlevelinputvoltage 2 V VIL Low levelinputvoltage 0.8 V IIN InputCurrent VIN = 0V or3.465V −35 +35 µA VOH Highleveloutputvoltage IOH = −2 mA 2.4 V VOL Low leveloutputvoltage IOL = 2 mA 0.4 V C IO Input/OutputCapacitance Typical 2.8 pF MDIO/MDC/ADD0-4 DC SPECIFICATIONS VIH Highlevelinputvoltage 2.0 3.465 V VIL Low levelinputvoltage GND 0.8 V IIN InputCurrent VIN = 0V or3.465V -150 +150 µA VOH Highleveloutputvoltage IOH = −2 mA 2.4 V VOL Low leveloutputvoltage IOL = 2 mA 0.4 V IOZ Power Down OutputCurrent Power down −100 +100 µA C IO Input/OutputCapacitance Typical 2.8 pF POWER CONSUMPTION PD Max totalpower consumption 614.4Mbps ParallelI/Oat1.9V 920 1040 mW ParallelI/Oat3.465V 1040 1150 mW PRWS patternembedded in 1228.8Mbps hyperframe ParallelI/Oat1.9V 950 1100 mW ParallelI/Oat3.465V 1110 1250 mW Outputloading: 2457.6Mbps CML: AC-coupled ParallelI/Oat1.9V 1020 1200 mWCMOS: 50Ω transmissionline ParallelI/Oat3.465V 1230 1350 mW POWER CONSUMPTION (Powerdown) PPDN Powerdown Mode Rx and Tx Powerdown 25 40 mW (1) Typicalparametersaremeasured atnominalsupplylevelsand TA = 25°C. They areforreferencepurposesand arenotproduction- tested. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Condition Min Typ (1) Max Units TYPICAL POWER CONSUMPTION (By Supply) PDS PVDD33 2457.6Mbps operation 315 mW ParallelI/Oat3.3VAVDD33 175 mWPRWS patternembedded in IOVDD 255 mWhyperframe AVDD18 485 mW RECOMMENDED REFCLK INPUT SPECIFICATIONS VIDSREFCLK Differentialinputvoltage ± 100 mV P-P VICM Common mode voltage 0.05V 2.4V V fREF REFCLK frequency OPMODE = 0 (BTS SerDes Mode) 30 30.72 31.5 MHz dfREF REFCLK frequencyvariation Variationfromnominalfrequency −100 100 ppm tREF-DC REFCLK dutycycle Between 50% ofthedifferential 45 55 % voltageacrossREFCLKP and REFCLKN tREF-X REFCLK transitiontime Transitiontimebetween 20% and 300 pS 80% ofthedifferentialvoltage acrossREFCLKP and REFCLKN SYSCLK DC OUTPUT SPECIFICATIONS VOD DifferentialOutputVoltage R L = 100Ω ± 250 ± 330 ± 450 mV VOS OffsetVoltage 1.125 1.20 1.375 V IOS OutputShortCircuitCurrent Outputpairshortedtogetherand 35 mA tiedtoGND IOZ Power Down OutputCurrent Power down −30 +30 µA TRANSMITTER SERIAL TIMING SPECIFICATIONS VOD Outputdifferentialvoltageswing PE[1]=0,PE[0]=0 ± 550 ± 700 ± 800 mVp-p PE[1]=0,PE[0]=1 ± 630 mVp-p PE[1]=1,PE[0]=0 ± 500 mVp-p R DO Outputdifferentialresistance 80 100 120 Ω R O OutputReturnLoss Frequency= 1.229GHz -13.4 dB tR ,tF Serialdataoutputtransitiontime(2) Measured between 20% and 80% 80 100 130 ps (3) JITT-DJ Serialdataoutputdeterministic OutputCJPAT withBER of10−12 (5) 0.14 UIp-p jitter(4)(2) JITT-TJ Serialdataoutputtotaljitter OutputCJPAT patternwithBER of 0.279 UIp-p (4)(2) 10−12 (5) tLAT-ACC-T Transmitlatencyvariationatstart 614.4Mbps 36 ns up(6)(7)(2) 1.228Gbps 18 2.4576Gbps 9 tLAT-T Transmitlatency 614.4Mbps 310 ns (8)(7) 1.228Gbps 155 2.4576Gbps 80 tDO-LOCK Maximum locktime K28.5patternat2457.6Mbps 110 130 us (2) Limitsareensuredby designand characterizationoverprocess,supplyvoltage,and temperaturevariations. (3) Edge ratecharacterizationincludestheloadingeffectsof1.0uF AC-couplingcapacitorsand 4 inchesof100-Ohm differentialmicrostrip. (4) TransmitJittertestingmethodologyisdefinedinAppendix48B ofIEEE 802.2ae-2002.The SCAN25100 transmitoutputjitterisconstant forallvalidCPRI datarates.For614.4and 1228.8Mbps rates,thetransmitjitterissignificantlylessthanthespecifiedlimitsintermsof UI. (5) CJPAT isa stresspatterndefinedinIEEE 802.2ae-2002Appendix48A (6) TransmitorReceiveK28.5pattern.Assumes TXCLK isstableand togglesonlyafterallSerDes clocksbecome synchronous. (7) Transmitlatencyisfixedonce thelinkisestablishedand isensuredby theTserspecification. (8) Conditions:The TX PLL islocked,theTXCLK isstableand theTXCLK issynchronous.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Condition Min Typ (1) Max Units RECEIVER SERIAL TIMING SPECIFICATIONS VID Inputvoltage RINP -RINN ± 100 ± 1100 mVp-p VCMR Receivercommon mode voltage 0.9 V R R DifferentialInputTerminations 80 100 120 Ω RLR I InputReturnLoss (2) Frequency= 1.229GHz -20 -15 dB tLAT-R Receivelatency 614.4Mbps 280 ns (9)(10) 1.228Gbps 140 ns 2.4576Gbps 75 ns tLAT-ACC-R Receiverlatencyvariationatstart 614.4Mbps 36 ns up (6)(9)(2) 1.228Gbps 18 2.4576Gbps 9 JITR-TOL Totalinputjittertolerance(2) InputCJPAT withBER of10−12(5) 0.66 UIp-p FR-LOCK Receiverlockrange Inputdataratereferencetolocal −200 +200 ppm transmitdatarate. tR-LOCK Maximum locktime K28.5patternat2457.6Mbps 1 ms TRANSMITTER INPUT TIMING SPECIFICATIONS tS-T SetupTime DIN [9:0]validtoTXCLK risingor 0.5 ns fallingedge tH-T HoldTime TXCLK risingorfallingedge toDIN 0.5 ns [9:0]valid tDC Dutycycle TXCLK dutycycle 45 55 % fTXCLK TXCLK frequency 30 125 MHz RECEIVER OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1, 1228.8and 614.4Mbps only) tPDRX RXCLK PropagationDelay RXCLK risingorfallingedge to 2 4 6 ns ROUT [9:0]valid tDC Dutycycle RXCLK inputdutycycle 45 55 % fRXCLKR RXCLK inputfrequency RXCLK inputfrequency 30 62.5 MHz tR ,tF Outputdatatransitiontime ForROUT [0-9],LOCK, etc.pins. 0.35 ns Measured between 20% and 80% levels RECEIVER OUTPUT TIMING SPECIFICATIONS (WriteMode RXCLKMODE=0) tS-R SetupTime ROUT [9:0]validtoRXCLK risingor 0.9 1.5 ns fallingedge (11) tH-R HoldTime RXCLK risingorfallingedge to 0.9 1.5 ns ROUT [9:0]valid(11) tDC Dutycycle RXCLK dutycycle 45 55 % fRXCLK RXCLK frequency 30 125 MHz tR ,tF Outputdatatransitiontime ForROUT [0-9],LOCK, etc.pins. 0.35 ns Measured between 20% and 80% levels CDET OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1, 1228.8and 614.4Mbps only) tPDCD CDET PropagationDelay RXCLK risingorfallingedge to 2 4 6 ns CDET CDET OUTPUT TIMING SPECIFICATIONS (WriteMode RXCLKMODE=0) (12) tS-C SetupTime CDET validtoRXCLK risingor 1 ns fallingedge (9) Receivelatencyisfixedonce thelinkisestablishedand isensuredby theTdes specification. (10)Conditions:The RX PLL islockedtotheincomingdataand theSCAN25100 isinWRITE mode. (11)ReceiveroutputtimingspecificationsforTS-R and TH-R aretestedattheCPRI rateof2.4576Gbps. (12)CDET nominalvaliddurationisdeterminedby theCPRI datarate.CDET timingissimilartotheROUT[0:9]timing. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Condition Min Typ (1) Max Units tH-C HoldTime RXCLK risingorfallingedge to 1.1 ns CDET valid SYSCLK LVDS OUTPUT TIMING SPECIFICATIONS tSYSCLKNDC Dutycycle 40 60 % JITSYSCLK Cycletocyclejitter (13) 40 65 ps p-p tR ,tF Outputtransitiontime Between 20% and 80% levels 0.1 0.3 ns (13) MDC/MDIO TIMING SPECIFICATIONS (Clause45) fMDC MDC Frequency 0 2.5 MHz tS-MDIO SetupTime MDIO (input)validtoMDC rising 10 ns clock tH-MDIO HoldTime MDC risingedge toMDIO (input) 10 ns invalid tD-MDIO DelayTime MDIO (output)delayfromMDC 0 300 ns risingedge tX-MDIO TransitionTime Measured atMDIO when used as 1 ns output,CL = 470 pF MINIMUM PULSE WIDTH, Hardware Reset (14) tTX-RST TransmiterReset TXPWDNB = 0 1 us tRX-RST ReceiverReset RXPWDNB = 0 1 us tRST SerDes Reset RESETB = 0 1 us JTAG TIMING SPECIFICATIONS fJTAG JTAG TCK Frequency R L= 1000Ω,C L = 15 pF 25 MHz tR-J TDO datatransitiontime(20% to 2 ns tF-J 80%) tS-TDI SetupTime TDI toTCK HighorLow 2 ns tH-TDI HoldTime TDI toTCK HighorLow 2 ns tS-TMS SetupTime TMS toTCK Highor 2 ns Low tH-TMS HoldTime TMS toTCK HighorLow 2 ns tW-TCK TCK PulseWidth 10 ns tW-TRST TRSTB PulseWidth 2.5 ns tREC RecoveryTime TRSTB toTCK 14 ns DELAY CALIBRATION MEASUREMENT (DCM) (15)(16)(17) T14 T14 DelayAccuracy Receiveand TransmitPLLs locked ± 800 ps tovalidhyperframedata.Toffset ToffsetDelayAccuracy ± 800 ps Tser SerializerDelayAccuracy ± 1200 ps Tdes DeserializerDelayAccuracy ± 1200 ps Tin-out Tin-outDelayAccuracy ± 1200 ps Tout-in Tout-inDelayAccuracy ± 1200 ps (13)Limitsareensuredby designand characterizationoverprocess,supplyvoltage,and temperaturevariations. (14)Limitsareensuredby design (15)Limitsareensuredby designand characterizationoverprocess,supplyvoltage,and temperaturevariations. (16)SerialsideDCM readingsarereferencedtothefirstbitoftheK28.5pattern{1100000101 001111 1010}.ParallelsideDCM readings arereferencedtotheTXCLK orRXCLK edge (notthedataedge)thatregisterstheK characteras an inputoroutput. (17)DCM readingshave been validatedwhen theRXCLK pinon theSCAN25100 isused as an outputin"WRITE "mode (RXCLKMODE = 0)and IOVDD = 3.3V.

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ROUT[0:9] CDET tS-R tS-RtH-R tH-R tS-C tS-CtH-C tH-C RXCLK OUTPUT tPDRX tPDRX tPDCDtPDCD ROUT[0:9] INPUT CDET RXCLK SCAN25100 www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 AC Timing Diagrams READ MODE WRITE MODE Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN25100

after a link resynchronization event (reset, power down, loss of lock, comma (re)align- ment, etc.) This state flushes and resets internal FIFOsWait until all clocks are stable and synchronous. Hold TxCLK and RxCLK high or low Toggle TxCLK (and RxCLK) to write (and read) data at parallel bus On-chip POR circuit maintains internal reset for = 150 ms based on an internal counter monitoring the REFCLK input. SCAN25100 SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com FunctionalDescription POWER UP AND LINK SYNCHRONIZATION An internalpower on reset(POR) circuitdisablesthe transmitteroutputand setsreceiverROUT[9:0],LOS, LOCKB, and CDET in statichigh stateforapproximately150 ms (150ms is based on an internalcounter monitoringthe30.72MHz RefCLK) toallowexternalclocksourcestostabilize.A specialpower up sequence is notrequired,buta monotonicpower ramp willensuretheSCAN25100 attainstheproperinitialstatewhen stable supplylevelswithinthe recommended range are achieved. Once the transmitterpowers up and TXCLK becomes active,thetransmitterstartssendingvaliddata.Once thereceiverispowered up and REFCLK exists, the receiveris ready to receivedata.When comma alignmentis enabled (CALIGN_EN = 1),the receiver searchesfora validcomma inthe incomingstream.When a comma isdetected,the receiverperformscode group(comma) alignmentand presentsdataon ROUT. To ensure the parallelbus FIFO read/writepointerdistanceis halfof the totalFIFO depth,the following procedureshouldbe followed(e.g.,afterresetorcomma (re)alignment): 1. Power up SCAN25100 whileholdingTXCLK and RXCLK (inreadmode) inputclocksstaticlow orhigh.The SCAN25100 willhold both transmitterand receiverFIFO’s in resetuntilthe TXCLK and RXCLK start toggling. 2. Waitforallclocksourcestobecome synchronousand stablebased on theCPRI timingspecification. 3. ToggleTXCLK and RXCLK inputclockstolatchdataintoand outoftheparallelDIN/ROUT buses. 4. Ifat any timethe clockrequiresa resynchronization,such as switching30.72 MHz system clock.Holding TXCLK and RXCLK (inreadmode) statichighorlowresetstheSCAN25100 internalFIFO pointers. Figure2. Power Up StateDiagram

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 POWER DOWN When thetransmitterispowered down by pullingpinTXPWDNB down, DOUT isputintoa highimpedance state. When thereceiverispowered down by pullingRXPWDNB down, ROUT[9:0],LOS, LOCKB, CDET, RXCLK, and SYSCLK are high impedance.The MDC/MDIO signalpinsare not powered down when TXPWDNB and/or RXPWDNB arelow. ResettingtheSCAN25100 The SCAN25100 has a richsetofhardwareand softwareresetfunctions.When performinghardwarepinresets, TXPWDNB and RXPWDNB pinsortheRESETB pinmust be heldlowforatleast1 us. Table1.Reset Conditions Reset Type What isReset Initialpower up Allinternalstatesand registersheldatresetfor150 ms afterpower on.This resetperiodisbased on an internalcountermonitoringthe30.72MHz REFCLK inputsignal. TXPWDNB and RXPWDNB lowfor≥ 1 us Allinternalstatesand registersarereset RESETB lowfor≥ 1 us Logicreset(includingMDIO) Write“0”toMDIO RESETB register Logicreset(excludingMDIO) SPMODE change Logicreset(excludingMDIO) TXCLK missingfor≥ 7 cycles TransmitFIFO flushed,transmitread/writepointersreset RXCLK missingfor≥ 7 cycles(Read Mode) ReceiveFIFO flushed,receiveread/writepointersreset TRSTB (IEEE1149.1interface) OnlyIEEE 1149.1statemachine isreset DeterministicFIFO Delay atStartUp To ensure synchronous operation,REFCLK, TXCLK, and RXCLK should be stableand the receiver synchronizedbeforedataissentintooroutoftheparallelbuses. SCAN25100 CLOCK DOMAINS Most SerDes have onlytwo clocks:a referenceclock(thatalsoactsas a transmitclock)and a receiverecovered clock.The sharingof clocksin these architectures,however, can cause loss of lock issuesduringRE synchronization.To provideseamless base stationsynchronization,the SCAN25100 featuresindependent transmitand receivePLLs and fourclocksignals. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SCAN25100

ROUT [0:9] PLL Parallel to Serial De- Emphasis DOUT r REFCLK (30.72 MHz) MDIO Rate Select etc. Pin Control Pattern Generator RIN r DIN [0:9] TXCLK RXCLK LOS SYSCLK (30.72 MHz) 8b/10b Encoder Pattern Verifier JTAG Serial to Parrallel CDR 8b/10b Decoder Output FIFO Input FIFO Equalizer Control Local Loop Back Special Line Loop Back Line Loop Back Special Local Loop Back Precision Delay Calibration Measurement Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay Calibration (Enable, Measurement) REFCLK CDR Clock TSER TDES SCAN25100 SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Figure3. SCAN25100 Clock Domains The SCAN25100 has additionalclockingfeaturesbeneficialforRE applications.The chip’s receiverPLL circuitry isindependentofREFCLK and has an integratedoscillator,allowingthereceivertolocktotheincomingREC streamand synchronizetheRE withoutlosinglockwhen REFCLK switchesfromlocaltorecoveredclock. Once theRE issynchronizedtotheREC, allclocksare synchronousand thefourclockdomains become one clockdomain.HoldingTXCLK (andRXCLK ifinreadmode) statichighorstaticlow untiltheRE issynchronized totheREC ensurestheon-chipFIFOs areflushedand reset.Once thesystem issynchronous,theSCAN25100 chipdelaysareconstantand theseand othersystemdelayscan be measured usingDCM. SYSCLK AND RXCLK RECOVERED CLOCKS The SCAN25100 providestwo recovered clocks,RXCLK (in writemode) and SYSCLK, with different characteristics: Table2.Recovered Clock TruthTable Pin Type BeforeLock AfterLock Phase vs.Incoming Serial Stream RXCLK (writemode) 1.8VCMOS or High-Z Digitalrecoveredclock Can be measured viaDCM LVTTL synchronoustooutputdata SYSCLK LVDS 30.72MHz ± 5% 30.72MHz analogrecovered Not Specified (internaloscillator) clockfromdeserializerPLL

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100 Ohm Media

100: LVDS Interface REFCLKN REFCLKP SCAN25100 50:(2x) LVPECL Interface SCAN25100 REFCLKN REFCLKP VT Note: AC coupling is optional for either interface SCAN25100 www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 SYSCLK can be used tosynchronizeremoteradioheads sinceitprovidesa local30.72MHz internalclockwhich isgracefullytransitionedtotherecoveredclock.RXCLK isdigitaland synchronoustorecoveredoutputdataand itsphase versusthe incomingserialstream can be preciselymeasured usingDCM. Eitheror both recovered clocksmay be used dependingon applicationrequirements. REFERENCE CLOCK The differentialREFCLKP and REFCLKN inputimpedance acceptsLVDS or LVPECL levelsignals.These pins shouldbe terminatedwithappropriatesurfacemount resistor(s)placedclosetotheREFCLKP and REFCLKN inputs. Figure4. SCAN25100 REFCLK Termination Table3.ReferenceClock InputRequirements REFCLK Mode Clock Rate Duty Cycle Accuracy Jitter(Typ) Jitter(Max) BTS SerDes Mode (OPMODE = 0) 30.72MHz 40% /60% ±100 ppm 40 ps p-p 140 ps p-p SPMODE[1:0] SPEED RATE SELECTION The SCAN25100 operatesin from a constant30.72 MHz REFCLK clockand performsnecessary clock multiplicationinternallyto supportCPRI base stationdata rates.The speed rateisprogrammable usingthe SPMODE[1:0] pinsorthroughMDIO when SPMODE[1:0] arepulledlow.MDIO defaultspeed is1228.8Mbps on initialpower up orreset. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Table4. Speed Rate ConfigurationTruthTable OPMODE SPMODE[1] SPMODE[0] REFCLK TXCLK/RXCLK SerialRate 0 (BTS Mode) 0 0 30.72MHz Reserved Reserved 0 (BTS Mode) 0 1 30.72MHz 30.72MHz 614.4Mbps 0 (BTS Mode) 1 0 30.72MHz 61.44MHz 1228.8Mbps 0 (BTS Mode) 1 1 30.72MHz 122.88MHz 2457.6Mbps VSEL PIN 1.8CMOS/3.3LVTTL SELECT The parallelinputbus, outputbus, and controlpinsare configurableforeither1.8V CMOS or 3.3V LVTTL compliance.To ensurereliabledeviceoperation,theVSEL and IOVDD must be configuredproperly: Table5.VSEL Pin ControlOptions Compliance VSEL ControlPin IOVDD Supply Pins 1.8VCMOS Tietoground 1.8V 3.3VLVCMOS TietoIOVDD supply(mustpower up withIOVDD) 3.3V TRANSMIT DATA DIN[9:0]TransmitParallelInputData TransmitinputdatapinsDIN[9:0]are latchedon bothrisingand fallingedges ofTXCLK. By usingbothTXCLK edges,theclockspeed ishalved,which reduceshighspeed designand EMI issues.The transmitterserializes and sends thevalidDx.y or Kx.ycode.Ifan invalidKx.ycode isprovidedatDIN[9:0],thetransmittersends a K30.7pattern. Table6.TransmitterParallelInputBus Mapping Tx Input 10-bitMode (TENBMODE = 1) 8-bitMode (TENBMODE = 0) DIN[0] Coded Data Bit Data Bit0 (A,lsb) DIN[1] Coded Data Bit Data Bit1 (B) DIN[2] Coded Data Bit Data Bit2 (C) DIN[3] Coded Data Bit Data Bit3 (D) DIN[4] Coded Data Bit Data Bit4 (E) DIN[5] Coded Data Bit Data Bit5 (F) DIN[6] Coded Data Bit Data Bit6 (G) DIN[7] Coded Data Bit Data Bit7 (H,msb) DIN[8] Coded Data Bit D/K Select(Z) DIN[9] Coded Data Bit Pulledlowthrougha 5 kΩ resistor TransmitSerialData Output DOUT isa differentialcurrentmode logic(CML) driver.Both DOUTP and DOUTN are terminatedwithon-chip resistorstoan internalbiasvoltage.The valuesoftheinternalterminationresistorsarecontrolledto50Ω ±20%. TransmitterDe-Emphasis The transmitterserialoutputprovides3 steps of de-emphasis to compensate forbackplanesand cable interconnects.PullingbothPE[1:0]pinslowenablesMDIO controlofde-emphasis. Table7.TransmitDe-Emphasis ControlSettings PE[1] PE[0] Descriptions 0 0 De-emphasisdisabled. 0 1 De-emphasisenabledlow(approximately1 dB).

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50 Ohm (2x)

100 Ohm MediaVOS = 1.45V Note: AC coupling is optional between SCAN25100's 0.1 PF RINN RINP 0.1 PF DOUTN DOUTP SCAN25100 www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Table7.TransmitDe-Emphasis ControlSettings(continued) PE[1] PE[0] Descriptions 1 0 De-emphasisenabledmedium (approximately3 dB). 1 1 De-emphasisenabledhigh(approximately6 dB). TransmitterReset Options Table8.TransmitterOutput TruthTable TXPWDNB Tx PLL DIN[9:0] Tx FIFO DOUTP/DOUTN

0 X x DOUTP and DOUTN pulledto

1 MissingREFCLK x Undefined

1 MissingTXCLK x Logic1

1 Not Locked x DOUTP and DOUTN pulledto

1 Locked ValidDx.yorKx.y Normal SerialData 1 Locked InvalidKx.y K30.7(8-bitMode) orSerialData (10-bitMode) 1 Locked x Underflow/Overflow K30.7(8-bitMode)

1 Not Locked x Underflow/Overflow 10'd0(10-bitMode)

The receiveinput(RIN)pinsare terminatedwithon-chip50Ω ±20% resistorsto an internalbiasvoltage.This biasvoltageissettoapproximately1.45voltsabove GND. NormallyCML signalsareAC-coupledand thisbias voltagesetsthe inputcommon mode forthe RIN inputs.DC couplingbetween two SCAN25100 devicesis acceptablewhen requiredintheapplication.ForotherCML outputsAC couplingisrequired. Figure5. SCAN25100 SerialInputConnection Receive Equalization The receiverfront-endprovides3 stepsofequalizationfiltertocompensate forISIdeterministicjitterfromlossy backplanesand cables.PullingbothEQ[1:0]pinslowenablesMDIO controlofequalization. Table9.ReceiverEqualizerControlSettings EQ[1] EQ[0] Descriptions 0 0 Equalizationdisabled. 0 1 Equalization(approximately2 dB). Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Table9.ReceiverEqualizerControlSettings(continued) EQ[1] EQ[0] Descriptions 1 0 Equalization(approximately4 dB). 1 1 Equalization(approximately8 dB). Receive Output Bus Receive outputdata ROUT[9:0] isclockedon both risingand fallingedges of RXCLK. By usingboth RXCLK edges,theclockspeed ishalved,whichreducesEMI issues.The receiveroutputbus can be configuredineither readorwritemode. Table10.ReceiverParallelOutput Bus Mapping Rx Output 10-bitMode (TENBMODE = 1) 8-bitMode (TENBMODE = 0) ROUT[0] Coded Data Bit Data Bit0 (A,lsb) ROUT[1] Coded Data Bit Data Bit1 (B) ROUT[2] Coded Data Bit Data Bit2 (C) ROUT[3] Coded Data Bit Data Bit3 (D) ROUT[4] Coded Data Bit Data Bit4 (E) ROUT[5] Coded Data Bit Data Bit5 (F) ROUT[6] Coded Data Bit Data Bit6 (G) ROUT[7] Coded Data Bit Data Bit7 (H,msb) ROUT[8] Coded Data Bit D/K Flag(Z) ROUT[9] Coded Data Bit LineCode ErrorFlag Table11. ReceiverOutput TruthTable(10-bitMode, TENBMODE = 1) RXPWDNB Rx PLL RXCLK SYSCLK ROUT[9:0] 0 x High-Z High-Z High-Z

1 MissingREFCLK & in10B High-Z Undefined Undefined

1 Not Locked Based on REFCLK running 30.72MHz based on 1111111111 atDDR Rate REFCLK 1 Locked RecoveredClock 30.72MHz based on RXCLK Deserialized10-bitWord WRITE MODE (RXCLKMODE = 0) In writemode, RXCLK is the recoveredclockoutput.The pins ROUT[9:0],CDET, LOCKB, and LOS are synchronoustoRXCLK. READ MODE (RXCLKMODE = 1) Inreadmode, RXCLK isan inputand thepinsROUT[9:0],CDET, LOCKB, and LOS arelatchedby theRXCLK inputstrobe.Note thatforreadmode, RXCLK must be synchronoustotheincomingserialdatastreamtoavoid receiverFIFO over-and underflow.Read mode isrecommended for1228.8and 614.4Mbps ratesonly.

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SysCLK 30.72 MHz (BTS Mode)

30.72 MHz (BTS Mode)

www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Figure6. WriteMode and Read Mode Diagram SYSCLK AND RE REMOTE RADIO HEAD SYNCHRONIZATION The SCAN25100 has independenttransmitand receivePLLs as wellas an internal~30.72 MHz oscillatorfor seamless RE synchronization.Once the SCAN25100 locksto incomingCPRI data,SysCLK becomes phase lockedtotherecoveredclock,automaticallysynchronizingtheRE totheREC. Thisphase locktransitionoccurs gracefullythroughanalogcircuitryto allowdownstream components to trackthe slightfrequencychange from externalclockto recoveredclock.DuringRE synchronization,TxCLK (and RxCLK ifinread mode) shouldbe heldstatichighorlowtopreventFIFO over-orunder-flow Unlikemost SerDes, the SCAN25100 deserializerdoes not depend on RefCLK . RefCLK can thereforebe switchedfroma localclocksource(crystaloscillator)totherecoveredclockwithoutthedeserializerlosinglock. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:SCAN25100

ROUT [0:9] RXCLK SCAN25100 JITTER CLEANER MDIO DOUT RIN VCXO Optional Optional

30.72 MHzREFCLK

XTAL OSC ~ 30.72 MHz (Crystal Osc) Deserializer Locks2 SYSCLK = REC Recovered Clock OUTPUT FIFO DIN [0:9] INPUT FIFO TXCLK CDR PLL OPTO MODULE To/From BTS IN/OUT OUT IN IN XO

30.72 MHz

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Figure7. Radio Equipment (RE)Clock Syncronization Inmulti-hopapplications,usinga jittercleanerbetween SysCLK and RefCLK isrecommended toattenuateany accumulatedjitter(< 5 MHz). RECEIVER PLL LOCK DETECTION The LOCKB pinindicatesthelockstatusofthereceivePLL. When assertedhigh,thereceivePLL isnotlocked totheincomingserialstream.When LOCKB islow,thereceivePLL islockedtotheincomingserialstream.Line code violations(LCVs)may ormay notexistwhen thePLL islocked. 8B/10B DECODING AND CODE GROUP ALIGNMENT IN 8-BITMODE charactersK28.1,K28.5,and K28.7 each containa comma bitsequence.When comma alignmentisenabled (CALIGN_EN = 1),thereceiverperformscode groupalignmentwhen encounteringa comma. The CALIGN_EN pinallowstheupperlayersystemtocontrolwhen alignmentand realignmentoccurs. COMMA DETECT (CDET) OPERATION When a K character(K28.1,K28.5,orK28.7)isdetectedwithcomma alignmentenabled(CALIGN_EN = 1),the receiverperformscode group alignment,i.e.thereceiveralignsROUT[9:0] datatotheproperword boundary. When thecomma isdetected,CDET remainshighforone 8b/10bword output(RXCLK period/2).When comma alignmentisdisabled(CALIGN_EN = 0),commas arestilldetectedand flaggedatpinCDET, but(re)alignmentis notperformed.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 LOS DETECTION LOS issettoHIGH duringreceiverpower up,duringhardwarereset(viaRESETB pin),or duringsoftware(via RESETB MDIO register)reset.LOS requiresone K28.5 characterand validlinecodingfor1 hyperframeinorder togo fromHIGH toLOW. Afterinitialization,theLOS isseton theconditionshown inthetablebelow.Also,when thedeserializerloseslock,LOS isnot automaticallysethighsincethedeserializercontinuestocountLCV ’s in ordertodetermineLOS statusaccordingtotheCPRI standard. Table12.LOS Set Conditions OPMODE Condition LOS 0 (BTS Mode) 16 ormore linecode violationsina CPRI hyperframe 1 The LOS mechanism affectstheROUT[9:0]and RXCLK outputsofthedeviceunder8-bitmode. Upon power up, theROUT[9:0]and RXCLK pinswillbe static.Once LOS islow,thedevicewillsend dataon theROUT[9:0]and RXCLK pins.AfterLOS ishigh,theoutputwillcontinuetosend datafor2-3 hyperframes.Ifthereare no line code violationsduringthenexthyperframe,theLOS signalgoes low and resumes normaloperation.Ifthereare linecode violationsafterthenext2-3 hyperframes,theoutputswillbe tri-statedand thedeviceentersa reset state. The LOS functionisdisabledin10-bitmode. The LOS defaultshighin10-bitmode. The LOS signalisresettolow(signaldetected)underthefollowingconditions: Table13.LOS Reset Conditions OPMODE Condition LOS 0 (BTS Mode) No LCVs occurwithina CPRI hyperframe 0 LOF (LOSS OF FRAME) DETECTION LOF counterisprovidedthroughan LOF MDIO statusregisterper CPRI Specification.The LOF functionis disabledin 10-bitmode. Under 8-bitmode, LOF willpreventthe SCAN25100 DCM scheme from activating. Delaycalibrationmeasurement can onlybe performedwhen LOF islow. TEST MODES Loop Back Modes The SCAN25100 supportsmultipleloopback modes fortestingdevice,link,and system operation.The lineloop back mode enablesthe user to check the integrityof the serialdata transmissionpaths.The localloopback verifiesoperationofthelocalboard.When switchingbetween normalmode and loopbackmodes, thereceiver must synchronizetothenew datastream. Loopback mode can be controlledthroughthe LOOP[1:0] pinsor viaMDIO. PullingLOOP[1:0] low enables MDIO controlofloopbackfunctions. Table14.Loopback ControlBitSettings LOOP[1] LOOP[0] Loop Back Mode 0 0 Normal mode — no loopback (enablesoftwareprogrammode) 0 1 Line(remote)loopback mode 1 0 Localloopback mode 1 1 Specialline(remote)loopback Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com At-Speed Built-InSelf-Test(BIST) The SCAN25100 featuresat-speedbuilt-inself-test(BIST)tosupportat-speedtestingduringbothmanufacturing as wellas fielddiagnosis.SeveraltestpatternsaresupportedincludingCJPAT lane0 and PRWS 10. BIST activationand statusareaccessedthroughtheSerialControlInterface(MDIO).Multipleregistersareused forthecontrol,patternselection,and customizationoftheat-speedBIST function.The BIST testresultsarealso reportedin BIST statusMDIO registers.One-bitBIST_ DETECTED and BIST_PASS statusregistersare providedtoindicateBIST startand pass/fail.A 10-bitcounterisused tostorethenumber oferrorsdetected.See MDIO registerlistand programming descriptionformore informationaboutat-speedBIST.BIST isdisabledin LineorSpecialLineloopbackmodes. IEEE 1149.1(JTAG) and 1149.6Operation The SCAN25100 supportsa fullycompliantIEEE 1149.1interface.The TestAccess Port(TAP) providesaccess toboundaryscan cellsatsingle-endedpinsforinterconnecttesting.The TAP alsoprovidesaccesstotheIEEE 1149.6testfeaturesfordifferentialpins.Refertothe(BoundarySCAN DescriptionLanguage (BSDL) filelocated on TI'swebsiteforthedetailsoftheIEEE1149.1and 1149.6implementation. JTAG BIST and Enhanced BIST mode The SCAN25100 ’s at-speedBIST patterngenerationand verificationfeatureisnormallyaccessedviatheMDIO programming interface,however,theBIST can alsobe accessed throughtheJTAG bus.Access totheJTAG BIST command requiresthe SCAN25100 be run inlocalloopbackBIST mode whileRXCLK and ROUT[9:0] outputsareheldinTri-State.Under thismode, thedevicerequirestheREFCLKP/N inputat30.72MHz and runs PRWS10 patternat2.4576Gbps. InadditiontothisJTAG BIST,SCAN25100 can be re-programmedtooperateinnormalmode transceiverlink mode, localloopbackmodes, allvalidspeed modes, allvalidde-emphasismodes, and allvalidequalization modes. To activatethisadvanced feature,a BSAMPLE instructionisexecuted.Then selectdata shiftregister and shiftintheregisterofthisorder:{PE[1],PE[0],EQ[0],EQ[1],SPMODE[0], SPMODE[1], LOCAL_EN} On the TDI input,thegeneratorwillshiftina patternthatstartswithLOCAL_EN and ends withPE[1].For example,to setthedeviceinto1.2288Gbps withmax EQ, max PE, and normalmode, shiftfromlefttoright0,1,0,1,1,1, and 1. SPMODE[1:0], PE[1:0],and EQ[1:0]followthe definitionsin the datasheetexceptthatMDIO willnot overridetheseparameters.The devicedefaultmode when SPMODE[1:0] = 2’b00 is1.2288 Gbps. EQ[1:0]= 2’b00 and PE[1:0]= 2’b00 disableequalizationand de-emphasis.Once theproperdatahas been shiftedintothe BSAMPLE dataregister,executingtheJTAG BIST command placesthedeviceintotheBIST mode. TI recommends JTAG BIST run forat least300ms to ensure BIST has been completed.Once 300ms has passed,the BIST resultcan be read throughthe data shiftregister.The outputismapped as follows:{BIST START, BIST COMPLETE, and BIST ERROR}. BIST START isshiftedoutfirstwithBIST_ERROR last.Ifthe testhas been completedand passed,theshiftedresultswillbe 0,1,and 1.IftheBIST_START is0,thereceiver can notdetecttheBIST signal.IfBIST_COMPLETE is0,BIST runtimeisnotlongenough.IftheBIST_ERROR goes 1,atleastone biterrorhas occurred. Instructioncodes and devicepinoutaredocumented intheSCAN25100 BSDL file. PrecisionDelay CalibrationMeasurement (DCM) The SCAN25100 DCM circuitrydeliversCPRI linkand measurements,enablingthenextgenerationdistributed multi-hopbase stationarchitecturesas wellas advanced diversity,beam forming,and MIMO antennasystems. The DCM preciselymeasures absoluteT14 and Toffsetdelaysto betterthan ± 800 ps and can trackdelay changes (infiberopticsforexample)witha resolutionof100’s ofpicoseconds.Measurements areaccessedvia theMDIO interfaceas oftenas every5 ms withoutinterruptingCPRI linkoperation.The SCAN25100 notonly reportsaccurateCPRI linkand chipdelays(chiplatencyisdeterministic),butalsoenablesmeasurement ofintra- module RE timingsuch as TBdelays.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 MDIO SerialControlInterface The MDIO serialcontrolinterfaceallows communication between a stationmanagement controllerand SCAN25100 devices.MDIO and MDC pinsare 3.3V LVTTL compliant,not 1.2V compatiable.Itissoftware compatiblewiththestationmanagement bus definedinIEEE 802.3ae-2002.The serialcontrolinterfaceconsists oftwo pins,thedataclockMDC and bidirectionaldataMDIO. MDC has a maximum clockrateof2.5MHz and no minimum limit.The MDIO isbidirectionaland can be sharedby up to32 physicaldevices. The MDIO pinrequiresa pull-upresistorwhich,duringIDLE and turnaround,willpullMDIO high.The parallel equivalenceoftheMDIO when sharedwithotherdevicesshouldnotbe lessthan1.5kΩ.Note thatwithmany devicesinparallel,theinternalpull-upresistorsadd inparallel.Signalqualityon thenetshouldprovideincident wave switching.Itmay be desirabletocontroltheedge rateofMDC and MDIO from thestationmanagement controllertooptimizesignalqualitydependingupon thetracenetand any resultingstublengths. InordertoinitializetheMDIO interface,thestationmanagement sends a sequence of32 contiguouslogicones on MDIO withMDC clocking.Thispreamblemay be generatedeitherby drivingMDIO highfor32 consecutive MDC clockcycles,or by simplyallowingthe MDIO pull-upresistorto pullthe MDIO highfor32 MDC clock cycles.A preambleisrequiredforeveryoperation(64-bitframes,do notsuppresspreambles). MDC isan a periodicsignal.Itshighorlow durationis160 ns minimum and has no maximum limit.Itsperiodis 400 ns minimum. MDC isnot requiredto maintaina constantphase relationshipwithTXCLK, SYSCLK, and REFCLK. The followingtableshows themanagement framestructureinaccordingtoIEEE 802.3ae. Table15.802.3aeMDIO Bus Protocol Mgmt Bus Protocol <Preamble><Start><OpCode ><PHY addr><dev addr><turnaround><data><idle> Read-Increment-Address <1… 1><00><10><PPPPP ><EEEEE ><Z0><DDDD DDDD DDDD DDDD ><idle> <1… 1> isa sequence of32 contiguousones and isused as preambleforsynchronizationpurposes. <PPPPP > isthePHY addressofthedevice,definedby thelogicstatesofADD[4:0].The MSB bitisthefirstbit transmittedorreceived.The PHY addressisreadatpower-uporaftera RESET event. <EEEEE > isthedevice(register)address.The MSB bitisthefirstbittransmittedorreceived. <AAAA AAAA AAAA AAAA > isthe16-bitaddressfieldoftheregistertobe accessed.The firstbittransmittedor receivedisbit15. <DDDD DDDD DDDD DDDD > isthe 16-bitdata field.Itisthe data to be writtenintothe SCAN25100 when performinga Writeoperation.Duringthe Read or Read-Increment-Addressoperation,itisthe read-backdata fromtheSCAN25100. The firstbittransmittedorreceivedisbit15. MDIO OPERATION The MDIO interfaceisactivewhen theSCAN25100 ispowered up,REFCLK ispresent,and theSCAN25100 not beingresetthroughtheRESETB pin.The MDIO bus returnsthefollowingdata:

CorrectPHY ADD, CorrectDEV ADD — expectedcontent
IncorrectPHY ADD, CorrectDEV ADD — FFFF ’h
CorrectPHY ADD, IncorrectDEV ADD — 0000’h
RESETB = Low — FFFF ’h The Startcode isindicatedby a <01> pattern.ThisassurestheMDIO linetransitionsfrom thedefaultidleline state. Turnaroundisdefinedas an idlebittimeinsertedbetween theRegisterAddressfieldand theData field.To avoid contentionduringa read transaction,no deviceshallactivelydrivethe MDIO signalduringthe firstbitof the turnaround.The addressedSCAN25100 drivesthe MDIO witha zero forthe second bitifthe turnaroundand followsthiswith the requireddata.Figure8 shows the timingrelationshipbetween MDC and MDIO as driven/receivedby theStationand theSCAN25100 fora typicalreadregisteraccess. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:SCAN25100

(Write) (NSID = 0x1E) Device Address ADD0 1032 1's Preamble z0 1 0 P P P P P E E E E E 0 D D D D D D D D D D D D D D D D ADD1 ADD2 ADD3 ADD4 ... z MDC MDIO Station MDIO SCAN25100 z z IdleRegister AddressTAStart Opcode (Address) (NSID = 0x1E) Device Address ADD0 1032 1's Preamble z0 0 0 P P P P P E E E E E 0 A A A A A A A A A A A A A A A A ADD1 ADD2 ADD3 ADD4 ... zMDIO Register Address 0-31MDIO Address 0-31 MDIO Address 0-31 MDIO Register Address 0-31 MDC MDIO Station MDIO SCAN25100 z z z IdleRegister DataTAStart Opcode (Read-Inc) (NSID = 0x1E) Device Address ADD0 z032 1's Preamble z0 0 1 P P P P P E E E E E 0 D D D D D D D D D D D D D D D D ADD1 ADD2 ADD3 ADD4 z ... MDC MDIO Station MDIO SCAN25100 z z IdleRegister AddressTAStart Opcode (Address) (NSID = 0x1E) Device Address ADD0 1032 1's Preamble z0 0 0 P P P P P E E E E E 0 A A A A A A A A A A A A A A A A ADD1 ADD2 ADD3 ADD4 ... zMDIO Register Address 0-31MDIO Address 0-31 MDIO Address 0-31 MDIO Register Address 0-31 SCAN25100 SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Figure8. TypicalMDIO/MDC Read Operation A normalwriteoperationuses the<01>.The dataislatchedintheSCAN25100 on each edge oftheMDC clock. MDIO issourcedfromthestationsideoftheMDIO controlinterface. Figure9. TypicalMDIO/MDC WriteOperation

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 RegisterDescription The SCAN25100 implementsthedeviceID of30 (0x1E.)Otherregistersdefinedby 802.3ae-2002may notbe implementedinSCAN25100. The SCAN25100 has a richMDIO registersettoallowthechiptobe controlledand monitoredthroughsoftware.Certainfunctionssuch as BIST and delaycalibrationare onlyaccessiblethrough MDIO. The typeofregistersused inSCAN25100 areRW, RC, RO, and WC. RW isa readand writeregister.RC isa read and clearregister.Upon readingthevalueoftheRC registerthroughMDIO, theregisterresetsitsvalue. WC isa writeand clearregister.Writeand clearregistersare used forresetoperations.A re-readoftheWC registerisnecessarytoverifytheregisterhas been cleared. Address Name Access Description(hex) 0 RESERVED RW Reserved. 1 POWERDOWN RW Transmiterand ReceiverPOWERDOWN control. 2 OUI RO OUI. 4 RESET RC Transmiterand ReceiverRESET control. 5 Rx Equalization RW CPRI LOF (LossofFrame) bypassand ReceiverEQ control. 6 Tx De-Emphasis RW Hyperframesizeand Transmitterde-emphasiscontrol. 7 LOOPBACK RW SelectsNormal,Lineand LocalLoopback. 8 MDIO RO Requiremed by MDIO. 9 BIST RW Patternand EnablecontrolforTrasmitand ReceiveBIST. A Speed Mode RW/Pin OW SelectsCPRI speed mode. B BIST Status RC BIST statusinformation. C RESERVED RO Reserved. D DCM Start RC InitiatesorrestartsDelayCalibrationMeasurement. E OUI Duplicate RO DuplicateofRegisterAddress2. F OUI Rev.Duplicate RO DuplicateofRegisterAddress3. 10 LOF RC CPRI Loss ofFrame (LOF)counter. 11 LOS RC CPRI Loss ofSync (LOS) counter. 12 Rx Lock RC ReceiverLoss ofLock (LOCKB) counter. 13 Loss ofClock RO Loss ofTransmitand/orReceiveclock. 14 PLL Status RO Tx and Rx PLL status. 15 HyperframeLength RW Programmable HyperframeLengthcontrol. 16-17 DCM Trigger RW DelayCalibrationTriggerpattern. 18 Reserved RW Reserved.

19 HyperframeTuning RW Programmable Hyperframesizeand DCM enable

1A-1D Reserved RO Reserved. 1E T14 Lower RO T14 Measurement. 1F T14 Upper RO T14 Measurement. 20 ToffsetLower RO ToffsetMeasurement. 21 ToffsetUpper RO ToffsetMeasurement. 22 TserLower RO TserMeasurement. 23 TserUpper RO TserMeasurement. 24 Tdes Lower RO Tdes Measurement. 25 Tdes Upper RO Tdes Measurement. 26 Tin-outLower RO Tin-outMeasurement. 27 Tin-outUpper RO Tin-outMeasurement. 28 Tout-inLower RO Tout-inMeasurement. 29 Tout-inUpper RO Tout-inMeasurement. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com NOTE The Defaultregistervalues assume 614.4 mbps operationwith the RESETB, RXCLKMODE, TXPWDN, and RXPWDN pinstiedtoa logichigh. Reserved Address:00h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. Powerdown Control Address:01h Value:FFFFh Bit Default BitName Access BitDescription D15 –D9 7'h7F Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D8 1'b1 RX PWDNB RW ReceiverPowerdown: Writinga [0]tothisbitplacesthereceiverofthe SCAN25100 intoa lowpower mode. D7-D1 7'h7F Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D0 1'b1 TX PWDNB RW TransmiterPowerdown: Writinga [0]tothisbitplacesthetransmiterof theSCAN25100 intoa lowpower mode. OUI Address:02h 0Eh Value:2000h Bit Default BitName Access BitDescription D15 –D0 16'h2000 OUI RO TIidentifierassignedby theIEEE. OUI + Address:03h 0Fh Value:5FE4h Bit Default BitName Access BitDescription D15-D10 6'h17 OUI[19:24] RO TIidentifierassignedby theIEEE. D9-D4 6'h3E PartNumber RO SCAN25100 deviceidentifier(3Eh). D3-D0 4'h4 Revision RO SCAN25100 revisionnumber. Reset Address:04h Value:FFFFh Bit Default BitName Access BitDescription D15 –D9 7'h7F Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D8 1'b1 RX RESETB WC ReceiverReset:Writing[0]tothisbitresetsRx controllogic.Returnsa value1 aftera few REFCLK cycles.IfREFCLK ismissing,thelogic remainsresetmode. D7-D1 7'h7F Reserved — Reservedforfutureuse.Undefinedvaluereturnedwhen read. D0 1'b1 TX PWDNB WC TransmiterReset:Writing[0]tothisbitresetsTx controllogic.Returnsa value1 aftera few REFCLK cycles.IfREFCLK ismissing,thelogic remainsresetmode.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Receive Equalization Address:05h Value:0000h Bit Default BitName Access BitDescription D15 1'b0 LOF Bypass RW DisablesLOF controltoallowDCM when usinga non-CPRI hyperframe length D14 –D2 13'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D1-D0 2'd0 RX EQ RW Receive Equalization:Setsreceiveequalizationwhen EQ[1:0]pinsare loworfloating. TransmitDe-Emphasis Address:06h Value:2000h Bit Default BitName Access BitDescription D15 –D8 8'h20 HyperframeSize RW Setsnon-CPRI hyperframelength. D7-D2 6'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D1-D0 2'b00 TX DE RW TransmitDe-Emphasis: Setstransmitde-emphasiswhen PE[1:0]pins areloworfloating. Loopback Mode Address:07h Value:0000h Bit Default BitName Access BitDescription D15 –D4 12'h000 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D3-D0 4'b0000 Loopback RW Programs loopbackmode 4'b0000 Normal operation(noloopback) 4'bxx10 Lineloopbackmode 4'bxxx1 Localloopbackmode 4'b1000 Speciallocalloopbackmode 4'b0100 Speciallineloopbackmode 4'b1100 Digitalloopbackmode Allothercombinationsplacedeviceinnormaloperation. MDIO Address:08h Value:8000h Bit Default BitName Access BitDescription D15-D14 2'b10 Reserved RO RequiredMDIO bits.Returns2'b10when read. D13-D0 14'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. BIST Control Address:09h Value:0000h Bit Default BitName Access BitDescription D15-D11 4'h0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D10 1'b0 RX OutputEnable RW Rx Output Enable:Writinga [1]valueenablesROUT pinsinBIST mode. D9-D8 2'b00 BIST Enable RW [9]Rx BIST Verify,[8]Tx BIST Enable:Writing1'stothesebitsenables BIST mode. Tx and Rx BIST modes may be operatedindependently. D7-D6 2'b00 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D5-D4 2'b00 RX BIST RW Rx BIST PatternDetect 2b'00 CJPAT pattern(lane0 perXAUI specification) Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Bit Default BitName Access BitDescription 2b'01 PRWS10 (PseudoRandom Word Sequence)pattern 2b'10 Reservedpattern 2b'11 CJPAT pattern(lane0 perXAUI specification) D3-D2 2'b00 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D1-D0 2'b00 TX BIST RW Tx BIST PatternGeneration 2b'00 CJPAT pattern(lane0 perXAUI specification) 2b'01 PRWS10 (PseudoRandom Word Sequence)pattern 2b'10 Reservedpattern 2b'11 CJPAT pattern(lane0 perXAUI specification) Speed Mode Address:0Ah Value:0000h Bit Default BitName Access BitDescription D15 –D2 14'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D1-D0 2'd0 SPMODE RW SetsCPRI speed mode when SPMODE[1:0] pinsareloworfloating. BIST Status Address:0Bh Value:0100h Bit Default BitName Access BitDescription D15-D13 3'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D12 1'b1 BIST Stopped RC BIST Stopped: A value[1]willoccurwhen Rx BIST verifierhas been stoppedduringa comparision. D11 1'b0 BIST Error RC BIST Error:Returnsa [1]valuewhen thereceiveBIST verifierhas been stoppedortheBIST errorcountisgreaterthan10d'0.Returnsa [0]value ifno BIST errors. D10 1'b0 BIST Detect RC Rx BIST verifierstartscomparingtheinputdatasequence after3 cyclesof properlyalignedheadersequenceshave been detected.A valueof[1] impliesthatBIST verifierischeckingthepattern.A readoperationwill NOT clearthisbitnorwillitresetthealignmentofthepattern. D9-D0 10'd0 ErrorCount RC Thisregisterdisplaysthecumulativenumber ofreceivebiterrors.The errorcountstartsonce a BIST patternhas been detectedand thereceive BIST verifierisenabled.Thisregistercountsa maximum of10'h3FFerrors and remainsstaticas soon as BIST isstoppedon theRx verifierside.A readoperationduringtheBIST enabledmode willcleartheerrorcount. Reserved Address:0Ch Value:0249h Bit Default BitName Access BitDescription D15 –D0 16'h0249 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. Run DCM Address:0Dh Value:0000h Bit Default BitName Access BitDescription D15 –D2 14'd0 Reserved WC Reservedforfutureuse.Returnsundefinedvaluewhen read. D1 1'b0 Reserved WC Reservedforfutureuse.Returnsundefinedvaluewhen read. D0 1'b0 Run DCM WC Writinga [1]runsDCM.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Loss ofFrame (LOF) Address:10h Value:0000h Bit Default BitName Access BitDescription D15 –D9 7'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D8 1'd0 LOF Status RC CPRI lossofFrame (LOF)status.A [1]valueindicateslossofCPRI frame.A [0]valueindicatesframeacquired. D7-D0 8'h00 LOF Count RC Loss offramecount.The maximum countwhichcan be accumulatedin thisregisteris8'hFF. Loss ofSignal(LOS) Address:11h Value:0000h Bit Default BitName Access BitDescription D15 –D9 7'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D8 0'b0 LOS Status RC CPRI lossofsignal(LOS) status.A value[1]indicateslossofframe. D7-D0 8'd0 LOS Count RC Loss ofsignalcount.The maximum countwhichcan be accumulatedin thisregisteris8'hFF. DeserializerLoss ofLock Address:12h Value:0000h Bit Default BitName Access BitDescription D15 –D8 8'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D7-D0 8'd0 Loss ofRx Count RC DeserializerPLL lossoflockcountsincethelastreadoperationofthis register.The maximum countwhichcan be accumulatedinthisregisteris 8'hFF. Note:Duringnormaloperation,receivePLL can go throughmultiple lockingcyclesbeforefinallydeclaringlock.Thisisnormalbehavior. Pin and Loss ofClock StatusRegisters Address:13h Value:3015h Bit Default BitName Access BitDescription D15-D14 2'b00 SPMODE[1:0] RO SPMODE[1:0] pinstatus D13 1'b1 TXPWDNB RO TXPWDNB pinstatus D12 1'b1 RXPWDNB RO RXPWDNB pinstatus D11 1'b0 LocalLoopback RO A value[1]indicateslocalloopbackisenabled D10 1'b0 LineLoopback RO A value[1]indicateslineloopbackisenabled D9 1'b0 SpecialLocal RO A value[1]indicatesspeciallocalloopbackisenabled Loopback D8 1'b0 SpecialLine RO A value[1]indicatesspeciallineloopbackisenabled Loopback D7 1'b0 DigitalLoopback RO A value[1]indicatesdigitalloopbackisenabled D6 1'b0 TX 10B mode RO D5 1'b0 RX 10B mode RO D4 1'b1 RXCLKMODEB RO InvertedvalueofRXCLKMODE pin. D3-D2 2'b01 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D1 1'b0 Loss ofTx Clock RO Thisregisterbitindicatesa lossofTXCLK. A valueof1 indicatesthe TXCLK isnotpresentornotrunninginthecurrentlyprogrammed speed mode. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Bit Default BitName Access BitDescription D0 1'b1 Loss ofRx Clock RO Thisregisterbitindicatesa lossofTXCLK. A valueof1 indicatesthe RXCLK isnotpresentornotrunninginthecurrentlyprogrammed speed mode. The RXCLK featureisonlysupportedinSCAN25100 READ mode operation. Misc Status2 Address:14h Value:0000h Bit Default BitName Access BitDescription D15 –D8 8'd0 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D7 RXCDR Lock - RO A value[0]indicatesthedeserializerPLL islocked Ready D6-D2 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. D1 TXPLL Lock -Ready RO A value[1]indicatestheserializerPLL islocked D0 TXPLL Counter RO Forinternaluse. StartofHyperframe Character Address:15h Value:01BCh Bit Default BitName Access BitDescription D15-D10 6'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D9-D0 10'h1BC 8b StartofHF RW 8b-bitmode startofhyperframecharacter Character StartofHyperframe Character Address:16h Value:017Ch Bit Default BitName Access BitDescription D15-D10 6'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D9-D0 10'h17C 10b StartofHF RW 10b-bitmode startofhyperframepositivecharacter Character+ StartofHyperframe Character Address:17h Value:0283h Bit Default BitName Access BitDescription D15-D10 6'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D9-D0 10'h283 10b StartofHF RW 8b-bitmode startofhyperframenegativecharacter Character- Reserved Address:18h Value:0EF5h Bit Default BitName Access BitDescription D15 –D0 16'h0EF5 Reserved — Reservedforfutureuse.Returnsundefinedvaluewhen read. DCM Address:19h Value:0000h Bit Default BitName Access BitDescription D15-D12 4'h0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Bit Default BitName Access BitDescription D11 1'b0 HyperframeLength RW Enablesnon-standardhyperframelengthtobe used withDCM Enable D10-D9 2'b00 InitialPower up wait RW These bitsprogramthepower up waitcycleforCPRI delaybiascircuitry cycle 2'b00 66us 2'b01 33us 2'b10 66us 2'b11 128us D8-D1 7'd0 Reserved RW Reservedforfutureuse.Returnsundefinedvaluewhen read. D0 1'b0 EnableDCM RW A value[1]enablesDCM controlcircuitry. Reserved Address:1Ah 1Bh 1Ch 1Dh Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. T14 Lower Address1Eh Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 T14 Lower RO Lower 16 T14 DCM bits.T14 isdefinedas Tx serialtoRx serialdelay. Thisistheroundtripdelayofthecable+ remoteside. T14 Upper Address1Fh Value:0000h Bit Default BitName Access BitDescription D15 –D6 10'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 T14 Upper RO Upper 5 T14 DCM bits.T14 isdefinedas Tx serialtoRx serialdelay.This istheroundtripdelayofthecable+ remoteside. ToffsetLower Address20h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 ToffsetLower RO Lower 16 ToffsetDCM bits.Toffsetisdefinedas theRx serialtoTx serial delay. ToffsetUpper Address21h Value:0000h Bit Default BitName Access BitDescription D15 –D6 10'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 ToffsetUpper RO Upper 5 ToffsetDCM bits.Toffsetisdefinedas theRx serialtoTx serial delay. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com Tser Lower Address22h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 TserLower RO Lower 16 TserDCM bits.Tserisdefinedas theserializerdelay. Tser Upper Address23h Value:0000h Bit Default BitName Access BitDescription D15 –D6 10'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 TserUpper RO Upper 5 TserDCM bits.Tserisdefinedas theserializerdelay. Tdes Lower Address24h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 Tdes Lower RO Lower 16 Tdes DCM bits.Tdes isdefinedas thedeserializerdelay. Tdes Upper Address25h Value:0000h Bit Default BitName Access BitDescription D15 –D6 10'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 Tdes Upper RO Upper 5 Tdes DCM bits.Tdes isdefinedas thedeserializerdelay. Tin-outLower Address26h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 Tin-outLower RO Lower 16 Tin-outDCM bits.Tin-outisdefinedas thedelaybetween theTx parallelinputsand theRx paralleloutputs. Tin-outUpper Address27h Value:0000h Bit Default BitName Access BitDescription D15 –D6 10'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 Tin-outUpper RO Upper 5 Tin-outDCM bits.Tin-outisdefinedas thedelaybetween theTx parallelinputsand theRx paralleloutputs. Tout-inLower Address28h Value:0000h Bit Default BitName Access BitDescription D15 –D0 16'd0 Tout-inLower RO Lower 16 Tout-inDCM bits.Tout-inisdefinedas thedelaybetween the Rx paralleloutputsand theTx parallelinputs.

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www.ti.com SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 Tout-inUpper Address29h Value:0000h Bit Default BitName Access BitDescription D15 –D8 8'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D7 1'd0 DCM Error RO Thisbitissetto[1]ifLOF isdetectedduringDCM measurement D6 1'd0 DCM Ready RO DCM resultsreadywhen thisbitis[1] D5 1'd0 Reserved RO Reservedforfutureuse.Returnsundefinedvaluewhen read. D4 –D0 5'd0 Tout-inUpper RO Upper 5 Tout-inDCM bits.Tout-inisdefinedas thedelaybetween theRx paralleloutputsand theTx parallelinputs. Design and Layout Guidelines The SCAN25100 isa 2457.6,1228.8,and 614.4Mbps serializer/deseralizer(SerDes)forhigh-speedbidirectional serialdatatransmissionoverFR-4 printedcircuitboardbackplanes,balancedcables,and opticalfiber.Thishigh- speed operationisachievedwithoutsignificantlayoutand overallPCB designconstraints.However,adheringto a few specificlayoutguidelineswilloptimizesignalintegrityand performance.The followinglistof topicsis coveredinTexas InstrumentsApplicationNote,AN-1463(SNLA078 ). 1. AC couplingcapacitorplacement,sizeand value. 2. Highspeed differentialsignalingoptions(microstrip/stripline/twin-axcable) 3. REFCLK terminations 4. DDR impedance recommendations 5. Decoupling 6. Power Filtering 7. Thermalrecommendations Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:SCAN25100

SNLS223C –SEPTEMBER 2006–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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www.ti.com 20-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SCAN25100TYA/NOPB NRND HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 SCAN25100TYA SCAN25100TYAX/NOPB NRND HTQFP PZP 100 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 SCAN25100TYA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 20-Jan-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Summary

SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

Description

SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

Source title SCAN25100TYA/NOPB Datasheet(PDF) - Texas Instruments

Read SCAN25100TYA/NOPB online.

SCAN25100_16 TI1 | Alldatasheet

Document overview

Technical content

2 SubmitDocumentationFeedback Copyright© 2006–2013,Texas InstrumentsIncorporated

11 DOUTN terminationresistorsconnectfromDO+ and DO − toan internalreference

66 DIN [1] LVCMOS Internal

67 DIN [2] pulldown In10-bitmode, the10-bitcode-groupatDIN [0–9]isserializedwiththeinternal8b/10b

69 DIN [4]

70 DIN [5] In8-bitmode, DIN [0-7]isfirstconvertedinto10-bitcode-groupby theinternal8b/10b

54 ROUT [1] LVCMOS Internal

57 ROUT [4]

23 SYSCLKN

91 RXPWDNB LVCMOS InternalTXPWDNB

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36 ADD1

35 ADD2

34 ADD3

33 ADD4

41 TDO Internalpullup on

44 TMS TDI,TMS, and

43 TCK TRSTB

46 TRSTB

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100 Ohm Media

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50 Ohm (2x)

0 X x DOUTP and DOUTN pulledto

1 MissingREFCLK x Undefined

1 MissingTXCLK x Logic1

1 Not Locked x DOUTP and DOUTN pulledto

1 Not Locked x Underflow/Overflow 10'd0(10-bitMode)

1 MissingREFCLK & in10B High-Z Undefined Undefined

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30.72 MHz (BTS Mode)

30.72 MHzREFCLK

30.72 MHz

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19 HyperframeTuning RW Programmable Hyperframesizeand DCM enable

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REVISION HISTORY

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SCAN25100TYA/NOPB specifications and overview.

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