SCAN18540T

SCAN18540T NSC | Alldatasheet

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n IEEE 1149.1 (JTAG) compliant n Dual output enable signals per byte n TRI-STATE outputs for bus-oriented applications n 9-bit data busses for parity applications n Reduced-swing outputs source 24 mA/sink 48 mA (Mil) n Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V n TTL compatible inputs n 25 mil pitch Cerpack packaging n Includes CLAMP and HIGHZ instructions n Standard Microcircuit Drawing (SMD) 5962-9312701 Connection Diagram Pin Names Description AI(0–8) Input pins, A side BI(0–8) Input pins, B side Pin Names Description AOE 1, AOE2 TRI-STATE Output Enable Input pins, A side BOE 1, BOE2 TRI-STATE Output Enable Input pins, B side AO (0–8) Output pins, A side BO (0–8) Output pins, B side TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS100323-1 September 1998 SCAN18540T Inverting Line Driver with TRI-STATE Outputs © 1998 National Semiconductor Corporation DS100323 www.national.com

Inputs AO (0–8) AOE 1 AOE 2 AI (0–8) LL H L HX X Z XH X Z LL L H Inputs BO (0–8) BOE 1 BOE 2 BI (0–8) LL H L HX X Z XH X Z LL L H H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Block Diagrams Byte-A DS100323-2 Tap Controller DS100323-3 www.national.com 2

Block Diagrams (Continued) Byte-B DS100323-4 Note:BSR stands for Boundary Scan Register www.national.com3

Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10–11for a further description of scan cell TYPE1 andFigure 10–12for a fur- ther description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable sig- nals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage iden- tical to scan cell TYPE1. It captures a fixed logic low. The INSTRUCTION register is an 8-bit register which cap- tures the default value of 01001101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18540T device. SCAN CMOS Test Access Logic devices do not in- clude the IEEE 1149.1 optional identification register. There- fore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. MSB → LSB Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGH-Z

Bypass Register Scan Chain Definition Logic 0 DS100323-9 Instruction Register Scan Chain Definition DS100323-10 www.national.com 4

Description of BOUNDARY-SCAN Circuitry(Continued) Scan Cell TYPE1 DS100323-7 Scan Cell TYPE2 DS100323-8 www.national.com5

Description of BOUNDARY-SCAN Circuitry(Continued) BOUNDARY-SCAN Register Scan Chain Definition (42 Bits in Length) DS100323-23 www.national.com 6

Description of BOUNDARY-SCAN Circuitry(Continued) BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type

41 AOE 1 3 Input TYPE1

40 AOE 2 54 Input TYPE1

39 AOE Internal TYPE2

38 BOE

37 BOE 2 31 Input TYPE1

36 BOE Internal TYPE2

A–in

34 AI 1 53 Input TYPE1

33 AI 2 52 Input TYPE1

32 AI 3 50 Input TYPE1

31 AI 4 49 Input TYPE1

30 AI 5 47 Input TYPE1

29 AI 6 46 Input TYPE1

28 AI 7 44 Input TYPE1

27 AI 8 43 Input TYPE1

26 BI 0 42 Input TYPE1

B–in

25 BI 1 41 Input TYPE1

24 BI 2 39 Input TYPE1

23 BI 3 38 Input TYPE1

22 BI 4 36 Input TYPE1

21 BI 5 35 Input TYPE1

20 BI 6 33 Input TYPE1

19 BI 7 32 Input TYPE1

18 BI 8 30 Input TYPE1

17 AO 0 2 Output TYPE2

A–out

16 AO 1 4 Output TYPE2

15 AO 2 5 Output TYPE2

14 AO 3 7 Output TYPE2

13 AO 4 8 Output TYPE2

12 AO 5 10 Output TYPE2

11 AO 6 11 Output TYPE2

10 AO 7 13 Output TYPE2

B–in 7B O 1 16 Output TYPE2 6B O 2 18 Output TYPE2 5B O 3 19 Output TYPE2 4B O 4 21 Output TYPE2 3B O 5 22 Output TYPE2 2B O 6 24 Output TYPE2 1B O 7 25 Output TYPE2 0B O 8 27 Output TYPE2 www.national.com7

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO ) −0.5V to V CC +0.5V DC Output Source/Sink Current (IO ) ±70 mA DC V CC or Ground Current Per Output Pin ±70 mA Junction Temperature Cerpack +175˚C Storage Temperature −65˚C to +150˚C ESD (Min) 2000V Recommended Operating Conditions Supply Voltage (VCC ) SCAN Products 4.5V to 5.5V Input Voltage (VI) 0 Vt oV CC Output Voltage (VO ) 0 Vt oV CC Operating Temperature (TA) Military −55˚C to +125˚C Minimum Input Edge Rate dV/dt 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1:Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of SCAN circuits outside databook specifications. Symbol Parameter V CC (V) Military Units Conditions TA = −55˚C to +125˚C Guaranteed Limits VIH Minimum High 4.5 2.0 V V OUT = 0.1V Input Voltage 5.5 2.0 or V CC −0.1V VIL Maximum Low 4.5 0.8 V V OUT = 0.1V Input Voltage 5.5 0.8 or V CC −0.1V VOH Minimum High 4.5 3.15 V I OUT = −50 µA Output Voltage 5.5 4.15 4.5 2.4 V V IN = VIL or VIH 5.5 2.4 I OH = −24 mA VOL Maximum Low 4.5 0.1 V I OUT = 50 µA Output Voltage 5.5 0.1 4.5 0.55 V IN = VIL or VIH 5.5 0.55 I OL = 48 mA IIN Maximum Input 5.5 ±1.0 µA V I = VCC , GND Leakage Current IIN Maximum Input 5.5 3.7 µA V I = VCC TDI, TMS Leakage −385 µA V I = GND Minimum Input 5.5 −160 µA V I = GND Leakage IOLD Minimum Dynamic 5.5 63 mA V OLD = 0.8V Max IOHD Output Current (Note 2) −27 mA V OHD = 2.0V Min IOZ Maximum Output 5.5 ±10.0 µA V I (OE) = VIL,V IH Leakage Current IOS Output Short 5.5 −100 mA Min VO = 0V Circuit Current ICC Maximum Quiescent 5.5 168 µA V O = Open Supply Current TDI, TMS = VCC 5.5 930 µA V O = Open TDI, TMS = GND www.national.com 8

(V) Military Units Conditions TA = −55˚C to +125˚C Guaranteed Limits ICCt Maximum ICC Per Input 5.5 2.0 mA V I = VCC –2.1V VI = VCC –2.1V 5.5 2.15 mA TDI/TMS Pin, Test One with the other Floating Note 2:Maximum test duration 2.0 ms, one output loaded at a time. Note 3:All outputs loaded; thresholds associated with output under test. Noise Specifications Symbol Parameter V CC (V) Military Units TA = −55˚C to +125˚C Guaranteed Limits VOLP Maximum High 0.8 Output Noise 5.0 V (Notes 4, 5) V OLV Minimum Low -0.8 Output Noise 5.0 V (Notes 4, 5) Note 4:Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 5:Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Normal Operation Symbol Parameter V CC (V) (Note 7) Military Units TA = −55˚C to +125˚C C L = 50 pF Min Max tPLH , Propagation Delay 5.0 2.5 10.5 ns tPHL Data to Q 2.5 11.0 tPLZ , Disable Time 5.0 1.5 11.2 ns tPHZ 1.5 11.2 tPZL , Enable Time 5.0 2.0 14.0 ns tPZH 2.0 12.0 Scan Test Operation Symbol Parameter V CC (V) (Note 7) Military Units TA = −55˚C to +125˚C C L = 50 pF Min Max tPLH , Propagation Delay 5.0 3.5 15.8 ns tPHL TCK to TDO 3.5 15.8 tPLZ , Disable Time 5.0 2.5 12.8 ns tPHZ TCK to TDO 2.5 12.8 www.national.com9

(V) (Note 7) Military Units TA = −55˚C to +125˚C C L = 50 pF Min Max tPZL , Enable Time 5.0 3.0 16.7 ns tPZH TCK to TDO 3.0 16.7 tPLH , Propagation Delay tPHL TCK to Data Out 5.0 5.0 21.7 ns During Update- 5.0 21.7 -DR State t PLH , Propagation Delay tPHL TCK to Data Out 5.0 5.0 21.2 ns During Update- 5.0 21.2 IR State t PLH , Propagation Delay tPHL TCK to Data Out 5.0 5.5 23.0 ns During Test Logic 5.5 23.0 Reset State t PLZ , Propagation Delay tPHZ TCK to Data Out 5.0 4.0 19.6 ns During Update- 4.0 19.6 DR State t PLZ , Propagation Delay tPHZ TCK to Data Out 5.0 5.0 22.4 ns During Update- 5.0 22.4 IR State t PLZ , Propagation Delay tPHZ TCK to Data Out 5.0 5.0 23.3 ns During Test Logic 5.0 23.3 Reset State t PZL , Propagation Delay 5.0tPZH TCK to Data Out 5.0 22.6 ns During Update- 5.0 22.6 DR State t PZL , Propagation Delay tPZH TCK to Data Out 5.0 6.5 26.2 ns During Update- 6.5 26.2 IR State t PZL , Propagation Delay tPZH TCK to Data Out 5.0 7.0 27.4 ns During Test Logic 7.0 27.4 Reset State Note 6:All Propagation Delays involving TCK are measured from the falling edge of TCK. www.national.com 10

(V) (Note 7) Military Units TA = −55˚C to +125˚C C L = 50 pF Guaranteed Minimum tS Setup Time, H or L 5.0 3.0 ns Data to TCK (Note 8) t H Hold Time, H or L 5.0 5.5 ns TCK to Data (Note 8) t S Setup Time, H or L AOE n, BOEn 5.0 3.0 ns to TCK (Note 10) tH Hold Time, H or L TCK to AOE n, 5.0 4.5 ns BOE n (Note 10) tS Setup Time, H or L Internal AOE, BOE, 5.0 3.0 ns to TCK (Note 9) t H Hold Time, H or L TCK to Internal 5.0 3.0 ns AOE, BOE (Note 9) t S Setup Time, H or L 5.0 8.0 ns TMS to TCK t H Hold Time, H or L 5.0 2.0 ns TCK to TMS t S Setup Time, H or L 5.0 4.0 ns TDI to TCK t H Hold Time, H or L 5.0 4.5 ns TCK to TDI t W Pulse Width TCK 5.0 H 12.0 ns L 5.0 fmax Maximum TCK 5.0 25 MHz Clock Frequency T PU Wait Time, 5.0 100 ns Power Up to TCK T DN Power Down Delay 0.0 100 ms Note 7:Voltage Range 5.0 is 5.0V±0.5V. All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note 8:This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26, and 27-35. Note 9:This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 10:Timing pertains to BSR 37, 38, 40 and 41. www.national.com11

Symbol Parameter Typ Units Conditions C IN Input Pin Capacitance 4.0 pF V CC = 5.0V C OUT Output Pin Capacitance 13.0 pF V CC = 5.0V C PD Power Dissipation 34.0 pF V CC = 5.0V Capacitance www.national.com 12

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 56-Lead Ceramic Flatpak (F) SCAN18540T Inverting Line Driver with TRI-STATE Outputs National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.