SCAN18373T

SCAN18373T FAIRCHILD | Alldatasheet

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I IEEE 1149.1 (JTAG) Compliant I Buffered active-low latch enable I 3-STATE outputs for bus-oriented applications I 9-bit data busses for parity applications I Reduced-swing outputs source 32 mA/sink 64 mA I Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V I TTL compatible inputs I 25 mil pitch SSOP (Shrink Small Outline Package) I Includes CLAMP and HIGHZ instructions I Member of Fairchild’s SCAN Products Ordering Code: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO 0 = Previous AO before H-to-L transition of ALE BO 0 = Previous BO before H-to-L transition of BLE Order Number Package Number Package Description SCAN1837TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Pin Names Description AI(0–8), BI(0–8) Data Inputs ALE, BLE Latch Enable Inputs AOE 1, BOE1 3-STATE Output Enable Inputs AO (0–8), BO(0–8) 3-STATE Latch Outputs Inputs AO (0–8) ALE AOE 1 AI(0–8) XH X Z HL L L HL H H LL X A O 0 Inputs BO (0–8) BLE BOE 1 BI(0–8) XH X Z HL L L HL H H LL X B O 0

www.fairchildsemi.com 2 SCAN18373T Functional Description The SCAN18373T consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI (0–8) or BI(0–8)) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW tran- sition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable (AOE 1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the stan- dard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A

3 www.fairchildsemi.com SCAN18373T Block Diagrams (Continued) Tap Controller Byte-B Note: BSR stands for Boundary Scan Register.

www.fairchildsemi.com 4 SCAN18373T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an eight-bit register which captures the value 00111101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition MSB → LSB Scan Cell TYPE1 Scan Cell TYPE2 Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGHZ

5 www.fairchildsemi.com SCAN18373T Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (42 Bits in Length)

www.fairchildsemi.com 6 SCAN18373T Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type

41 AOE 1 3 Input TYPE1

40 ACP 54 Input TYPE1

39 AOE Internal TYPE2

38 BOE

37 BCP 31 Input TYPE1

36 BOE Internal TYPE2

A–in

34 AI1 53 Input TYPE1

33 AI2 52 Input TYPE1

32 AI3 50 Input TYPE1

31 AI4 49 Input TYPE1

30 AI5 47 Input TYPE1

29 AI6 46 Input TYPE1

28 AI7 44 Input TYPE1

27 AI8 43 Input TYPE1

26 BI0 42 Input TYPE1

B–in

25 BI1 41 Input TYPE1

24 BI2 39 Input TYPE1

23 BI3 38 Input TYPE1

22 BI4 36 Input TYPE1

21 BI5 35 Input TYPE1

20 BI6 33 Input TYPE1

19 BI7 32 Input TYPE1

18 BI8 30 Input TYPE1

17 AO 0 2 Output TYPE2

A–out

16 AO 1 4 Output TYPE2

15 AO 2 5 Output TYPE2

14 AO 3 7 Output TYPE2

13 AO 4 8 Output TYPE2

12 AO 5 10 Output TYPE2

11 AO 6 11 Output TYPE2

10 AO 7 13 Output TYPE2

B–out 7B O 1 16 Output TYPE2 6B O 2 18 Output TYPE2 5B O 3 19 Output TYPE2 4B O 4 21 Output TYPE2 3B O 5 22 Output TYPE2 2B O 6 24 Output TYPE2 1B O 7 25 Output TYPE2 0B O 8 27 Output TYPE2

7 www.fairchildsemi.com SCAN18373T Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications. Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO ) ±70 mA DC V CC or Ground Current Per Output Pin ±70 mA Junction Temperature SSOP +140°C Storage Temperature −65°C to +150°C ESD (Min) 2000V Supply Voltage (VCC ) SCAN Products 4.5V to 5.5V Input Voltage (VI)0 V t o V CC Output Voltage (VO )0 V t o V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate ∆V/∆t 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH 4.5 3.15 3.15 VI OUT = −50 µA Output Voltage 5.5 4.15 4.15 (Note 2) 4.5 2.4 2.4 V VIN = VIL or VIH 5.5 2.4 2.4 I OH = −32 mA 4.5 2.4 V VIN = VIL or VIH 5.5 2.4 I OH = −24 mA VOL Maximum LOW 4.5 0.1 0.1 V I OUT = 50 µA Output Voltage 5.5 0.1 0.1 (Note 2) 4.5 0.55 0.55 V VIN = VIL or VIH 5.5 0.55 0.55 I OL = 64 mA 4.5 0.55 V VIN = VIL or VIH 5.5 0.55 I OL = 48 mA IIN Maximum Input 5.5 ±0.1 ±1.0 µAV I = VCC , GND Leakage Current IIN Maximum Input 5.5 2.8 3.6 µAV I = VCC TDI, TMS Leakage −385 −385 µAV I = GND Minimum Input Leakage 5.5 −160 −160 µAV I = GND IOLD Minimum Dynamic 5.5 94 94 mA V OLD = 0.8V Max IOHD Output Current (Note 3) −40 −40 mA V OHD = 2.0V Min IOZ Maximum Output 5.5 ±0.5 ±5.0 µAV I(OE) = VIL,VIHLeakage Current IOS Output Short 5.5 −100 −100 mA VO = 0V Circuit Current Min ICC Maximum Quiescent 5.5 16.0 88 µAV O = Open Supply Current TDI, TMS = VCC 5.5 750 820 µAV O = Open TDI, TMS= GND

www.fairchildsemi.com 8 SCAN18373T Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Note 4: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched LOW and one output held LOW. Note 5: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched HIGH and one output held HIGH. Note 6: Worst case package. Note 7: Maximum number of data inputs (n) switching. (n−1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). Normal Operation Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits ICCt Maximum ICC per Input 5.5 2.0 2.0 mA V I = VCC − 2.1V VI = VCC − 2.1V 5.5 2.15 2.15 mA TDI/TMS Pin, Test One with the Other Floating Symbol Parameter V CC TA = +25°CT A = −40°C to +85°C Units (V) Typ Guaranteed Limits VOLP Maximum HIGH Output Noise 5.0 1.0 1.5 V (Note 4)(Note 5) VOLV Minimum LOW Output Noise 5.0 −0.6 −1.2 V (Note 4)(Note 5) VOHP Maximum Overshoot 5.0 V OH + 1.0 V OH + 1.5 V (Note 5)(Note 6) VOHV Minimum VCC Droop 5.0 V OH − 1.0 V OH − 1.8 V (Note 5)(Note 6) VIHD Minimum HIGH Dynamic Input Voltage Level 5.5 1.6 2.0 2.0 V (Note 6)(Note 7) VILD Maximum LOW Dynamic Input Voltage Level 5.5 1.4 0.8 0.8 V (Note 6)(Note 7) Symbol Parameter VCC TA = +25°CT A =− 40°Ct o+85°C Units(V) C L = 50 pF C L = 50 pF (Note 8) Min Typ Max Min Max ns tPHL Delay, D to Q 2.5 9.0 2.5 9.8 ns tPHL Delay, LE to Q 2.5 10.5 2.5 11.3 ns tPHZ 1.5 9.5 1.5 10.0 ns tPZH 2.0 9.0 2.0 9.7

9 www.fairchildsemi.com SCAN18373T AC Operating Requirements Normal Operation Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Scan Test Operation Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All propagation delays involving TCK are measured from the falling edge of TCK. Symbol Parameter VCC TA = +25°CT A =− 40°Ct o+85°C Units(V) C L = 50 pF C L = 50 pF (Note 9) Guaranteed Minimum tS Setup Time, H or L 5.0 3.0 3.0 ns Data to LE tH Hold Time, H or L 5.0 1.5 1.5 ns LE to Data tW LE Pulse Width 5.0 5.0 5.0 ns Symbol Parameter VCC TA = +25°CT A =− 40°Ct o+85°C Units(V) C L = 50 pF C L = 50 pF (Note 10) Min Typ Max Min Max ns tPHL TCK to TDO 3.5 13.2 3.5 14.5 ns tPHZ TCK to TDO 2.5 11.5 2.5 11.9 ns tPZH TCK to TDO 3.0 14.5 3.0 15.8 tPLH , Propagation Delay 5.0 5.0 18.0 5.0 19.8 tPHL TCK to Data Out 5.0 18.0 5.0 19.8 ns during Update-DR State tPLH , Propagation Delay 5.0 5.0 18.6 5.0 20.2 tPHL TCK to Data Out 5.0 18.6 5.0 20.2 ns during Update-IR State tPLH , Propagation Delay 5.0 5.5 19.9 5.5 21.5 tPHL TCK to Data Out ns during Test Logic 5.5 19.9 5.5 21.5 Reset State tPLZ , Propagation Delay 5.0 4.0 16.4 4.0 18.2 tPHZ TCK to Data Out 4.0 16.4 4.0 18.2 ns during Update-DR State tPLZ , Propagation Delay 5.0 19.5 5.0 20.8 during Update-IR State tPLZ , Propagation Delay 5.0 19.9 5.0 21.5 tPHZ TCK to Data Out 5.0 ns during Test Logic 5.0 19.9 5.0 21.5 Reset State t PZL , Propagation Delay 5.0 18.9 5.0 20.9 during Update-DR State t PZL , Propagation Delay 6.5 22.4 6.5 24.2 during Update-IR State t PZL , Propagation Delay 7.0 23.8 7.0 25.7 tPZH TCK to Data Out 5.0 ns during Test Logic 7.0 23.8 7.0 25.7 Reset State

www.fairchildsemi.com 10 SCAN18373T AC Operating Requirements Scan Test Operation Note 11: Voltage Range 5.0 is 5.0V ± 0.5V. Note 12: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 13: Timing pertains to BSR 38 and 41 only. Note 14: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 15: Timing pertains to BSR 37 and 40 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Symbol Parameter VCC TA = +25°CT A =− 40°Ct o+85°C Units(V) C L = 50 pF C L = 50 pF (Note 11) Guaranteed Minimum tS Setup Time, 5.0 3.0 3.0 ns Data to TCK (Note 12) tH Hold Time, 5.0 4.5 4.5 ns TCK to Data (Note 12) tS Setup Time, H or L 5.0 3.0 3.0 ns AOE 1, BOE1 to TCK (Note 13) tH Hold Time, H or L 5.0 4.5 4.5 ns TCK to AOE1, BOE1 (Note 13) tS Setup Time, H or L Internal AOE, BOE, 5.0 3.0 3.0 ns to TCK (Note 14) t H Hold Time, H or L TCK to Internal 5.0 3.0 3.0 ns AOE, BOE (Note 14) t S Setup Time 5.0 3.0 3.0 ns ALE, BLE (Note 15) to TCK tH Hold Time 5.0 3.5 3.5 ns TCK to ALE, BLE (Note 15) tS Setup Time, H or L 5.0 8.0 8.0 ns TMS to TCK tH Hold Time, H or L 5.0 2.0 2.0 ns TCK to TMS tS Setup Time, H or L 5.0 4.0 4.0 ns TDI to TCK tH Hold Time, H or L 5.0 4.5 4.5 ns TCK to TDI tW Pulse Width TCK 5.0 H1 5 . 0 1 5 . 0 n s L5 . 0 5 . 0 fMAX Maximum TCK 5.0 25 25 MHz Clock Frequency Tpu Wait Time, Power Up to TCK 5.0 100 100 ns Tdn Power Down Delay 0.0 100 100 ms

11 www.fairchildsemi.com SCAN18373T Extended AC Electrical Characteristics Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.). Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 18: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 19: The Output Disable Time is dominated by the RC network (500Ω , 250 pF) on the output and has been excluded from the datasheet. Note 20: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL ), LOW-to-HIGH (tOSLH ), or any combination switching LOW-to-HIGH. Capacitance Symbol Parameter TA = 25°C Units VCC = 5.0V C L = 50 pF T A = −40°C to +85°C 18 Outputs VCC = 5.0V ± 0.5V Switching C L = 250 pF (Note 16) (Note 17) Min Typ Max Min Max tPLH Propagation Delay 3.0 12.0 4.0 13.5 ns tPHL Latch Enable to Output 3.0 12.8 4.0 16.0 tPLH Propagation Delay 3.0 11.5 4.0 13.0 ns tPHL Data to Output 3.0 11.5 4.0 14.5 tPZH Output Enable Time 2.5 10.5 (Note 18) ns tPZL 2.5 12.5 tPHZ Output Disable Time 2.0 10.5 (Note 19) ns tPLZ 2.0 10.5 tOSHL Pin to Pin Skew 0.5 1.0 1.0 ns (Note 20) HL Data to Output tOSLH Pin to Pin Skew 0.5 1.0 1.0 ns (Note 20) LH Data to Output Symbol Parameter Typ Units Conditions C IN Input Pin Capacitance 4.0 pF V CC = 5.0V C OUT Output Pin Capacitance 13.0 pF V CC = 5.0V C PD Power Dissipation Capacitance 34.0 pF V CC = 5.0V

www.fairchildsemi.com 12 SCAN18373T Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com