SCAN18245T

SCAN18245T FAIRCHILD | Alldatasheet

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I IEEE 1149.1 (JTAG) Compliant I Dual output enable control signals I 3-STATE outputs for bus-oriented applications I 9-bit data busses for parity applications I Reduced-swing outputs source 32 mA/sink 64 mA I Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V I TTL compatible inputs I 25 mil pitch SSOP (Shrink Small Outline Package) I Includes CLAMP and HIGHZ instructions I Member of Fairchild’s SCAN Products Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description SCAN18245TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Pin Names Description A1(0–8) Side A1 Inputs or 3-STATE Outputs B1(0–8) Side B1 Inputs or 3-STATE Outputs A2(0–8) Side A2 Inputs or 3-STATE Outputs B2(0–8) Side B2 Inputs or 3-STATE Outputs G1 , G2 Output Enable Pins DIR1, DIR2 Direction of Data Flow Pins

www.fairchildsemi.com 2 SCAN18245T Truth Table H = HIGH Voltage Level L= LOW Voltage Level X= Immaterial Z= High Impedance Functional Description The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, when HIGH enables data from A Ports to B Ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition. Block Diagrams A1, B1, G1 and DIR1 Note: BSR stands for Boundary Scan Register. A2, B2, G2 and DIR2 Note: BSR stands for Boundary Scan Register. Tap Controller Inputs A1 (0–8) B1 (0–8) Inputs A2 (0–8) B2 (0–8) G1 DIR1 G2 DIR2 LLH ← HL L H ← H LLL ← LL L L ← L LHH → HL H H → H LHL → LL H L → L HXZ Z HXZ Z

3 www.fairchildsemi.com SCAN18245T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. (See IEEE Standard 1149.1 Figure 10–11 for a further description of scan cell TYPE1 and Figure 10–12 for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an eight-bit register which captures the value 00111101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition MSB → LSB Scan Cell TYPE1 Scan Cell TYPE2 Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGHZ

www.fairchildsemi.com 4 SCAN18245T Boundary-Scan Register Scan Chain Definition (80 Bits in Length)

5 www.fairchildsemi.com SCAN18245T Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type Bit No. Pin Name Pin No. Pin Type Scan Cell Type

79 DIR1 3 Input TYPE1

35 B1 0 2 Input TYPE1

B1–in

78 G1 54 Input TYPE1 34 B1 1 4 Input TYPE1

77 AOE 1 Internal TYPE2 33 B1 2 5 Input TYPE1

76 BOE 1 Internal TYPE2 32 B1 3 7 Input TYPE1

75 DIR2 26 Input TYPE1 31 B1 4 8 Input TYPE1

74 G2 31 Input TYPE1 30 B1 5 10 Input TYPE1

73 AOE 2 Internal TYPE2 29 B1 6 11 Input TYPE1

72 BOE 2 Internal TYPE2 28 B1 7 13 Input TYPE1

71 A1 0 55 Input TYPE1

A1–in

27 B1 8 14 Input TYPE1

70 A1 1 53 Input TYPE1 26 B2 0 15 Input TYPE1

B2–in

69 A1 2 52 Input TYPE1 25 B2 1 16 Input TYPE1

68 A1 3 50 Input TYPE1 24 B2 2 18 Input TYPE1

67 A1 4 49 Input TYPE1 23 B2 3 19 Input TYPE1

66 A1 5 47 Input TYPE1 22 B2 4 21 Input TYPE1

65 A1 6 46 Input TYPE1 21 B2 5 22 Input TYPE1

64 A1 7 44 Input TYPE1 20 B2 6 24 Input TYPE1

63 A1 8 43 Input TYPE1 19 B2 7 25 Input TYPE1

62 A2 0 42 Input TYPE1

A2–in

18 B2 8 27 Input TYPE1

61 A2 1 41 Input TYPE1 17 A1 0 55 Output TYPE2

A1–out

60 A2 2 39 Input TYPE1 16 A1 1 53 Output TYPE2

59 A2 3 38 Input TYPE1 15 A1 2 52 Output TYPE2

58 A2 4 36 Input TYPE1 14 A1 3 50 Output TYPE2

57 A2 5 35 Input TYPE1 13 A1 4 49 Output TYPE2

56 A2 6 33 Input TYPE1 12 A1 5 47 Output TYPE2

55 A2 7 32 Input TYPE1 11 A1 6 46 Output TYPE2

54 A2 8 30 Input TYPE1 10 A1 7 44 Output TYPE2

53 B1 0 2 Output TYPE2

B1–out 9A 1 8 43 Output TYPE2

52 B1 1 4 Output TYPE2 8 A2 0 42 Output TYPE2

A2–out

51 B1 2 5 Output TYPE2 7 A2 1 41 Output TYPE2

50 B1 3 7 Output TYPE2 6 A2 2 39 Output TYPE2

49 B1 4 8 Output TYPE2 5 A2 3 38 Output TYPE2

48 B1 5 10 Output TYPE2 4 A2 4 36 Output TYPE2

47 B1 6 11 Output TYPE2 3 A2 5 35 Output TYPE2

46 B1 7 13 Output TYPE2 2 A2 6 33 Output TYPE2

45 B1 8 14 Output TYPE2 1 A2 7 32 Output TYPE2

44 B2 0 15 Output TYPE2

B2–out 0A 2 8 30 Output TYPE2

43 B2 1 16 Output TYPE2

42 B2 2 18 Output TYPE2

41 B2 3 19 Output TYPE2

40 B2 4 21 Output TYPE2

39 B2 5 22 Output TYPE2

38 B2 6 24 Output TYPE2

37 B2 7 25 Output TYPE2

36 B2 8 27 Output TYPE2

www.fairchildsemi.com 6 SCAN18245T Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications. Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC +0.5V DC Output Source/Sink Current (IO ) ±70 mA DC V CC or Ground Current Per Output Pin ±70 mA Junction Temperature SSOP +140°C Storage Temperature −65°C to +150°C ESD (Min) 2000V Supply Voltage (VCC ) SCAN Products 4.5V to 5.5V Input Voltage (VI) 0V to V CC Output Voltage (VO ) 0V to V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate ∆V/∆t 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH 4.5 3.15 3.15 VI OUT = −50 µA Output Voltage 5.5 4.15 4.15 (Note 2) 4.5 2.4 2.4 V VIN = VIL or VIH 5.5 2.4 2.4 I OH = −32 mA 4.5 2.4 V VIN = VIL or VIH 5.5 2.4 I OH = −24 mA VOL Maximum LOW 4.5 0.1 0.1 VI OUT = 50 µA Output Voltage 5.5 0.1 0.1 (Note 2) 4.5 0.55 0.55 V VIN = VIL or VIH 5.5 0.55 0.55 I OL = 64 mA 4.5 0.55 V VIN = VIL or VIH 5.5 0.55 I OL = 48 mA IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAV I = VCC , GND IIN Maximum Input Leakage 5.5 2.8 3.6 µAV I = VCC TDI, TMS −385 −385 µAV I = GND Minimum Input Leakage 5.5 −160 −160 µAV I = GND IOLD Minimum Dynamic 5.5 94 94 mA V OLD = 0.8V Max IOHD Output Current (Note 3) −40 −40 mA V OHD = 2.0V Min IOZT Maximum I/O 5.5 ±0.6 ±6.0 µA VI (OE) = VIL, Leakage Current VIHVI = VCC , GND VO = VCC , GND IOS Output Short Circuit Current 5.5 −100 −100 mA (min) V O = 0V ICC Maximum Quiescent 5.5 16.0 88 µA VO = HIGH Supply Current TDI, TMS = VCC 5.5 750 820 µA VO = HIGH TDI, TMS = GND

7 www.fairchildsemi.com SCAN18245T Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). Normal Operation Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits ICCt Maximum ICC Per Input 5.5 2.0 2.0 mA V I = VCC –2.1V VI = VCC –2.1V 5.5 2.15 2.15 mA TDI/TMS Pin, test one with the other floating Symbol Parameter V CC TA = +25°CT A = −40°C to +85°C Units (V) Typ Guaranteed Limits VOLP Maximum HIGH Output Noise 5.0 1.0 1.5 V (Note 5)(Note 6) VOLV Minimum LOW Output Noise 5.0 −0.6 −1.2 V (Note 5)(Note 6) VOHP Maximum Overshoot 5.0 V OH +1.0 V OH +1.5 V (Note 4)(Note 6) VOHV Minimum VCC Droop 5.0 V OH −1.0 V OH −1.8 V (Note 4)(Note 6) VIHD Minimum HIGH Dynamic Input 5.5 1.6 2.0 2.0 V Voltage Level (Note 4)(Note 7) VILD Maximum LOW Dynamic Input 5.5 1.4 0.8 0.8 V Voltage Level (Note 4)(Note 7) Symbol Parameter VCC TA = +25°CT A =−40°C to +85°C Units(V) C L = 50 pF C L = 50 pF (Note 8) Min Typ Max Min Max ns tPHL A to B, B to A 1.6 7.9 1.6 8.8 ns tPHZ 1.2 8.5 1.2 9.0 ns tPZH 1.6 8.5 1.6 9.5

www.fairchildsemi.com 8 SCAN18245T Scan Test Operation Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note: All Propagation Delays involving TCK are measured from the falling edge of TCK. Symbol Parameter VCC TA = +25°CT A =−40°C to +85°C Units(V) C L = 50 pF C L = 50 pF (Note 9) Min Typ Max Min Max ns tPHL TCK to TDO 2.8 13.2 2.8 14.5 ns tPHZ TCK to TDO 2.0 11.5 2.0 11.9 ns tPZH TCK to TDO 2.4 14.5 2.4 15.8 ns tPHL TCK to Data Out 4.0 18.0 4.0 19.8 During Update-DR State tPLH , Propagation Delay 4.0 18.6 4.0 20.2 ns During Update-IR State ns tPHL TCK to Data Out 4.4 19.9 4.4 21.5 During Test Logic Reset State t ns tPHZ TCK to Data Out 3.2 16.4 3.2 18.2 During Update-DR State ns tPHZ TCK to Data Out 2.8 18.0 2.8 19.3 During Update-IR State ns tPHZ TCK to Data Out 2.8 18.4 2.8 20.0 During Test Logic Reset State ns tPZH TCK to Data Out 4.0 18.9 4.0 20.9 During Update-DR State ns tPZH TCK to Data Out 3.2 19.9 3.2 21.7 During Update-IR State ns tPZH TCK to Data Out 3.6 21.3 3.6 23.3 During Test Logic Reset State

9 www.fairchildsemi.com SCAN18245T AC Operating Requirements Scan Test Operation Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. Note 11: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 12: Timing pertains to BSR 74 and 78 only. Note 13: Timing pertains to BSR 75 and 79 only. Note 14: Timing pertains to BSR 72, 73, 76 and 77 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units(V) C L = 50 pF C L = 50 pF (Note 10) Guaranteed Minimum tS Setup Time, H or L 5.0 0.0 0.0 ns Data to TCK (Note 11) tH Hold Time, H or L 5.0 6.5 6.5 ns TCK to Data (Note 11) tS Setup Time, H or L 5.0 0.0 0.0 ns G1 , G2 to TCK (Note 12) tH Hold Time, H or L 5.0 4.0 4.0 ns TCK to G1, G2 (Note 12) tS Setup Time, H or L 5.0 0.0 0.0 ns DIR1, DIR2 to TCK (Note 13) tH Hold Time, H or L 5.0 4.0 4.0 ns TCK to DIR1, DIR2 (Note 13) tS Setup Time, H or L nsInternal AOEn, BOEn 5.0 1.0 1.0 to TCK (Note 14) tH Hold Time, H or L 5.0 4.0 4.0 nsTCK to Internal AOEn, BOE n (Note 14) tS Setup Time, H or L 5.0 7.0 7.0 ns TMS to TCK tH Hold Time, H or L 5.0 2.0 2.0 ns TCK to TMS tS Setup Time, H or L 5.0 1.0 1.0 ns TDI to TCK tH Hold Time, H or L 5.0 3.5 3.5 ns TCK to TDI tW Pulse Width 5.0 nsH 15.0 15.0 L5 . 0 5 . 0 fMAX Maximum TCK 5.0 25 25 MHz Clock Frequency TPU Wait Time, 5.0 100 100 ns Power Up to TCK TDN Power Down 0.0 100 100 ms Delay

www.fairchildsemi.com 10 SCAN18245T Extended AC Electrical Characteristics Note 15: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to- HIGH, HIGH-to-LOW, etc.) Note 16: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 17: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 18: The Output Disable Time is dominated by the RC network (500Ω , 250 pF) on the output and has been excluded from the datasheet. Note 19: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL ), LOW-to-HIGH (tOSLH ), or any combination switching LOW-to-HIGH and/or HIGH- to-LOW. Capacitance Symbol Parameter TA = +25°C, VCC = 5.0V T A = −40°C to +85°C Units C L = 50 pF V CC = 5.0V ± 0.5V

18 Outputs Switching C L = 250 pF

(Note 15) (Note 16) Min Typ Max Min Max tPLH, Propagation Delay 2.5 10.5 3.5 12.0 ns tPHL Data to Output 2.5 10.5 3.5 13.5 tPZH , Output Enable Time 2.5 10.5 (Note 17) ns tPZL 2.5 13.5 tPHZ, Output Disable Time 2.0 9.5 (Note 18) ns tPLZ 2.0 10.0 tOSHL Pin to Pin Skew 0.5 1.0 1.0 ns (Note 19) HL Data to Output tOSLH Pin to Pin Skew 0.5 1.0 1.0 ns (Note 19) LH data to Output Symbol Parameter Typ Units Conditions C IN Input Pin Capacitance 4 pF V CC = 5.0V C I/O Input/Output Capacitance 20 pF V CC = 5.0V C PD Power Dissipation Capacitance 41 pF V CC = 5.0V

11 www.fairchildsemi.com SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com