SCAN182373A FAIRCHILD | Alldatasheet

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I IEEE 1149.1 (JTAG) Compliant I High performance BiCMOS technology I 25Ω series resistor outputs eliminate need for external terminating resistors I Buffered active-low latch enable I 3-STATE outputs for bus-oriented applications I 25 mil pitch SSOP (Shrink Small Outline Package) I Includes CLAMP , IDCODE and HIGHZ instructions I Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT I Power up 3-STATE for hot insert I Member of Fairchild’s SCAN Products Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description SCAN182373ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Pin Names Description AI(0–8), BI(0–8) Data Inputs ALE, BLE Latch Enable Inputs AOE 1, BOE1 3-STATE Output Enable Inputs AO (0–8), BO(0–8) 3-STATE Latch Outputs

www.fairchildsemi.com 2 SCAN182373A Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO 0 = Previous AO before H-to-L transition of ALE BO 0 = Previous BO before H-to-L transition of BLE † = Inactive-to-active transition must occur to enable outputs upon power-up. Functional Description The SCAN182373A consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI (0–8) or BI(0–8)) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW tran- sition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable (AOE 1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the stan- dard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs AO (0–8) ALE †AOE 1 AI (0–8) XHXZ HLLL HLHH LLX A O 0 Inputs BO (0–8) BLE †BOE 1 BI (0–8) XHXZ HLLL HLHH LLX B O 0

3 www.fairchildsemi.com SCAN182373A Block Diagrams Byte-A Tap Controller Byte-B Note: BSR stands for Boundary Scan Register.

www.fairchildsemi.com 4 SCAN182373A Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. Scan cell TYPE 1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 SCAN182373A Product IDCODE (32-Bit Code per IEEE 1149.1) The INSTRUCTION register is an 8-bit register which cap- tures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition Scan Cell TYPE1 Scan Cell TYPE2 Version Entity Part Manufacturer Required by Number ID 1149.1 0000 111111 0000001000 00000001111 1 MSB LSB MSB → LSB Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGH-Z

01000001 SAMPLE-IN

01000010 SAMPLE-OUT

00100010 EXTEST-OUT

10101010 IDCODE

11111111 BYPASS

5 www.fairchildsemi.com SCAN182373A BOUNDARY-SCAN Register Scan Chain Definition (42 Bits in Length)

www.fairchildsemi.com 6 SCAN182373A Input BOUNDARY-SCAN Register Scan Chain Definition (22 Bits in Length) When Sample In is Active

7 www.fairchildsemi.com SCAN182373A Output BOUNDARY-SCAN Register Scan Chain Definition (20 Bits in Length) When Sample Out and Extent Out are Active

www.fairchildsemi.com 8 SCAN182373A BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type

41 AOE 1 3 Input TYPE1

40 ALE 54 Input TYPE1

39 AOE Internal TYPE2

38 BOE

37 BLE 31 Input TYPE1

36 BOE Internal TYPE2

34 AI 1 53 Input TYPE1

33 AI 2 52 Input TYPE1

32 AI 3 50 Input TYPE1

31 AI 4 49 Input TYPE1

30 AI 5 47 Input TYPE1

29 AI 6 46 Input TYPE1

28 AI 7 44 Input TYPE1

27 AI 8 43 Input TYPE1

26 BI 0 42 Input TYPE1

25 BI 1 41 Input TYPE1

24 BI 2 39 Input TYPE1

23 BI 3 38 Input TYPE1

22 BI 4 36 Input TYPE1

21 BI 5 35 Input TYPE1

20 BI 6 33 Input TYPE1

19 BI 7 32 Input TYPE1

18 BI 8 30 Input TYPE1

17 AO 0 2 Output TYPE2

16 AO 1 4 Output TYPE2

15 AO 2 5 Output TYPE2

14 AO 3 7 Output TYPE2

13 AO 4 8 Output TYPE2

12 AO 5 10 Output TYPE2

11 AO 6 11 Output TYPE2

10 AO 7 13 Output TYPE2

9 www.fairchildsemi.com SCAN182373A Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit of current limit is sufficient to protect inputs. Note 3: Guaranteed not tested. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output in Disabled or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Twice the Rated I OL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V ESD (HBM) Min 2000V Free Air Ambient Temperature −40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate ( ∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter VCC Min Typ Max Units Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage Output Min −1.2 V I IN = −18 mA VOH HIGH Voltage Min 2.5 V I OH = −3 mA Min 2.0 V I OH = −32 mA VOL Output LOW Voltage Min 0.8 V I OL = 15 mA IIH Input HIGH Current All Others Max 5 µAV IN = 2.7V (Note 3) Max 5 µAV IN = VCC TMS, TDI Max 5 µAV IN = VCC IBVI Input HIGH Current Breakdown Test Max 7 µAV IN = 7.0V IBVIT Input HIGH Current Breakdown Test (I/O) Max 100 µAV IN = 5.5V IIL Input LOW Current All Others Max −5 µAV IN = 0.5V (Note 3) Max −5 µAV IN = 0.0V TMS, TDI Max −385 µAV IN = 0.0V VID Input Leakage Test 0.0 4.75 V I ID = 1.9 µA All Other Pins Grounded IIH + IOZH Output Leakage Current Max 50 µAV OUT = 2.7V IIL + LOZL Output Leakage Current Max −50 V OUT = 0.5V IOZH Output Leakage Current Max 50 µAV OUT = 2.7V IOZL Output Leakage Current Max −50 µAV OUT = 0.5V IOS Output Short-Circuit Current Max −100 −275 mA V OUT = 0.0V ICEX Output HIGH Leakage Current Max 50 µAV OUT = VCC IZZ Bus Drainage Test 0.0 100 µAV OUT = 5.5V All Others Grounded ICCH Power Supply Current Max 250 µAV OUT = VCC ; TDI, TMS = VCC Max 1.0 mA V OUT = VCC ; TDI, TMS = GND ICCL Power Supply Current Max 65 mA V OUT = LOW; TDI, TMS = VCC Max 65.8 mA V OUT = LOW; TDI, TMS = GND ICCZ Power Supply Current Max 250 µA TDI, TMS = VCC Max 1.0 mA TDI, TMS = GND ICCT Additional ICC /Input All Other Inputs Max 2.9 mA V IN = VCC −2.1V TDI, TMS Inputs Max 3 mA V IN = VCC −2.1V ICCD Dynamic ICC No Load Max 0.2 mA/ Outputs Open MHz One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 10 SCAN182373A Normal Operation: Note 4: Voltage Range 5.0V ± 0.5V AC Operating Requirements Normal Operation: Note 5: Voltage Range 5.0V ±0.5V Scan Test Operation: Note 6: Voltage Range 5.0V ± 0.5V Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 4) Min Typ Max tPLH Propagation Delay 5.0 1.2 3.7 6.5 ns tPHL D to Q 2.0 4.5 7.4 tPLH Propagation Delay 5.0 1.3 4.1 7.4 ns tPHL LE to Q 1.8 4.5 7.3 tPLZ Disable Time 5.0 1.6 4.9 9.0 ns tPHZ 1.8 6.0 10.7 tPZL Enable Time 5.0 1.6 6.0 9.5 ns tPZH 1.0 5.0 9.3 Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 5) Guaranteed Minimum tS Setup Time, H or L 5.0 1.7 ns Data to LE t H Hold Time, H or L 5.0 1.6 ns LE to Data tW LE Pulse Width 5.0 2.3 ns Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 6) Min Typ Max tPLH Propagation Delay 5.0 3.6 5.8 8.6 ns tPHL TCK to TDO 4.8 7.4 10.6 tPLZ Disable Time 5.0 2.7 5.6 9.0 ns tPHZ TCK to TDO 4.0 7.1 10.9 tPZL Enable Time 5.0 5.2 8.6 12.5 ns tPZH TCK to TDO 3.6 6.6 10.1 tPLH Propagation Delay 3.9 6.4 9.5 ns tPHL TCK to Data Out during Update-DR State 5.0 5.1 8.0 11.6 tPLH Propagation Delay 4.7 7.7 11.3 ns tPHL TCK to Data Out during Update-IR State 5.0 5.7 9.1 13.1 tPLH Propagation Delay 5.0 5.5 9.2 13.6 ns tPHL TCK to Data Out during Test Logic Reset State 6.7 10.7 15.6 tPLZ Disable Time 4.1 7.7 12.1 ns tPHZ TCK to Data Out during Update-DR State 5.0 4.7 8.4 12.7 tPLZ Disable Time 4.2 8.3 13.5 ns tPHZ TCK to Data Out during Update-IR State 5.0 4.7 9.0 14.0 tPLZ Disable Time 5.0 5.5 10.1 15.6 ns tPHZ TCK to Data Out during Test Logic Reset State 6.3 10.8 16.2 tPZL Enable Time 5.8 9.6 14.2 ns tPZH TCK to Data Out during Update-DR State 5.0 4.3 7.7 11.7 tPZL Enable Time 6.1 11.0 16.0 ns tPZH TCK to Data Out during Update-IR State 5.0 4.7 9.0 13.7 tPZL Enable Time 5.0 7.3 12.5 18.3 ns tPZH TCK to Data Out during Test Logic Reset State 5.8 10.5 15.8

11 www.fairchildsemi.com SCAN182373A AC Operating Requirements Scan Test Operation: Note 7: Voltage Range 5.0V ± 0.5V. Note 8: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 9: Timing pertains to BSR 38 and 41 only. Note 10: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 11: Timing pertains to BSR 37 and 40 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Capacitance Note 12: C OUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012 Symbol Parameter VCC T A = −40°C to +85°C Units(V) C L = 50 pF (Note 7) Guaranteed Minimum tS Setup Time, 5.0 2.7 ns Data to TCK (Note 8) tH Hold Time, 5.0 2.4 ns Data to TCK (Note 8) tS Setup Time, H or L 5.0 5.1 ns AOE 1, BOE 1 to TCK (Note 9) tH Hold Time, H or L 5.0 1.8 ns TCK to AOE 1, BOE 1 (Note 9) tS Setup Time, H or L 5.0 3.5 ns Internal AOE, BOE, to TCK (Note 10) tH Hold Time, H or L TCK to Internal 5.0 1.8 ns AOE, BOE (Note 10) t S Setup Time 5.0 5.1 ns ALE, BLE (Note 11) to TCK tH Hold Time 5.0 1.8 ns TCK to ALE, BLE (Note 11) tS Setup Time, H or L 5.0 7.9 ns TMS to TCK tH Hold Time, H or L 5.0 1.8 ns TCK to TMS tS Setup Time, H or L 5.0 6.0 ns TDI to TCK tH Hold Time, H or L 5.0 3.0 ns TCK to TDI tW Pulse Width TCK H 5.0 10.3 ns L1 0 . 3 fMAX Maximum TCK Clock Frequency 5.0 50 MHz tPU Wait Time, Power Up to TCK 5.0 100 ns tDN Power Down Delay 0.0 100 ms Symbol Parameter Typ Units Conditions, T A = 25°C C IN Input Capacitance 5.8 pF V CC = 0.0V C OUT Output Capacitance (Note 12) 13.8 pF V CC = 5.0V

www.fairchildsemi.com 12 SCAN182373A Transparent Latch with 25Ω Series Resistor Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com