SCAN182245A NSC | Alldatasheet
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Technical content
Features
Y High performance BiCMOS technology Y 25X series resistors in outputs eliminate the need for external terminating resistors Y Dual output enable control signals Y TRI-STATEÉ outputs for bus-oriented applications Y 25 mil pitch SSOP (Shrink Small Outline Package) Y IEEE 1149.1 (JTAG) Compliant Y Includes CLAMP, IDCODE and HIGHZ instructions Y Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT Y Power Up TRI-STATE for hot insert Y Member of National’s SCAN Products Connection Diagram TL/F/11657–1 Pin Names Description A1(0–8) Side A1 Inputs or TRI-STATE Outputs B1(0–8) Side B1 Inputs or TRI-STATE Outputs A2(0–8) Side A2 Inputs or TRI-STATE Outputs B2(0–8) Side B2 Inputs or TRI-STATE Outputs G1,G 2 Output Enable Pins (Active Low) DIR1, DIR2 Direction of Data Flow Pins Order Number Description SCAN182245ASSC SSOP in Tubes SCAN182245ASSCX SSOP Tape and Reel SCAN182245AFMQB Flatpak MilitaryTRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Inputs A1(0–8) B1(0–8) ²G1 DIR1 LL H w H LL L w L LH H x H LH L x L HX Z Z Inputs A2(0–8) B2(0–8) ²G2 DIR2 LL H w H LL L w L LH H x H LH L x L HX Z Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance ² e Inactive-to-Active transition must occur to enable outputs upon power-up. Functional Description The SCAN182245A consists of two sets of nine non-invert- ing bidirectional buffers with TRI-STATE outputs and is in- tended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B ports to A ports, when HIGH enables data from A ports to B ports. The Output Enable pins (G1 and G2 ) when HIGH disables both A and B ports by placing them in a high impedance condition. Block Diagrams A1, B1, G1 and DIR1 TL/F/11657–2 Note: BSR stands for Boundary Scan Register. http:/ /www.national.com 2
Block Diagrams (Continued) Tap Controller TL/F/11657–18 A2, B2, G2 and DIR2 TL/F/11657–3 Note: BSR stands for Boundary Scan Register. http:/ /www.national.com3
Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. (See IEEE Standard 1149.1 Figure 10-11 for a further description of scan cell TYPE1 and Figure 10-12 for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage iden- tical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 TL/F/11657–17 SCAN182245A Product IDCODE (32-Bit Code per IEEE 1149.1) Version Entity Part Manufacturer Required by Number ID 1149.1 0000 111111 0000000000 00000001111 1 MSB LSB The INSTRUCTION register is an 8-bit register which cap- tures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The se- quence of: CAPTURE-IR x EXIT1-IR x UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition TL/F/11657–10 MSB x LSB Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
01000001 SAMPLE-IN
01000010 SAMPLE-OUT
00100010 EXTEST-OUT
10101010 IDCODE
11111111 BYPASS
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Description of BOUNDARY-SCAN Circuitry (Continued) Scan Cell TYPE1 TL/F/11657–11 Scan Cell TYPE2 TL/F/11657–12 http:/ /www.national.com5
Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Scan Chain Definition (80 Bits in Length) TL/F/11657–32 http:/ /www.national.com 6
Description of BOUNDARY-SCAN Circuitry (Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample In is Active TL/F/11657–33 http:/ /www.national.com7
Description of BOUNDARY-SCAN Circuitry (Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample Out and EXTEST-Out are Active TL/F/11657–34 http:/ /www.national.com 8
Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type
79 DIR1 3 Input TYPE1
78 G1 54 Input TYPE1
77 AOE 1 Internal TYPE2
76 BOE 1 Internal TYPE2
75 DIR2 26 Input TYPE1
31 Input TYPE1
73 AOE 2 Internal TYPE2
72 BOE 2 Internal TYPE2
71 A1 0 55 Input TYPE1
A1–in
70 A1 1 53 Input TYPE1
69 A1 2 52 Input TYPE1
68 A1 3 50 Input TYPE1
67 A1 4 49 Input TYPE1
66 A1 5 47 Input TYPE1
65 A1 6 46 Input TYPE1
64 A1 7 44 Input TYPE1
63 A1 8 43 Input TYPE1
62 A2 0 42 Input TYPE1
A2–in
61 A2 1 41 Input TYPE1
60 A2 2 39 Input TYPE1
59 A2 3 38 Input TYPE1
58 A2 4 36 Input TYPE1
57 A2 5 35 Input TYPE1
56 A2 6 33 Input TYPE1
55 A2 7 32 Input TYPE1
54 A2 8 30 Input TYPE1
53 B1 0 2 Output TYPE2
B1–out
52 B1 1 4 Output TYPE2
51 B1 2 5 Output TYPE2
50 B1 3 7 Output TYPE2
49 B1 4 8 Output TYPE2
48 B1 5 10 Output TYPE2
47 B1 6 11 Output TYPE2
46 B1 7 13 Output TYPE2
45 B1 8 14 Output TYPE2
44 B2 0 15 Output TYPE2
B2–out
43 B2 1 16 Output TYPE2
42 B2 2 18 Output TYPE2
41 B2 3 19 Output TYPE2
40 B2 4 21 Output TYPE2
39 B2 5 22 Output TYPE2
38 B2 6 24 Output TYPE2
37 B2 7 25 Output TYPE2
36 B2 8 27 Output TYPE2
35 B1 0 2 Input TYPE1
B1–in
34 B1 1 4 Input TYPE1
33 B1 2 5 Input TYPE1
32 B1 3 7 Input TYPE1
31 B1 4 8 Input TYPE1
30 B1 5 10 Input TYPE1
29 B1 6 11 Input TYPE1
28 B1 7 13 Input TYPE1
27 B1 8 14 Input TYPE1
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Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Definition Index (Continued) Bit No. Pin Name Pin No. Pin Type Scan Cell Type
26 B2 0 15 Input TYPE1
B2–in
25 B2 1 16 Input TYPE1
24 B2 2 18 Input TYPE1
23 B2 3 19 Input TYPE1
22 B2 4 21 Input TYPE1
21 B2 5 22 Input TYPE1
20 B2 6 24 Input TYPE1
19 B2 7 25 Input TYPE1
18 B2 8 27 Input TYPE1
17 A1 0 55 Output TYPE2
A1–out
16 A1 1 53 Output TYPE2
15 A1 2 52 Output TYPE2
14 A1 3 50 Output TYPE2
13 A1 4 49 Output TYPE2
12 A1 5 47 Output TYPE2
11 A1 6 46 Output TYPE2
10 A1 7 44 Output TYPE2
A2–out 7A 2 1 41 Output TYPE2 6A 2 2 39 Output TYPE2 5A 2 3 38 Output TYPE2 4A 2 4 36 Output TYPE2 3A 2 5 35 Output TYPE2 2A 2 6 33 Output TYPE2 1A 2 7 32 Output TYPE2 0A 2 8 30 Output TYPE2 http:/ /www.national.com 10
SCAN ABT Live Insertion and Power Cycling Characteristics SCAN ABT is intended to serve in Live Insertion backplane applications. It provides 2nd Level Isolation 1 which indicates that while external circuitry to control the output enable pin is unnecessary, there may be a need to implement differen- tial length backplane connector pins for V CC and GND. As well, pre-bias circuitry for backplane pins may be necessary to avoid capacitive loading effects during live insertion. SCAN ABT provides control of output enable pins during power cycling via the circuit in Figure A . It essentially con- trols the G n pin until V CC reaches a known level. During power-up , when V CC ramps through the 0.0V to 0.7V range, all internal device circuitry is inactive, leaving output and I/O pins of the device in high impedance. From approxi- mately 0.8V to 1.8V V CC, the Power-On-Reset circuitry, (POR), in Figure A becomes active and maintains device high impedance mode. The POR does this by providing a low from its output that resets the flip-flop The output, Q ,o f the flip-flop then goes high and disables the NOR gate from an incidental low input on the G n pin. After 1.8V V CC, the POR circuitry becomes inactive and ceases to control the flip-flop. To bring the device out of high impedance, the G n input must receive an inactive-to-active transition, a high-to- low transition on G n in this case to change the state of the flip-flop. With a low on the Q output of the flip-flop, the NOR gate is free to allow propagation of a G n signal. During power-down , the Power-On-Reset circuitry will be- come active and reset the flip-flop at approximately 1.8V V CC. Again, the Q output of the flip-flop returns to a high and disables the NOR gate from inputs from the G n pin. The device will then remain in high impedance for the remaining ramp down from 1.8V to 0.0V V CC. Some suggestions to help the designer with live insertion issues: # The G n pin can float during power-up until the Power-On- Reset circuitry becomes inactive. # The G n pin can float on power-down only after the Pow- er-On-Reset has become active. The description of the functionality of the Power-On-Reset circuitry can best be described in the diagram of Figure B . TL/F/11657–19 FIGURE A TL/F/11657–20 FIGURE B 1Section 7, ‘‘Design Consideration for Fault Tolerant Backplanes’’, Application Note AN-881. SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices. http:/ /www.national.com11
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias Ceramic b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State b0.5V to a5.5V in the HIGH State b0.5V to V CC Current Applied to Output in LOW State (Max) Twice the Rated I OL (mA) DC Latchup Source Current Commercial b500 mA Military b300 mA Over Voltage Latchup (I/O) 10V ESD (HBM) Min. 2000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial b40§Ct o a85§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Minimum Input Edge Rate ( DV/Dt) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter V CC Min Typ Max Units Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage Min b1.2 V I IN eb 18 mA VOH Output HIGH Voltage Min 2.5 V I OH eb 3m A Mil Min 2.0 V I OH eb 24 mA Comm Min 2.0 V I OH eb 32 mA VOL Output LOW Voltage Mil Min 0.8 V I OL e 12 mA Comm Min 0.8 V I OL e 15 mA IIH Input HIGH Current All Others Max 5 mAV IN e 2.7V (Note 1) Max 5 mAV IN e VCC TMS, TDI Max 5 mAV IN e VCC IBVI Input HIGH Current Max 7 mA VIN e 7.0V Breakdown Test IBVIT Input HIGH Current Max 100 mA VIN e 5.5V Breakdown Test (I/O) IIL Input LOW Current All Others Max b5 mAV IN e 0.5V (Note 1) Max b5 mAV IN e 0.0V TMS, TDI Max b385 mAV IN e 0.0V VID Input Leakage Test 0.0 4.75 V IID e 1.9 mA All Other Pins Grounded IIH a IOZH Output Leakage Current Max 50 mAV OUT e 2.7V IIL a IOZL Output Leakage Current Max b50 mAV OUT e 0.5V IOZH Output Leakage Current Max 50 mAV OUT e 2.7V IOZL Output Leakage Current Max b50 mAV OUT e 0.5V Note 1: Guaranteed not tested. http:/ /www.national.com 12
Symbol Parameter V CC Min Typ Max Units Conditions IOS Output Short-Circuit Current Max b100 b275 mA V OUT e 0.0V ICEX Output HIGH Leakage Current Max 50 mAV OUT e VCC IZZ Bus Drainage Test 0.0 100 mA VOUT e 5.5V All Others GND ICCH Power Supply Current Max 250 mAV OUT e VCC; TDI, TMS e VCC Max 1.0 mA V OUT e VCC; TDI, TMS e GND ICCL Power Supply Current Max 65 mA V OUT e LOW; TDI, TMS e VCC Max 65.8 mA V OUT e LOW; TDI, TMS e GND ICCZ Power Supply Current Max 250 mA TDI, TMS e VCC Max 1.0 mA TDI, TMS e GND ICCT Additional I CC/Input All Other Inputs Max 2.9 mA V IN e VCC b 2.1V TDI, TMS inputs Max 3 mA V IN e VCC b 2.1V ICCD Dynamic I CC No Load Max 0.2 mA/ Outputs Open MHz One Bit Toggling, 50% Duty Cycle Symbol Parameter VCC* (V) Military Commercial UnitsTA eb 55§Ct o a125§CT A eb 40§Ct o a85§C CL e 50 pF C L e 50 pF Min Typ Max Min Typ Max *Voltage Range 5.0V g0.5V http:/ /www.national.com13
Symbol Parameter VCC* (V) Military Commercial UnitsTA eb 55§Ct o a125§CT A eb 40§Ct o a85§C CL e 50 pF C L e 50 pF Min Typ Max Min Typ Max during Update-DR State during Update-IR State during Test Logic Reset State during Update-DR State during Update-IR State during Test Logic Reset State during Update-DR State during Update-IR State during Test Logic Reset State *Voltage Range 5.0V g0.5V All Propagation Delays involving TCK are measured from the falling edge of TCK. http:/ /www.national.com 14
AC Operating Requirements Scan Test Operation Symbol Parameter VCC* (V) Military Commercial UnitsTA eb 55§Ct o a125§CT A eb 40§Ct o a85§C CL e 50 pF C L e 50 pF Guaranteed Minimum tS Setup Time 5.0 4.8 nsData to TCK (Note 1) tH Hold Time 5.0 2.5 nsData to TCK (Note 1) tS Setup Time, H or L 5.0 4.1 nsG1,G 2 to TCK (Note 2) tH Hold Time, H or L 5.0 1.7 nsTCK to G1 ,G 2 (Note 2) tS Setup Time, H or L 5.0 4.2 nsDIR1, DIR2 to TCK (Note 4) tH Hold Time, H or L 5.0 2.3 nsTCK to DIR1, DIR2 (Note 4) tS Setup Time 5.0 3.8 nsInternal OE to TCK (Note 3) tH Hold Time, H or L 5.0 2.3 nsTCK to Internal OE (Note 3) tS Setup Time, H or L 5.0 8.7 nsTMS to TCK tH Hold Time, H or L 5.0 1.5 nsTCK to TMS tS Setup Time, H or L 5.0 6.7 nsTDI to TCK tH Hold Time, H or L 5.0 5.0 nsTCK to TDI tW Pulse Width TCK H 5.0 10.2 nsL 8.5 fmax Maximum TCK 5.0 50 MHzClock Frequency tPU Wait Time, 5.0 100 nsPower Up to TCK tDN Power Down Delay 0.0 100 ms *Voltage Range 5.0V g0.5V All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note 1: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 2: Timing pertains to BSR 74 and 78 only. Note 3: Timing pertains to BSR 72, 73, 76 and 77 only. Note 4: Timing pertains to BSR 75 and 79 only. Capacitance Symbol Parameter Typ Units Conditions, T A e 25§C CIN Input Capacitance 5.9 pF V CC e 0.0V (G n, DIR n) CI/O (Note 1) Output Capacitance 13.7 pF V CC e 5.0V (A n,B n) Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012. http:/ /www.national.com15
Ordering Information
Serially Controlled Access Network Special Variations X e Tape and Reel18-Bit Logic QB e Military grade device with environmental and burn-inFunction Type processing. Technology Designator Temperature RangeT e TTL Input TTL Output CMOS Device C e Commercial ( b40§Ct oC e CMOS Input/Output CMOS Device a85§C)B e Bipolar TTL Device M e Military ( b55§Ct o a125§C)E e ECL Device A e BiCMOS Device Package CodeF e TTL Input/CMOS Output CMOS Device SS e 25 mil Pitch (JEDEC) SSOP F e 25 mil Pitch Ceramic Flatpak http:/ /www.national.com 16
Physical Dimensions inches (millimeters) 56-Lead SSOP (0.300 × Wide) (SS) Order Number SCAN182245ASSC or SCAN182245ASSCX http:/ /www.national.com17
SCAN182245A Transceiver with 25 X Series Resistor Outputs Physical Dimensions inches (millimeters) (Continued) 56-Lead Ceramic Flatpak (F) Order Number SCAN182245AFMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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