SCAN182245A FAIRCHILD | Alldatasheet

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I High performance BiCMOS technology I 25Ω series resistors in outputs eliminate the need for external terminating resistors I Dual output enable control signals I 3-STATE outputs for bus-oriented applications I 25 mil pitch SSOP (Shrink Small Outline Package) I IEEE 1149.1 (JTAG) Compliant I Includes CLAMP , IDCODE and HIGHZ instructions I Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT I Power Up 3-STATE for hot insert I Member of Fairchild’s SCAN Products Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description SCAN182245ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide SCAN182245AMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description A1(0–8) Side A1 Inputs or 3-STATE Outputs B1(0–8) Side B1 Inputs or 3-STATE Outputs A2(0–8) Side A2 Inputs or 3-STATE Outputs B2(0–8) Side B2 Inputs or 3-STATE Outputs G1 , G2 Output Enable Pins (Active LOW) DIR1, DIR2 Direction of Data Flow Pins

www.fairchildsemi.com 2 SCAN182245A Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Note 1: Inactive-to-Active transition must occur to enable outputs upon power-up. Functional Description The SCAN182245A consists of two sets of nine non-invert- ing bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, when HIGH enables data from A Ports to B Ports. The Out- put Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition. Block Diagrams A1, B1, G1 and DIR1 Note: BSR stands for Boundary Scan Register. A2, B2, G2 and DIR2 Note: BSR stands for Boundary Scan Register. Tap Controller Inputs (Note 1) DIR1 LLH ← H LLL ← L LHH → H LHL → L HXZZ Inputs (Note 1) DIR2 LLH ← H LLL ← L LHH → H LHL → L HXZZ

3 www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 SCAN182245A Product IDCODE (32-Bit Code per IEEE 1149.1) The INSTRUCTION register is an 8-bit register which cap- tures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR → EXIT1-IR → UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition MSB → LSB Scan Cell TYPE1 Scan Cell TYPE2 Versio n Entity Part Manufacture r Required Number ID by 1149.1 0000 111111 000000000 00000001111 1 MSB MSB Instruction Code Instruction

00000000 EXTEST

10000001 SAMPLE/PRELOAD

10000010 CLAMP

00000011 HIGH-Z

01000001 SAMPLE-IN

01000010 SAMPLE-OUT

00100010 EXTEST-OUT

10101010 IDCODE

11111111 BYPASS

www.fairchildsemi.com 4 SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Scan Chain Definition (80 Bits in Length)

5 www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample In is Active

www.fairchildsemi.com 6 SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample Out and EXTEST-Out are Active

7 www.fairchildsemi.com SCAN182245A Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type Bit No. Pin Name Pin No. Pin Type Scan Cell Type

79 DIR1 3 Input TYPE1

35 B10 2 Input TYPE1

B1–in

78 G1 54 Input TYPE1 34 B1 1 4 Input TYPE1

77 AOE 1 Internal TYPE2 33 B1 2 5 Input TYPE1

76 BOE 1 Internal TYPE2 32 B1 3 7 Input TYPE1

75 DIR2 26 Input TYPE1 31 B1 4 8 Input TYPE1

74 G2 31 Input TYPE1 30 B1 5 10 Input TYPE1

73 AOE 2 Internal TYPE2 29 B1 6 11 Input TYPE1

72 BOE 2 Internal TYPE2 28 B1 7 13 Input TYPE1

71 A10 55 Input TYPE1

A1–in

27 B18 14 Input TYPE1

70 A11 53 Input TYPE1 26 B2 0 15 Input TYPE1

B2–in

69 A12 52 Input TYPE1 25 B2 1 16 Input TYPE1

68 A13 50 Input TYPE1 24 B2 2 18 Input TYPE1

67 A14 49 Input TYPE1 23 B2 3 19 Input TYPE1

66 A15 47 Input TYPE1 22 B2 4 21 Input TYPE1

65 A16 46 Input TYPE1 21 B2 5 22 Input TYPE1

64 A17 44 Input TYPE1 20 B2 6 24 Input TYPE1

63 A18 43 Input TYPE1 19 B2 7 25 Input TYPE1

62 A20 42 Input TYPE1

A2–in

18 B28 27 Input TYPE1

61 A21 41 Input TYPE1 17 A1 0 55 Output TYPE2

A1–out

60 A22 39 Input TYPE1 16 A1 1 53 Output TYPE2

59 A23 38 Input TYPE1 15 A1 2 52 Output TYPE2

58 A24 36 Input TYPE1 14 A1 3 50 Output TYPE2

57 A25 35 Input TYPE1 13 A1 4 49 Output TYPE2

56 A26 33 Input TYPE1 12 A1 5 47 Output TYPE2

55 A27 32 Input TYPE1 11 A1 6 46 Output TYPE2

54 A28 30 Input TYPE1 10 A1 7 44 Output TYPE2

53 B10 2 Output TYPE2

B1–out 9A 18 43 Output TYPE2

52 B11 4 Output TYPE2 8 A2 0 42 Output TYPE2

A2–out

51 B12 5 Output TYPE2 7 A2 1 41 Output TYPE2

50 B13 7 Output TYPE2 6 A2 2 39 Output TYPE2

49 B14 8 Output TYPE2 5 A2 3 38 Output TYPE2

48 B15 10 Output TYPE2 4 A2 4 36 Output TYPE2

47 B16 11 Output TYPE2 3 A2 5 35 Output TYPE2

46 B17 13 Output TYPE2 2 A2 6 33 Output TYPE2

45 B18 14 Output TYPE2 1 A2 7 32 Output TYPE2

44 B20 15 Output TYPE2

B2–out 0A 28 30 Output TYPE2

43 B21 16 Output TYPE2

42 B22 18 Output TYPE2

41 B23 19 Output TYPE2

40 B24 21 Output TYPE2

39 B25 22 Output TYPE2

38 B26 24 Output TYPE2

37 B27 25 Output TYPE2

36 B28 27 Output TYPE2

9 www.fairchildsemi.com SCAN182245A Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Note 4: Guaranteed not tested. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Twice the Rated I OL (mA) DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V ESD (HBM) Min. 2000V Free Air Ambient Temperature −40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate ( ∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter VCC Min Typ Max Units Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage Min −1.2 V I IN = −18 mA VOH Output HIGH Voltage Min 2.5 V I OH = −3 mA Min 2.0 V I OH = −32 mA VOL Output LOW Voltage Min 0.8 V I OL = 15 mA IIH Input HIGH Current All Others Max 5 µAV IN = 2.7V (Note 4) Max 5 µAV IN = VCC TMS, TDI Max 5 µAV IN = VCC IBVI Input HIGH Current Breakdown Test Max 7 µAV IN = 7.0V IBVIT Input HIGH Current Breakdown Test (I/O) Max 100 µAV IN = 5.5V IIL Input LOW Current All Others Max −5 µAV IN = 0.5V (Note 4) Max −5 µAV IN = 0.0V TMS, TDI Max −385 µAV IN = 0.0V VID Input Leakage Test 0.0 4.75 V I ID = 1.9 µA All Other Pins Grounded IIH + IOZH Output Leakage Current Max 50 µAV OUT = 2.7V IIL + IOZL Output Leakage Current Max −50 µAV OUT = 0.5V IOZH Output Leakage Current Max 50 µAV OUT = 2.7V IOZL Output Leakage Current Max −50 µAV OUT = 0.5V IOS Output Short-Circuit Current Max −100 −275 mA V OUT = 0.0V ICEX Output HIGH Leakage Current Max 50 µAV OUT = VCC IZZ Bus Drainage Test 0.0 100 µAV OUT = 5.5V, All Others GND ICCH Power Supply Current Max 250 µAV OUT = VCC ; TDI, TMS = VCC Max 1.0 mA V OUT = VCC ; TDI, TMS = GND ICCL Power Supply Current Max mA V OUT = LOW; TDI, TMS = VCC Max 65.8 mA V OUT = LOW; TDI, TMS = GND ICCZ Power Supply Current Max 250 µA TDI, TMS = VCC Max 1.0 mA TDI, TMS = GND ICCT Additional ICC /Input All Other Inputs Max 2.9 mA V IN = VCC − 2.1V TDI, TMS inputs Max 3 mA V IN = VCC − 2.1V ICCD Dynamic ICC No Load Max 0.2 mA/ Outputs Open MHz One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 10 SCAN182245A Normal Operation: Note 5: Voltage Range 5.0V ± 0.5V Scan Test Operation Note 6: Voltage Range 5.0V ± 0.5V Note: All Propagation Delays involving TCK are measured from the falling edge of TCK. Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 5) Min Typ Max tPLH tPHL Propagation Delay 5.0 1.0 3.1 5.2 ns A to B, B to A 1.5 4.4 6.5 tPLZ Disable Time 5.0 1.5 4.8 8.6 ns tPHZ 1.5 5.2 8.9 tPZL Enable Time 5.0 1.5 5.5 9.1 ns tPZH 1.5 4.6 8.2 Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 6) Min Typ Max tPLH tPHL Propagation Delay 5.0 2.9 6.1 10.2 ns TCK to TDO 4.2 7.7 12.1 tPLZ Disable Time 5.0 2.1 5.9 10.7 ns tPHZ TCK to TDO 3.3 7.4 12.5 tPZL tPZH Enable Time 5.0 4.6 8.7 13.7 ns TCK to TDO 2.8 6.8 11.5 tPLH Propagation Delay 5.0 2.8 6.3 10.7 ns tPHL TCK to Data Out during Update-DR State 4.5 8.2 13.0 tPLH Propagation Delay 5.0 3.3 7.2 12.2 ns tPHL TCK to Data Out during Update-IR State 5.0 9.3 14.8 tPLH Propagation Delay 5.0 3.7 8.4 14.0 ns tPHL TCK to Data Out during Test Logic Reset State 5.7 10.8 17.2 tPLZ Disable Time 5.0 2.8 7.6 13.9 ns tPHZ TCK to Data Out during Update-DR State 3.5 8.4 14.5 tPLZ Disable Time 5.0 3.6 8.7 15.1 ns tPHZ TCK to Data Out during Update-IR State 3.8 9.2 15.9 tPLZ Disable Time 5.0 4.0 9.8 17.1 ns tPHZ TCK to Data Out during Test Logic Reset State 4.2 9.9 16.6 tPZL Enable Time 5.0 4.4 9.3 15.5 ns tPZH TCK to Data Out during Update-DR State 3.0 7.5 13.3 tPZL Enable Time 5.0 5.2 10.7 17.4 ns tPZH TCK to Data Out during Update-IR State 3.9 9.0 15.4 tPZL Enable Time 5.0 5.7 12.0 19.8 ns tPZH TCK to Data Out during Test Logic Reset State 3.0 10.2 17.6

11 www.fairchildsemi.com SCAN182245A AC Operating Requirements Scan Test Operation Note 7: Voltage Range 5.0V ± 0.5V Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 9: Timing pertains to BSR 74 and 78 only. Note 10: Timing pertains to BSR 75 and 79 only. Note 11: Timing pertains to BSR 72, 73, 76 and 77 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Capacitance Note 12: C I/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. Symbol Parameter VCC TA = −40°C to +85°C Units(V) C L = 50 pF (Note 7) Guaranteed Minimum tS Setup Time 5.0 4.8 ns Data to TCK (Note 8) tH Hold Time 5.0 2.5 ns Data to TCK (Note 8) tS Setup Time, H or L 5.0 4.1 ns G1 , G2 to TCK (Note 9) tH Hold Time, H or L 5.0 1.7 ns TCK to G1, G2 (Note 9) tS Setup Time, H or L 5.0 4.2 ns DIR1, DIR2 to TCK (Note 10) tH Hold Time, H or L 5.0 2.3 ns TCK to DIR1, DIR2 (Note 10) tS Setup Time 5.0 3.8 ns Internal OE to TCK (Note 11) tH Hold Time, H or L 5.0 2.3 ns TCK to Internal OE (Note 10) tS Setup Time, H or L 5.0 8.7 ns TMS to TCK tH Hold Time, H or L 5.0 1.5 ns TCK to TMS tS Setup Time, H or L 5.0 6.7 ns TDI to TCK tH Hold Time, H or L 5.0 5.0 ns TCK to TDI tW Pulse Width TCK: H 5.0 10.2 ns L8 . 5 fMAX Maximum TCK 5.0 50 MHz Clock Frequency tPU Wait Time, 5.0 100 ns Power Up to TCK tDN Power Down Delay 0.0 100 ms Symbol Parameter Typ Units Conditions, TA = 25°C C IN Input Capacitance 5.9 pF V CC = 0.0V (Gn, DIRn) C I/O (Note 12) Output Capacitance 13.7 pF V CC = 5.0V (An, Bn)

www.fairchildsemi.com 12 SCAN182245A Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

13 www.fairchildsemi.com SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com