SCAN15MB200TSQX/NO.A

SCAN15MB200 TI | Alldatasheet

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www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 Dual1.5Gbps2:1/1:2LVDSMux/BufferwithPre-EmphasisandIEEE1149.6 Check forSamples: SCAN15MB200 1FEATURES DESCRIPTION The SCAN15MB200 isa dual-port2 to1 multiplexer 2• 1.5Gbps Data Rate Per Channel and 1 to 2 repeater/buffer.High-speeddata paths• ConfigurableOff/OnPre-emphasis Drives and flow-throughpinoutminimizeinternaldevicejitterLossy Backplanes and Cables and simplifyboard layout,while pre-emphasis

• LVDS/BLVDS/CML/LVPECL Compatible Inputs, overcomes ISI jittereffectsfrom lossybackplanes and cables.The differentialinputs and outputsLVDS Compatible Outputs interfacetoLVDS orBus LVDS signalssuch as those• Low Output Skew and Jitter on TI's10-,16-,and 18-bitBus LVDS SerDes,orto• On-chip 100Ω Inputand Output Termination CML orLVPECL signals.
• IEEE 1149.1and 1149.6Compliant IntegratedIEEE 1149.1 (JTAG) and 1149.6 circuitry
• 15 kV ESD Protectionon LVDS Inputs/Outputs supports testabilityof both single-ended LVTTL/CMOS and high-speed differentialPCB• Hot Plug Protection interconnects.The 3.3V supply,CMOS process,and• Single3.3VSupply robustI/O ensure high performanceat low power• Industrial-40to+85°C Temperature Range over the entireindustrial-40 to +85°C temperature
• 48-PinWQFN Package range. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

LI_0 SOA_0 SOB_0 SIA_0 SIB_0 MUX_S0 PREA_0 ENA_0 PREB_0 ENB_0 Channel 0 LO_0 PREL_0 IEEE 1149.1 (JTAG) Test Access Port, 1149.6, Fault Insertion TDI TDO TCK TMS TRST ENL_0 SCAN15MB200 SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com Block Diagram Figure1. SCAN15MB200 Block Diagram Pin Descriptions Pin WQFN Pin I/O,Type DescriptionName Number SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ 30 I,LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_0− 29 LVPECL compatible. SIA_1+ 19 I,LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_1− 20 LVPECL compatible. SIB_0+ 28 I,LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_0− 27 LVPECL compatible. SIB_1+ 21 I,LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_1− 22 LVPECL compatible. LINE SIDE DIFFERENTIAL INPUTS LI_0+ 40 I,LVDS Line-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_0− 39 LVPECL compatible. LI_1+ 9 I,LVDS Line-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_1− 10 LVPECL compatible. SWITCH SIDE DIFFERENTIAL OUTPUTS SOA_0+ 34 O, LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_0 − 33 SOA_1+ 15 O, LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_1 − 16 SOB_0+ 32 O, LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_0 − 31 SOB_1+ 17 O, LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_1 − 18 (1) ForinterfacingLVDS outputstoCML orLVPECL compatibleinputs,refertotheapplicationssectionofthisdatasheet(planned). (2) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheSCAN15MB200 device have been optimizedforpoint-to-pointbackplaneand cableapplications.

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www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 Pin Descriptions(continued) Pin WQFN Pin I/O,Type DescriptionName Number LINE SIDE DIFFERENTIAL OUTPUTS LO_0+ 42 O, LVDS Line-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(3)(4). LO_0 − 41 LO_1+ 7 O, LVDS Line-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(3)(4). LO_1 − 8 DIGITAL CONTROL INTERFACE MUX_S0 38 I,LVTTL Mux SelectControlInputs(perchannel)toselectwhichSwitch-sideinput,A orB,ispassed through MUX_S1 11 totheLine-side. PREA_0 26 I,LVTTL Outputpre-emphasiscontrolforSwitch-sideoutputs.Each outputdriveron theSwitchA-sideand B- PREA_1 23 sidehas a separatepintocontrolthepre-emphasison oroff. PREB_0 25 PREB_1 24 PREL_0 44 I,LVTTL Outputpre-emphasiscontrolforLine-sideoutputs.Each outputdriveron theLineA-sideand B-side PREL_1 5 has a separatepintocontrolthepre-emphasison oroff. ENA_0 36 I,LVTTL OutputEnableControlforSwitchA-sideand B-sideoutputs.Each outputdriveron theA-sideand ENA_1 13 B-sidehas a separateenablepin. ENB_0 35 ENB_1 14 ENL_0 45 I,LVTTL OutputEnableControlforThe Line-sideoutputs.Each outputdriveron theLine-sidehas a separate ENL_1 4 enablepin. TDI 2 I,LVTTL TestData InputtosupportIEEE 1149.1features TDO 1 O, LVTTL TestData OutputtosupportIEEE 1149.1features TMS 46 I,LVTTL TestMode SelecttosupportIEEE 1149.1features TCK 47 I,LVTTL TestClocktosupportIEEE 1149.1features TRST 3 I,LVTTL TestResettosupportIEEE 1149.1features POWER VDD 6,12,37, I,Power VDD = 3.3V±0.3V. 43,48 GND See (5) I,Power Ground referenceforLVDS and CMOS circuitry. FortheWQFN package,theDAP isused as theprimaryGND connectiontothedevice.The DAP is theexposed metalcontactatthebottomoftheWQFN-48 package.Itshouldbe connectedtothe groundplanewithatleast4 viasforoptimalAC and thermalperformance. (3) ForinterfacingLVDS outputstoCML orLVPECL compatibleinputs,refertotheapplicationssectionofthisdatasheet(planned). (4) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheSCAN15MB200 device have been optimizedforpoint-to-pointbackplaneand cableapplications. (5) Note thattheDAP on thebacksideoftheWQFN package istheprimaryGND connectionforthedevicewhen usingtheWQFN package. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN15MB200

ENL_0 PREL_0 VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- PREA_1 PREB_1 VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD PREL_1 ENL_1 TRST TDI TDO PREB_0 PREA_0 SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 Channel 0 Channel 1 VDD TCK TMS ENL_0 PREL_0 VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- PREA_1 PREB_1 VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD PREL_1 ENL_1 TRST TDI TDO 12 11 10 9 8 7 6 5 4 3 2 1PREB_0 PREA_0 SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 25 26 27 28 29 30 31 32 33 34 35 36 DAP (GND) SCAN15MB200 SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com Connection Diagram WQFN Top View DAP = GND DirectionalSignalPaths Top View (Refertopinnames forsignalpolarity)

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www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 OUTPUT CHARACTERISTICS The outputcharacteristicsof the SCAN15MB200 have been optimizedforpoint-to-pointbackplaneand cable applications,and arenotintendedformultipointormultidropsignaling. A 100Ω output(source)terminationresistorisincorporatedinthedevicetoeliminatetheneed foran external resistor,providingexcellentdrivecharacteristicsby locatingthe sourceterminationas closeto the outputas physicallypossible. Pre-Emphasis Controls The pre-emphasisisused tocompensate forlongor lossytransmissionmedia.Separatepinsare providedfor each outputto minimizepower consumption.Pre-emphasisis programmable to be offor on per the Pre- emphasisControlTable. PREx_n (1) Output Pre-emphasis 0 0% 1 100% (1) AppliestoPREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1 MultiplexerTruthTable (1)(2) Data Inputs ControlInputs Output SIA_0 SIB_0 MUX_S0 ENL_0 LO_0 X valid 0 1 SIB_0 valid X 1 1 SIA_0 X X X 0 (3) Z (1) Same functionalityforchannel1 (2) X = Don 'tCare Z = HighImpedance (TRI-STATE) (3) When allenableinputsfrombothchannelsareLow, thedevice entersa powerdown mode. Refertotheapplicationssectiontitled TRI-STATE and Powerdown Modes . Repeater/BufferTruthTable (1)(2) Data Input ControlInputs Outputs LI_0 ENA_0 ENB_0 SOA_0 SOB_0 X 0 0 Z (3) Z (3) valid 0 1 Z LI_0 valid 1 0 LI_0 Z valid 1 1 LI_0 LI_0 (1) Same functionalityforchannel1 (2) X = Don 'tCare Z = HighImpedance (TRI-STATE) (3) When allenableinputsfrombothchannelsareLow, thedevice entersa powerdown mode. Refertotheapplicationssectiontitled TRI-STATE and Powerdown Modes . These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN15MB200

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com AbsoluteMaximum Ratings (1) Value Unit SupplyVoltage(VDD ) −0.3Vto+4.0 V CMOS InputVoltage -0.3Vto(VDD +0.3) V LVDS ReceiverInputVoltage(2) -0.3Vto(VDD +0.3) V LVDS DriverOutputVoltage -0.3Vto(VDD +0.3) V LVDS OutputShortCircuitCurrent +40 mA JunctionTemperature +150 °C StorageTemperature −65°C to+150 °C Lead Temperature(Solder,4sec) 260 °C Max Pkg Power Capacity@ 25°C 5.2 W ThermalResistance(θJA) 24 °C/W Package Deratingabove +25°C 41.7 mW/ °C ESD LastPassingVoltage HBM, 1.5kΩ,100pF 8 kV LVDS pinstoGND only 15 kV EIAJ,0Ω,200pF 250 V CDM 1000 V (1) Absolutemaximum ratingsarethosevaluesbeyond whichdamage tothedevicemay occur.The databookspecificationsshouldbe met, withoutexception,toensurethatthesystemdesignisreliableoveritspower supply,temperature,and output/inputloadingvariables.TI does notrecommend operationofproductsoutsideofrecommended operationconditions. (2) VID max < 2.4V Recommended OperatingConditions Min Max Unit SupplyVoltage(VCC ) 3.0 3.6 V InputVoltage(VI) (1) 0 VCC V OutputVoltage(VO ) 0 VCC V OperatingTemperature(TA)Industrial −40 +85 °C (1) VID max < 2.4V ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n, TDI,TDO, TCK, TMS, TRST) VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VDD = VDDMAX −10 +10 µA IIHR HighLevelOutputCurrent PREA_n, PREB_n, PREL_n 40 200 µA IIL Low LevelInputCurrent VIN = VSS ,VDD = VDDMAX −10 +10 µA IILR Low LevelInputCurrent TDI,TMS, TRST -40 -200 µA C IN1 InputCapacitance Any DigitalInputPintoVSS 2.0 pF C OUT1 OutputCapacitance Any DigitalOutputPintoVSS 4.0 pF VCL InputClamp Voltage ICL = −18 mA −1.5 −0.8 V VOH HighLevelOutputVoltage IOH = −12 mA, VDD = 3.0V 2.4 V (TDO) IOH = −100 µA,VDD = 3.0V VDD -0.2 V VOL Low LevelOutputVoltage IOL = 12 mA, VDD = 3.0V 0.5 V (TDO) IOL = 100 µA,VDD = 3.0V 0.2 V IOS OutputShortCircuitCurrent TDO -15 -125 mA IOZ OutputTRI-STATE Current TDO -10 +10 µA (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25°C. They areforreferencepurposes,and arenotproduction-tested.

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www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units LVDS INPUT DC SPECIFICATIONS (SIA±,SIB±,LI±) VTH DifferentialInputHighThreshold(2) VCM = 0.8Vor1.2Vor3.55V, 0 100 mVVDD = 3.6V VTL DifferentialInputLow Threshold(2) VCM = 0.8Vor1.2Vor3.55V, −100 0 mVVDD = 3.6V VID DifferentialInputVoltage VCM = 0.8Vto3.55V,VDD = 3.6V 100 2400 mV VCMR Common Mode VoltageRange VID = 150 mV, VDD = 3.6V 0.05 3.55 V C IN2 InputCapacitance IN+ orIN− toVSS 2.0 pF IIN InputCurrent VIN = 3.6V,VDD = VDDMAX or0V −15 +15 µA VIN = 0V,VDD = VDDMAX or0V −15 +15 µA LVDS OUTPUT DC SPECIFICATIONS (SOA_n ±,SOB_n ±,LO_n ±) VOD DifferentialOutputVoltage, R L istheinternal100Ω between OUT+ 250 360 500 mV0% Pre-emphasis(2) and OUT − ΔVOD Change inVOD between -35 35 mVComplementaryStates VOS OffsetVoltage(3) 1.05 1.22 1.475 V ΔVOS Change inVOS between -35 35 mVComplementaryStates IOS OutputShortCircuitCurrent OUT+ orOUT − ShorttoGND −21 -40 mA C OUT2 OutputCapacitance OUT+ orOUT − toGND when TRI- 4.0 pFSTATE SUPPLY CURRENT (Static) ICC SupplyCurrent Allinputsand outputsenabledand active,terminatedwithdifferentialloadof 225 275 mA 100Ω between OUT+ and OUT-. ICCZ SupplyCurrent-Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 = 0.6 4.0 mAENB_1 = ENL_1 = L SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT DifferentialLow toHighTransition Use an alternating1 and 0 patternat200 170 250 psTime Mb/s,measure between 20% and 80% of VOD .(4) tHLT DifferentialHightoLow Transition 170 250 psTime tPLHD DifferentialLow toHighPropagation Use an alternating1 and 0 patternat200 1.0 2.5 nsDelay Mb/s,measure at50% VOD between inputtooutput.tPHLD DifferentialHightoLow Propagation 1.0 2.5 nsDelay tSKD1 PulseSkew |tPLHD –tPHLD |(4) 25 75 ps tSKCC OutputChanneltoChannelSkew Differenceinpropagationdelay(tPLHD or 50 115 pstPHLD )among alloutputchannels.(4) tJIT Jitter(0% Pre-emphasis)(5) RJ -Alternating1 and 0 at750MHz (6) 1.1 1.5 psrms DJ -K28.5Pattern,1.5Gbps (7) 20 34 psp-p TJ -PRBS 27-1Pattern,1.5Gbps (8) 14 28 psp-p (2) DifferentialoutputvoltageVOD isdefinedas ABS(OUT+ –OUT −).DifferentialinputvoltageVID isdefinedas ABS(IN+–IN−). (3) OutputoffsetvoltageVOS isdefinedas theaverageoftheLVDS single-endedoutputvoltagesatlogichighand logiclowstates. (4) Not Productiontested.Specifiedby statisticalanalysison a sample basisatthetimeofcharacterization. (5) Jitterisnotproductiontested,butspecifiedthroughcharacterizationon a sample basis. (6) Random Jitter,orRJ,ismeasured RMS witha histogramincluding1500 histogramwindow hits.The inputvoltage= VID = 500mV, 50% dutycycleat750MHz, tr = tf= 50ps (20% to80%). (7) DeterministicJitter,orD J,ismeasured toa histogrammean witha sample sizeof350 hits.Stimulusand fixturejitterhas been streamsof(00111110101100000101). (8) TotalJitter,orTJ,ismeasured peak topeak witha histogramincluding3500 window hits.Stimulusand fixturejitterhas been subtracted. The inputvoltage= VID = 500mV, 27-1 PRBS patternat1.5Gbps, tr = tf= 50ps (20% to80%). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN15MB200

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units tON LVDS OutputEnableTime Time fromENA_n, ENB_n, orENL_n to 0.5 1.5 µsOUT ± change fromTRI-STATE toactive. tON2 LVDS OutputEnabletimefrom Time fromENA_n, ENB_n, orENL_n to 10 20 µspowerdown mode OUT ± change fromPowerdown toactive tOFF LVDS OutputDisableTime Time fromENA_n, ENB_n, orENL_n to OUT ± change fromactivetoTRI-STATE 12 ns orpowerdown. SWITCHING CHARACTERISTICS -SCAN FEATURES fMAX Maximum TCK ClockFrequency R L = 500Ω, 25.0 MHz C L = 35 pFtS TDI toTCK, H orL 3.0 ns tH TDI toTCK, H orL 0.5 ns tS TMS toTCK, H orL 3.0 ns tH TMS toTCK, H orL 0.5 ns tW TCK PulseWidth,H orL 10.0 ns tW TRST PulseWidth,L 2.5 ns tREC RecoveryTime,TRST toTCK 2.0 ns

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TOTAL JITTER (ps) TEMPERATURE (° C) -40 1000 -20 20 40 60 80 POWER SUPPLY CURRENT (mA) 350 BIT DATA RATE (Mbps) 0 2000 100 150 200 500 1000 1500 250 300 PRE-EMPHASIS ON PRE-EMPHASIS OFF TOTAL JITTER (ps) BIT DATA RATE (Mbps) 0 2000 500 1000 1500 VCM = 3.0V VCM = 0.25V VCM = 1.2V SCAN15MB200 www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 TypicalPerformance Characteristics WQFN Performance Characteristics Power Supply Current TotalJitter vs. vs. BitData Rate BitData Rate Dynamic power supplycurrentwas measured withallchannelsactiveTotalJittermeasured at0V differentialwhilerunninga PRBS 27-1 and togglingatthebitdatarate.Data patternhas no effecton the patternwithone channelactive,allotherchannelsaredisabled.VDD = Figure2. Figure3. TotalJitter vs. Temperature TotalJittermeasured at0V differentialwhilerunninga PRBS 27-1 patternwithone channel active,allotherchannels aredisabled. Figure4. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN15MB200

150: 150: 50: 50: 15MB200 SCAN15MB200 SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com TRI-STATE AND POWERDOWN MODES The SCAN15MB200 has outputenablecontrolon each of the sixonboard LVDS outputdrivers.Thiscontrol allowseach outputindividuallytobe placedina low power TRI-STATE mode whilethedeviceremainsactive, and isusefultoreducepower consumptionon unused channels.InTRI-STATE mode, some outputsmay remain activewhilesome areinTRI-STATE. When allsixoftheoutputenables(alldriverson bothchannels)aredeasserted(LOW), thenthedeviceentersa Powerdown mode thatconsumes only0.5mA (typical)of supplycurrent.In thismode, the entiredeviceis essentiallypowered off,includingallreceiverinputs,outputdriversand internalbandgap referencegenerators. When returningto activemode from Powerdown mode, thereisa delayuntilvaliddata ispresentedat the outputsbecause oftheramp topower up theinternalbandgap referencegenerators. Any singleoutputenablethatremainsactivewillholdthedeviceinactivemode even iftheotherfiveoutputsare inTRI-STATE. When inPowerdown mode, any outputenablethatbecomes activewillwake up the deviceback intoactive mode, even iftheotherfiveoutputsareinTRI-STATE. InputFailsafeBiasing Externalpullup and pulldown resistorsmay be used toprovideenough ofan offsettoenablean inputfailsafe under open-circuitconditions.ThisconfigurationtiesthepositiveLVDS inputpintoVDD thrua pullup resistor and the negativeLVDS inputpinistiedto GND by a pulldown resistor.The pullup and pulldown resistors shouldbe inthe5kΩ to15kΩ range tominimizeloadingand waveform distortiontothedriver.Pleasereferto applicationnoteAN-1194 (SNLA051 ),“FailsafeBiasingofLVDS Interfaces”formore information. InterfacingLVPECL toLVDS An LVPECL driverconsistsofa differentialpairwithcoupledemittersconnectedtoGND viaa currentsource. Thisdrivesa pairofemitter-followersthatrequirea 50Ω toVCC -2.0load.A modern LVPECL driverwilltypically includetheterminationscheme withinthedevicefortheemitterfollower.Ifthedriverdoes notincludetheload, thenan externalscheme must be used.The 1.3V supplyisusuallynotreadilyavailableon a PCB, therefore,a loadscheme withouta uniquepower supplyrequirementmay be used. Figure5. DC Coupled LVPECL toLVDS Interface Figure5 isa separatedπ terminationscheme fora 3.3V LVPECL driver.R1 and R2 providesproperDC loadfor thedriveremitterfollowers,and may be includedas partofthedriverdevice. NOTE The biasnetworksshown above forLVPECL driversand receiversmay or may not be presentwithinthe driverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges.

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150: 150: 50: 50: 15MB200 0.1 PF 0.1 PF SCAN15MB200 www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 The 15MB200 includesa 100Ω inputterminationforthetransmissionline.The common mode voltagewillbe at the normal LVPECL levels– around 2 V. This scheme works wellwithLVDS receiversthathave rail-to-rail common mode voltage,VCM , range.Most Texas InstrumentsLVDS receivershave wide VCM range.The exceptionsarenotedindevices’respectivedatasheets.Those LVDS devicesthatdo have a wide VCM rangedo notvaryinperformancesignificantlywhen receivinga signalwitha common mode otherthanstandardLVDS VCM of1.2V. Figure6. AC Coupled LVPECL toLVDS Interface An AC coupledinterfaceispreferredwhen transmitterand receivergroundreferencesdiffermore than1 V. This isa likelyscenariowhen transmitterand receiverdevicesare on separatePCBs. Figure6 illustratesan AC coupledinterfacebetween a LVPECL driverand LVDS receiver.R1 and R2, ifnotpresentinthedriverdevice provideDC loadfortheemitterfollowersand may range between 140-220Ω formost LVPECL devicesforthis particularconfiguration. NOTE The biasnetworksshown above forLVPECL driversand receiversmay or may not be presentwithinthe driverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges. The 15MB200 includesan internal100Ω resistortoterminatethetransmissionlineforminimalreflections.The signalafterac couplingcapacitorswillswingarounda levelsetby internalbiasingresistors(i.e.fail-safe)which iseitherVDD /2or0 V dependingon theactualfailsafeimplementation.Ifinternalbiasingisnotimplemented,the signalcommon mode voltagewillslowlydrifttoGND level. InterfacingLVDS toLVPECL An LVDS driverconsistsofa currentsource(nominal3.5mA) which drivesa CMOS differentialpair.Itneeds a differentialresistiveloadintherange of70 to130Ω togenerateLVDS levels.Ina system,theloadshouldbe selectedtomatch transmissionlinecharacteristicdifferentialimpedance so thatthelineisproperlyterminated. The terminationresistorshouldbe placedas closetothereceiverinputsas possible.When interfacingan LVDS driverwitha non-LVDS receiver,one onlyneeds tobiastheLVDS signalso thatitiswithinthecommon mode range of the receiver.This may be done by usingseparatebiasingvoltagewhich demands anotherpower supply.Some receivershave requiredbiasingvoltageavailableon-chip(VT,VTT orVBB ). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SCAN15MB200

130: 130: 50: 50: LVPECL VDD 83: 83: 0.1PF 0.1PF 15MB200 50: 50: 50: 50: LVPECL VT SCAN15MB200 SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com Figure7. DC Coupled LVDS toLVPECL Interface Figure7 illustratesinterfacebetween an LVDS driverand a LVPECL witha VT pinavailable.R1 and R2, ifnot presentinthereceiver,provideproperresistiveloadforthedriverand terminationforthetransmissionline,and VT setsdesiredbiasforthereceiver. NOTE The biasnetworksshown above forLVPECL driversand receiversmay or may not be presentwithinthe driverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges. Figure8. AC Coupled LVDS toLVPECL Interface Figure8 illustratesAC coupled interfacebetween an LVDS driverand LVPECL receiverwithouta VT pin available.The resistorsR1, R2, R3, and R4, ifnotpresentinthereceiver,providea loadforthedriver,terminate thetransmissionline,and biasthesignalforthereceiver. NOTE The biasnetworksshown above forLVPECL driversand receiversmay or may not be presentwithinthe driverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges.

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www.ti.com SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 Design-For-Test(DfT)Features IEEE 1149.1SUPPORT The SCAN15MB200 supportsa fullycompliantIEEE 1149.1 interface.The Test Access Port(TAP) provides access to boundary scan cellsat each LVTTL I/Oon the deviceforinterconnecttesting.Differentialpinsare includedinthe same boundary scan chainbut insteadcontainIEEE1149.6 cells.IEEE1149.6 isthe improved IEEE standardfortestinghigh-speeddifferentialsignals. RefertotheBSDL filelocatedon TI'swebsiteforthedetailsoftheSCAN15MB200 IEEE 1149.1implementation. IEEE 1149.6SUPPORT AC-coupled differentialinterconnectionson very high speed (1+ Gbps) data paths are not testableusing traditionalIEEE 1149.1 techniques.The IEEE 1149.1 structuresand methods are intendedto teststatic(DC- coupled),singleended networks.IEEE 1149.6 is specificallydesigned fortestinghigh-speeddifferential, includingAC couplednetworks. The SCAN15MB200 is intendedforhigh-speedsignallingup to 1.5 Gbps and includesIEEE1149.6 on all differentialinputsand outputs. FAULT INSERTION FaultInsertionisa techniqueused toassistintheverificationand debug ofdiagnosticsoftware.Duringsystem testingfaultsare "injected"tosimulatehardwarefailureand thushelpverifythemonitoringsoftwarecan detect and diagnosethesefaults.In the SCAN15MB200 an IEEE1149.1 "stuck-at"instructioncan createa stuck-at condition,eitherhigh or low,on any pin or combinationof pins.A more detaileddescriptionof the stuck-at featurecan be foundinTIApplicationsnoteAN-1313 (SNLA060 ). Packaging Information The WQFN package isa leadframebased chipscalepackage (CSP) thatmay enhance chipspeed,reduce thermalimpedance,and reducetheprintedcircuitboardarearequiredformounting.The smallsizeand verylow profilemake thispackage idealforhighdensityPCBs used insmall-scaleelectronicapplicationssuch as cellular phones,pagers,and handheldPDAs. The WQFN package isofferedintheno Pullbackconfiguration.Intheno Pullbackconfigurationthestandardsolderpads extendand terminateattheedge ofthepackage.Thisfeature offersa visiblesolderfilletafterboardmounting. The WQFN has thefollowingadvantages:

• Low thermalresistance
• Reduced electricalparasitics
• Improvedboardspace efficiency
• Reduced package height
• Reduced package mass For more detailsaboutWQFN packagingtechnology,refertoapplicationsnoteAN-1187 (SNOA401 ),"Leadless LeadframePackage" Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SCAN15MB200

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SCAN15MB200TSQ/NO.A Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 15MB200 SCAN15MB200TSQ/NOPB Active Production WQFN (RHS) | 48 250 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 15MB200 SCAN15MB200TSQX/NO.A Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 15MB200 SCAN15MB200TSQX/NOPB Active Production WQFN (RHS) | 48 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 15MB200 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SCAN15MB200TSQ/ NOPB SCAN15MB200TSQX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SCAN15MB200TSQ/NOPB WQFN RHS 48 250 208.0 191.0 35.0 SCAN15MB200TSQX/ NOPB WQFN RHS 48 2500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 48X 0.30 0.18 5.1 0.1 48X 0.5 0.3 0.8 0.7 (A) TYP 0.05 0.00 44X 0.5 5.5 2X 5.5 A 7.15 6.85 B 7.15 6.85 0.30 0.18 0.5 0.3 (0.2) WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 1.800 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.25) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.25) TYP ( 5.1) (R0.05) TYP (1.25) TYP (1.05) TYP (1.05) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.25) 44X (0.5) (6.8) (6.8) 16X ( 1.05) (0.625) TYP (R0.05) TYP (1.25) TYP (1.25) TYP (0.625) TYP WQFN - 0.8 mm max heightRHS0048A PLASTIC QUAD FLATPACK - NO LEAD 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X SYMM 13 24 3748

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