SCAN12100

SCAN12100 NSC | Alldatasheet

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■ Exceeds LV and HV CPRI voltage and jitter requirements ■ 1228.8, and 614.4 Mbps operation ■ Pin and package compatibility with the SCAN25100 ■ Integrated delay calibration measurement (DCM) directly measures T14 and Toffset delays to ≤ ± 800 ps ■ DCM also measures chip and other delays to ≤ ± 1200 ps accuracy ■ Deterministic chip latency ■ Automatic receiver lock and RE synchronization without reference clock or external crystal ■ Independent transmit and receive PLLs for seamless RE synchronization ■ Low noise recovered clock output ■ Requires no jitter cleaning in single-hop applications ■ >8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV CDM ■ Hot plug protection ■ LOS, LOF, 8b/10b line code violation, comma, and receiver PLL lock reporting ■ Programmable hyperframe length and start of hyperframe character ■ Programmable transmit de-emphasis and receive equalization with on-chip termination ■ Advanced testability features — IEEE 1149.1 and 1149.6 — At-speed BIST pattern generator/verifier — Multiple loopback modes ■ 1.8V or 3.3V compatible parallel bus interface ■ 100-pin TQFP package with exposed dap ■ Industrial –40 to +85° C temperature range Block Diagram 20209542 © 2006 National Semiconductor Corporation 202095 www.national.com SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes

(Top View) 100–Pin TQFP with Exposed Ground Pad Order Number SCAN12100TYA See NS Number VXF100B www.national.com 2 SCAN12100

Pin # Pin Name I/O, Type Description HIGH SPEED DIFFERENTIAL I/O DOUTP DOUTN O, CML Inverting and non-inverting high speed CML differential outputs of the serializer. On- chip termination resistors connect from DO+ and DO− to an internal reference RINP RINN I, CML Inverting and non-inverting high speed differential inputs of the deseralizer. On-chip termination resistors connect from RI+ and RI− to an internal reference. On-chip termination resistors are configured for AC-coupled applications. PARALLEL DATA BUS DIN [0] DIN [1] DIN [2] DIN [3] DIN [4] DIN [5] DIN [6] DIN [7] DIN [8] DIN [9] I, LVTTL or 1.8V LVCMOS Internal pull down Transmit data word. In 10-bit mode, the 10-bit code-group at DIN [0–9] is serialized with the internal 8b/ 10b encoder disabled. Bit 9 is the msb. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 ROUT [0] ROUT [1] ROUT [2] ROUT [3] ROUT [4] ROUT [5] ROUT [6] ROUT [7] ROUT [8] ROUT [9] O, LVTTL or 1.8V LVCMOS Internal pull down Deserialized receive data word. In 10-bit mode, ROUT [0-9] is the deserialized received data word in 10-bit code group. Bit 9 is the msb. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 CLOCK SIGNALS REFCLKP REFCLKN I, LVDS or LVPECL Inverting and non-inverting differential serializer reference clock. A low jitter clock source should be connected to REFCLKP & REFCLKN. 64 TXCLK I, LVTTL or 1.8V LVCMOS Internal pull down Transmit clock. TXCLK must be synchronous to REFCLK to avoid FIFO under/ overflow though it may differ in phase. 52 RXCLK I/O, LVTTL or 1.8V LVCMOS Write mode: RXCLK is recovered clock output pin. Read mode: RXCLK is an input pin. ROUT [9:0] are latched out on RXCLK rising and falling edges. RXCLK must be synchronous to the incoming serial data to avoid FIFO over/underflow, though it may differ in phase. See RXCLKMODE pin description for more details. SYSCLKP SYSCLKN O, LVDS 30.72 MHz output clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V LVCMOS Receiver CPRI loss of signal (LOS) status (8-bit mode only). 0 = signal detected (per CPRI standard) 1 = signal lost (per CPRI standard) 77 LOCKB O, LVTTL or 1.8V LVCMOS Receiver PLL lock status 0 = Receiver PLL locked 1 = Receiver PLL not locked 3 www.national.com SCAN12100

Pin # Pin Name I/O, Type Description 79 CDET O, LVTTL or 1.8V LVCMOS Comma Detect. 0 = no comma yet detected in the incoming serial stream or receiver PLL not locked. 1 = the receiver PLL is locked and a positive or negative comma bit sequence detected in the incoming bit stream. The serial to parallel converter is aligned to the proper 10- bit word boundary when comma alignment is enabled (CALIGN_EN = 1). CONTROL PINS PE [0] PE [1] I, LVTTL or 1.8V LVCMOS Internal pull down Transmitter de-emphasis configuration. Pulling both pins low enables MDIO control, default is no de-emphasis. PE1 PE0 0 0 No de-emphasis 0 1 Low de-emphasis 1 0 Medium de-emphasis 1 1 Maximum de-emphasis EQ [0] EQ [1] I, LVTTL or 1.8V LVCMOS Internal pull down Receive input equalization configuration. Pulling both pins low enables MDIO control, default is no receive equalization. EQ1 EQ0 0 0 No receive equalization 0 1 Low receive equalization 1 0 Medium receive equalization 1 1 Maximum receive equalization TXPWDNB RXPWDNB I, LVTTL or 1.8V LVCMOS Internal pull down Power down control signals. TXPWDNB 0 = Transmitter is powered down and DOUT± pins are high impedance. 1 = Transmitter is powered up. RXPWDNB 0 = Receiver is powered down and ROUT [9:0] as well as LOS, LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 = Receiver is powered up. 92 CALIGN_EN I, LVTTL or 1.8V LVCMOS Internal pull down Comma alignment enable. 0 = comma alignment circuitry disabled. Receiver will not realign 10-bit data based on incoming comma characters. CDET pin still flags comma detection. 1 = comma detect and alignment circuitry enabled. Receiver aligns 10-bit data to incoming comma character and flags comma detect through CDET pin. 93 RXCLKMODE I, LVTTL or 1.8V LVCMOS Internal pull down Receiver recovered clock mode 0 = Write mode. RXCLK pin is a recovered clock output. (RXCLK = output pin) 1 = Read mode. RXCLK pin is ROUT [9:0] bus read input strobe. (RXCLK = input pin) 80 VSEL I, LVTTL or 1.8V LVCMOS Internal pull down Selects whether single-ended data and control pins are 3.3V LVTTL or 1.8V LVCMOS. 0 = 1.8V LVCMOS. Tie VSEL to ground and power IOVDD at 1.8 V. 1 = 3.3V LVTTL. Tie VSEL to IOVDD supply and power IOVDD at 3.3 V. 94 OPMODE I, LVTTL or 1.8V LVCMOS Internal pull down Selects SerDes mode. 0 = Base station mode 1 = Reserved for future use 95 RESETB I, LVTTL or 1.8V LVCMOS Internal pull down Hardware SerDes reset. Resets PLLs and MDIO registers. 0 = Hardware SerDes reset 1 = Normal operation www.national.com 4 SCAN12100

Pin # Pin Name I/O, Type Description SPMODE [0] SPMODE [1] I, LVTTL or 1.8V LVCMOS Internal pull down Speed mode configuration. (OPMODE must be low) Pulling both pins low enables MDIO control. SPMODE [1] SPMODE [0] 0 0 Rate selected via MDIO 0 1 614.4 Mbps rate mode 1 0 1228.8 Mbps rate mode 1 1 Reserved 98 TENBMODE I, LVTTL or 1.8V LVCMOS, Internal pull down Enable 10-bit mode The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder. 1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder. 100 LOOP [0] LOOP [1] I, LVTTL or 1.8V LVCMOS, Internal pull down Loop back configuration. Pulling both pins low enables MDIO control. Note: During Special line (remote) loop back mode, the output de-emphasis control is disabled. LOOP [1] LOOP [0] 0 0 Normal mode—no loop back 0 1 Line (remote) loop back mode 1 0 Local loop back mode 1 1 Special line (remote) loop back mode MDC/MDIO MDC MDIO ADD0 ADD1 ADD2 ADD3 ADD4 3.3V LVTTL Internal pull up on ADDR pins MDC/MDIO configuration bus. Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible. IEEE 1149.1 (JTAG) TDI TDO TMS TCK TRSTB 3.3V LVTTL Internal pull up on TDI, TMS, and TRSTB JTAG test bus for IEEE 1149.1 and 1149.6 support. RESERVED PINS RES1 RES2 I Reserved. Tie with 5 KΩ resistor to ground. POWER 9, 15, 20, 32, 38, 47, AVDD18 I, Power 1.8V analog supply. 8, 14, 21, AVDD33 I, Power 3.3V analog supply. 1, 2, 28, 29 PVDD33 I, Power 3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak). 50, 51, 76, IOVDD I, Power 1.8V or 3.3V parallel I/O bus and control pin supply. See VSEL pin description for additional information. GROUND 3, 4, 5, 10, 13, 16, 19, 24, 25, 26, 27, 39, 40, 48, 49, 63, 75, 86 GND I, Ground Device ground. 5 www.national.com SCAN12100

Pin # Pin Name I/O, Type Description GROUND DAP 101 GND I, Ground Device ground. Pad must be soldered and contected to GND plane with a minimum of 8 thermal vias to achieve specified thermal performance. Note: I= input O = output Internal pull down = input pin is pulled low by an internal resistor Internal pull up = input pin is pulled high by an internal resistor www.national.com 6 SCAN12100

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (AVDD18) −0.3V to +2.0V Supply Voltage (PVDD, IOVDD) −0.3V to +3.6V Supply Voltage (AVDD33) −0.3V to +3.6V LVCMOS Input Voltage −0.3V to (IOVDD + 0.5V) LVCMOS Output Voltage −0.3V to (IOVDD + 0.5V) MDC/MDIO/ADD[0:4],VSEL Input Voltage −0.3V to (AVDD33 + 0.5V) MDIO Output Voltage −0.3V to (AVDD33 + 0.5V) CML Receiver Input Voltage −0.3V to (AVDD + 0.3V) CML Receiver Output Voltage −0.3V to (AVDD + 0.3V) Junction Temperature +125°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 10–20 sec 235 °C Lead-free +260°C flow is available Maximum Package Power Dissipation at 25°C 100-pin TQFP with Exposed Pad 4.16 W Note: This is the maximum TQFP-100 package power dissipation capability. For SCAN12100 power dissipation, see the information in the Electrical Characteristics section. Derating above 25°C 41.6 mW/°C Thermal Resistance , θJA (0 airflow) 24.0°C/W ESD Rating CML RIN/DOUT Pins HBM, 1.5 k Ω, 100 pF >8 kV EIAJ, 0 Ω, 200 pF >250V CDM >2 kV All Other Pins HBM, 1.5 k Ω, 100 pF >7 kV EIAJ, 0 Ω, 200 pF >250V CDM >2 kV Recommended Operating Conditions Min Typ Max Unit Supply Voltage AVDD18 1.7 1.8 1.9 V AVDD33, PVDD33 3.135 3.3 3.465 V IOVDD (1.8V Mode) 1.7 1.8 1.9 V IOVDD (3.3V Mode) 3.135 3.3 3.465 V Temperature -40 25 85 °C Junction temperature 125 °C Supply Noise (Peak-to-Peak) <100 mV Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Condition Min Typ (Note 2) Max Units LVCMOS DC SPECIFICATIONS (1.8V I/O) VIH High level input voltage 0.65VDD V VIL Low level input voltage 0.35VDD V IIN Input Current VIN = 0V or 1.9V −10 +50 µA VOH High level output voltage IOH = −2 mA 1.2 V VOL Low level output voltage IOL = 2 mA 0.45 V IOZ Power Down Output Current Power down −20 +20 µA CIO Input/Output Capacitance Typical 2.8 pF LVCMOS DC SPECIFICATIONS (3.3V I/O) VIH High level input voltage 2 V VIL Low level input voltage 0.8 V IIN Input Current VIN = 0V or 3.465V −10 +50 µA VOH High level output voltage IOH = −2 mA 2.4 V VOL Low level output voltage IOL = 2 mA 0.4 V IOZ Power Down Output Current Power down −20 +20 µA CIO Input/Output Capacitance Typical 2.8 pF JTAG DC SPECIFICATIONS (3.3V I/O) VIH High level input voltage 2 V VIL Low level input voltage 0.8 V IIN Input Current VIN = 0V or 3.465V −35 +50 µA VOH High level output voltage IOH = −2 mA 2.4 V 7 www.national.com SCAN12100

Symbol Parameter Condition Min Typ (Note 2) Max Units VOL Low level output voltage IOL = 2 mA 0.4 V CIO Input/Output Capacitance Typical 2.8 pF MDIO/MDC/ADD0-4 DC SPECIFICATIONS VIH High level input voltage 2.0 3.465 V VIL Low level input voltage GND 0.8 V IIN Input Current VIN = 0 or 3.465V -150 150 µA VOH High level output voltage IOH = −2 mA 2.4 V VOL Low level output voltage IOL = 2 mA 0.4 V IOZ Power Down Output Current Power down −100 +100 µA CIO Input/Output Capacitance Typical 2.8 pF POWER CONSUMPTION (Powerdown) PPDN Powerdown Mode Rx and Tx Powerdown 25 40 mW RECOMMENDED REFCLK INPUT SPECIFICATIONS VIDSREFCLK Differential input voltage ± 100 mVP-P VICM Common mode voltage 0.05V 2.4V V fREF REFCLK frequency OPMODE = 0 (BTS SerDes Mode) 30 30.72 31.5 MHz dfREF REFCLK frequency variation Variation from nominal frequency −100 100 ppm tREF-DC REFCLK duty cycle Between 50% of the differential voltage across REFCLKP and REFCLKN 45 55 % tREF-X REFCLK transition time Transition time between 20% and 80% of the differential voltage across REFCLKP and REFCLKN 300 pS SYSCLK DC OUTPUT SPECIFICATIONS VOD Differential Output Voltage RL = 100Ω ± 250 ± 330 ± 450 mV VOS Offset Voltage 1.125 1.20 1.375 V IOS Output Short Circuit Current Output pair shorted together and tied to GND 35 mA IOZ Power Down Output Current Power down −30 +30 µA TRANSMITTER SERIAL TIMING SPECIFICATIONS VOD Output differential voltage swing PE[1]=0, PE[0]=0 ± 550 ± 700 ± 800 mVp-p PE[1]=0, PE[0]=1 ± 630 mVp-p PE[1]=1, PE[0]=0 ± 500 mVp-p RDO Output differential resistance 80 100 120 Ω RO Output Return Loss Frequency = 1.229 GHz -13.4 dB tR, tF Serial data output transition time (Notes 10, 14) Measured between 20% and 80% 80 100 130 ps JITT-DJ Serial data output deterministic jitter (Notes 3, 10) Output CJPAT with BER of 10−12 (Note 4)

0.14 UIp-p

JITT-TJ Serial data output total jitter (Notes 3, 10) Output CJPAT pattern with BER of 10−12 (Note 4)

0.279 UIp-p

tLAT-T Transmit latency (Note 7) 614.4 Mbps 310 ns

1.228 Gbps 155

tDO-LOCK Maximum lock time K28.5 pattern at 1228.8 Mbps 110 130 us RECEIVER SERIAL TIMING SPECIFICATIONS VID Input voltage RINP - RINN ± 100 ± 1100 mVp-p VCMR Receiver common mode voltage 0.9 V RR Differential Input Terminations 80 100 120 Ω www.national.com 8 SCAN12100

Symbol Parameter Condition Min Typ (Note 2) Max Units RLRI Input Return Loss (Note 10) Frequency = 1.229 GHz -20 -15 dB tLAT-R Receive latency (Note 8) 614.4 Mbps 280 ns

1.228 Gbps 140 ns

JITR-TOL Total input jitter tolerance (Note 10) Input CJPAT with BER of 10−12 (Note 4)

0.66 UIp-p

FR-LOCK Receiver lock range Input data rate reference to local transmit data rate. −200 +200 ppm tR-LOCK Maximum lock time K28.5 pattern at 1228.8 Mbps 1 ms TRANSMITTER INPUT TIMING SPECIFICATIONS tS-T Setup Time DIN [9:0] valid to TXCLK rising or falling edge 0.5 ns tH-T Hold Time TXCLK rising or falling edge to DIN [9:0] valid 0.5 ns tDC Duty cycle TXCLK duty cycle 45 55 % fTXCLK TXCLK frequency 30 62.5 MHz RECEIVER OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1) tPDRX RXCLK Propagation Delay RXCLK rising or falling edge to ROUT [9:0] valid 2 4 6 ns tDC Duty cycle RXCLK input duty cycle 45 55 % fRXCLKR RXCLK input frequency RXCLK input frequency 30 62.5 MHz tR, tF Output data transition time For ROUT [0-9], LOCK, etc. pins. Measured between 20% and 80% levels 0.35 ns RECEIVER OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0) tS-R Setup Time ROUT [9:0] valid to RXCLK rising or falling edge (Note 9) 2.2 ns tH-R Hold Time RXCLK rising or falling edge to ROUT [9:0] valid (Note 9) 2.4 ns tDC Duty cycle RXCLK duty cycle 45 55 % fRXCLK RXCLK frequency 30 62.5 MHz tR, tF Output data transition time For ROUT [0-9], LOCK, etc. pins. Measured between 20% and 80% levels 0.35 ns CDET OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1) tPDCD CDET Propagation Delay RXCLK rising or falling edge to CDET 2 4 6 ns CDET OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0) (Note 5) tS-C Setup Time CDET valid to RXCLK rising or falling edge 2.6 ns tH-C Hold Time RXCLK rising or falling edge to CDET valid 2.6 ns SYSCLK LVDS OUTPUT TIMING SPECIFICATIONS tSYSCLKNDC Duty cycle 40 60 % JITSYSCLK Cycle to cycle jitter (Note 10) 40 65 ps p-p tR, tF Output transition time Between 20% and 80% levels (Note 10) 0.1 0.3 ns MDC/MDIO TIMING SPECIFICATIONS (Clause 45) fMDC MDC Frequency 0 2.5 MHz tS-MDIO Setup Time MDIO (input) valid to MDC rising clock 10 ns 9 www.national.com SCAN12100

Symbol Parameter Condition Min Typ (Note 2) Max Units tH-MDIO Hold Time MDC rising edge to MDIO (input) invalid 10 ns tD-MDIO Delay Time MDIO (output) delay from MDC rising edge 0 300 ns tX-MDIO Transition Time Measured at MDIO when used as output, CL = 470 pF 1 ns MINIMUM PULSE WIDTH, Hardware Reset (Note 11) tTX-RST Transmiter Reset TXPWDNB = 0 1 us tRX-RST Receiver Reset RXPWDNB = 0 1 us tRST SerDes Reset RESETB = 0 1 us JTAG TIMING SPECIFICATIONS fJTAG JTAG TCK Frequency RL= 1000Ω, CL = 15 pF 25 MHz tR-J tF-J TDO data transition time (20% to 80%) 2 ns tS-TDI Setup Time TDI to TCK High or Low 2 ns tH-TDI Hold Time TDI to TCK High or Low 2 ns tS-TMS Setup Time TMS to TCK High or Low 2 ns tH-TMS Hold Time TMS to TCK High or Low 2 ns tW-TCK TCK Pulse Width 10 ns tW-TRST TRSTB Pulse Width 2.5 ns tREC Recovery Time TRSTB to TCK 14 ns DELAY CALIBRATION MEASUREMENT (DCM) (Notes 10, 12, 13) T14 T14 Delay Accuracy Receive and Transmit PLLs locked to valid hyperframe data. ± 800 ps Toffset Toffset Delay Accuracy ± 800 ps Tser Serializer Delay Accuracy ± 1200 ps Tdes Deserializer Delay Accuracy ± 1200 ps Tin-out Tin-out Delay Accuracy ± 1200 ps Tout-in Tout-in Delay Accuracy ± 1200 ps Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Typical parameters are measured at nominal supply levels and TA = 25°C. They are for reference purposes and are not production-tested. Note 3: Transmit Jitter testing methodology is defined in Appendix 48B of IEEE 802.2ae-2002. The SCAN12100 transmit output jitter is constant for all valid CPRI datarates. The transmit jitter is significantly less than the specified limits in terms of UI. Note 4: CJPAT is a stress pattern defined in IEEE 802.2ae-2002 Appendix 48A Note 5: CDET nominal valid duration is determined by the CPRI data rate. CDET timing is similar to the ROUT[0:9] timing. Note 6: Transmit or Receive K28.5 pattern. Assumes TXCLK is stable and toggles only after all SerDes clocks become synchronous. Note 7: Transmit latency is fixed once the link is established and is guaranteed by the Tser specification. Note 8: Receive latency is fixed once the link is established and is guaranteed by the Tdes specification. Note 9: Receiver output timing specifications for TS-R and TH-R are tested at the CPRI rate of 1.2288 Gbps. Note 10: Limits are guaranteed by design and characterization over process, supply voltage, and temperature variations. Note 11: Limits are guaranteed by design. Note 12: Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output. Note 13: DCM readings are valid when the RXCLK pin on the SCAN12100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD = 3.3V. Note 14: Edge rate characterization includes the loading effects of 1.0 uF AC-coupling capacitors and 4 inches of 100 ohm differential microstrip. www.national.com 10 SCAN12100

11 www.national.com SCAN12100

The SCAN12100 implements the device ID of 61 (0x3D.) Other registers defined by 802.3ae-2002 are not implement- ed in SCAN12100. The SCAN12100 has a rich MDIO register set to allow the chip to be controlled and monitored through software. Certain functions such as BIST and delay calibra- tion are only accessible through MDIO. The type of registers used in SCAN12100 are RW, RC, RO, and WC. RW is a read and write register. RC is a read and clear register. Upon reading the value of the RC register through MDIO, the register will reset its value. WC is a write and clear register. Write and clear registers are used for reset operations. A re-read of the WC register is necessary to verify the register has been cleared. Address Name Access Description (hex) 0 RESERVED RW Reserved. 1 POWERDOWN RW Transmiter and Receiver POWERDOWN control. 2 OUI RO OUI. 4 RESET RC Transmiter and Receiver RESET control. 5 Rx Equalization RW CPRI LOF (Loss of Frame) bypass and Receiver EQ control. 6 Tx De-Emphasis RW Hyperframe size and Transmitter De-Emphasis control. 7 LOOPBACK RW Selects Normal, Line and Local Loopback. 8 MDIO RO Required by MDIO. 9 BIST RW Pattern and Enable control for Trasmit and Receive BIST. A Speed Mode RW/Pin OW Selects CPRI speed mode. B BIST Status RC BIST status information. C RESERVED RO Reserved. D DCM Start RC Initiates or restarts Delay Calibration Measurement. E OUI Duplicate RO Duplicate of Register Address 2. F OUI Rev. Duplicate RO Duplicate of Register Address 3. 10 LOF RC CPRI Loss of Frame (LOF) counter. 11 LOS RC CPRI Loss of Sync (LOS) counter. 12 Rx Lock RC Receiver Loss of Lock (LOCKB) counter. 13 Loss of Clock RO Loss of Transmit and/or Receive clock. 14 PLL Status RO Tx and Rx PLL status. 15 Hyperframe Length RW Programmable Hyperframe Length control. 16-17 DCM Trigger RW Delay Calibration Trigger pattern. 18 Reserved RW Reserved.

19 Hyperframe Tuning RW Programmable Hyperframe size and DCM enable

1A-1D Reserved RO Reserved. 1E T14 Lower RO T14 Measurement. 1F T14 Upper RO T14 Measurement. 20 Toffset Lower RO Toffset Measurement. 21 Toffset Upper RO Toffset Measurement. 22 Tser Lower RO Tser Measurement. 23 Tser Upper RO Tser Measurement. 24 Tdes Lower RO Tdes Measurement. 25 Tdes Upper RO Tdes Measurement. 26 Tin-out Lower RO Tin-out Measurement. 27 Tin-out Upper RO Tin-out Measurement. 28 Tout-in Lower RO Tout-in Measurement. 29 Tout-in Upper RO Tout-in Measurement. www.national.com 12 SCAN12100

Physical Dimensions inches (millimeters) unless otherwise noted 100-Pin TQFP with Exposed Ground Pad (Top View) Order Number SCAN12100TYA See www.national.com/quality/marking_conventions.html for additional part marking information 13 www.national.com SCAN12100

SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2006 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com