SC908 SEMTECH | Alldatasheet
Document overview
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Technical content
Features
Single Cell Li-Ion battery charger — CC/CV charging with current soft start Charger regulated output voltage — 4.2V ±1% over temperature with Kelvin sense of battery voltage Charger input protection withstands 28V indefi nitely Charger max constant current setting — 500mA Adjustable charge termination current down to 10mA Battery NTC interface disables charging if battery temperature out of range Programmable low battery detector threshold Four status indicators Programmable charge completion timer Buck converter with enable — output programmable from 1V to 3V, 150mA max output Buck converter effi ciency — 88% at 50mA General purpose low noise LDO regulator with fast enable, active shutdown 4x4x0.9 (mm) MLPQ package WEEE and RoHS compliant
Applications
Description
The SC908 is a complete power management system designed for use in Bluetooth wireless headsets, portable media players, and other battery-powered electronics where size is critical. Included are a full featured stand- alone Li-Ion battery charger with a programmable low-battery monitor, a low noise LDO regulator, and a DC- DC buck converter. Battery charging features include programmable pre- charge, fast-charge, and termination current settings. Charge termination is controlled by a programmable timer and by a resistor that sets the termination current. The 28V max input voltage protects against hotplug over- shoot and faulty adapters without additional protection circuitry. The battery voltage Kelvin sense input elimi- nates errors due to high charging currents. A battery thermistor interface disables charging when the battery temperature exceeds safe-to-charge limits. The step-down switching regulator (buck converter) improves system effi ciency and extends battery life. The LDO regulator can be powered directly from the battery or from the buck converter output when effi ciency is criti- cal. The fast-starting low noise LDO regulator is suitable for audio, RF, or general purpose regulation required by peripheral devices, such as a vibrating alert motor. The low battery detector warns when the battery level is below 3.3V, and when the battery has discharged below a lower programmable voltage limit. SC908 BAT IPRGM ITERM DGND EN_NTC CHRGB RTIME RIPRGM Li-Ion BATTERYCBAT LVIN LVOUT CLVOUT LS RS1 RS2 LEN SEN SFB PGND SLX AGND CSVOUT SVOUT, To Bluetooth Processor RRTIME RNPU RNTC (Battery Pack NTC Thermistor) FLTB LBATB CLVIN RL1 RL2 LFB RLBAT RITERM BSEN RRLBAT VAD Charging Adapter CVAD Can supply LDO from battery or from DC-DC converter VSYS CVREF VREF CVSYS CPB CSFB Charging Charger Present To Audio Circuits or vibrator motor CSFG Typical Application Circuit January 24, 2008 US Patent: 6,836,095
Ordering Information
SC908MLTRT(1,2) MLPQ-24 SC908EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free package only. Device is WEEE and RoHS compliant. TOP VIEW 7 8 9 10 11 12 24 23 22 21 20 19 14T VAD RLBAT RTIME ITERM IPRGM VSYS LVIN DGND AGND VREF LVOUT LFB SEN LEN CPB FLTB LBATB SFB CHRGB PGND SLX EN_NTC BAT BSEN SC908 yyww xxxxx xxxxx MLP-24; 4x4, 24 LEAD θJA = 29°C/W yy = year of manufacture ww = week of manufacture xxxx = lot number
Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) All absolute maximum ratings are with respect to DGND unless otherwise noted. (2) V SRC = larger of VBAT and VVSYS (3) Continuous (4) Peak (5) Tested according to JEDEC standard JESD22-A114-B. (6) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Absolute Maximum Ratings(1) SRC (2) + 0.3 DC-DC Converter Output Current (mA) ESD Protection Level Recommended Operating Conditions BAT Thermal Information Test Conditions: VVAD = 4.75V to 5.25 V; VBAT = 3.7V; VLEN = VVAD; Typ values at 25°C; Min and Max at -40°C < TA < 85°C, unless specifi ed. Parameter Symbol Conditions Min Typ Max Units Charger VAD Input Voltage VADOP (1) Operating Voltage 4.45 5 7.05 V VADUVLO-R UVLO Rising Threshold 4.05 4.25 4.45 V VADUVLO-F UVLO Falling Threshold 3.8 4 4.2 V VADUVLO-H UVLO Hysteresis (V ADUVLO-R - VADUVLO-F) 150 mV VADOVP-R OVP Rising Threshold 7.5 7.80 V VADOVP-F OVP Falling Threshold 7.05 7.3 V VADOVP-H OVP Hysteresis (V ADOVP-R - VADOVP-F) 50 mV Battery Leakage Current (2) lleakBAT VVAD=VSEN=VLEN=0V, VBAT=4.2V 0.1 2 μA
Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units Charger (continued) Charging Adapter Operating Current VADICCQ VEN_NTC = 0.5 × VVSYS, ICPB = ICHRGB = IFLTB = ILBATB = IITERM = IIPRGM = 0mA, VSEN = VLEN = 0V 1.5 mA CV Regulation Voltage V CV Measured at BSEN pin 20mA < IBAT < 500mA 0°C < TJ < 125°C 4.16 4.2 4.24 V Precharge Threshold (Rising) VT PreQ Measured at BSEN pin 2.7 2.8 2.9 V Recharge Threshold (Falling) VT ReQ VCV - VBSEN 65 113 160 mV VSYS output voltage (3) VVSYS VVAD ≥ 5V, IVSYS ≤ 5mA 4.7 V VSYS output current I VSYS 5m A ITERM Programming Resistor R ITERM Nominal 1%-tol Standard Value 2.67 17.4 kΩ IBAT Pre-Charge Current I PreQ RITERM = 4.99kΩ to GND 27 39 52 mA IBAT Termination Current I TERM RITERM = 4.99kΩ to GND 27 39 52 mA IPRGM Programming Resistor R IPRGM Nominal 1%-tol Standard Value 2.15 15.0 kΩ IBAT Fast-Charge Current I FQ RIPRGM = 6.04kΩ, VBAT = 3.7V 167 173 179 mA VAD - BAT Dropout Voltage V DO IBAT = 500mA, 0°C ≤ TJ ≤ 85°C 0.8 V IPRGM Regulated Voltage V IPRGM RIPRGM = 6.04kΩ to GND 1.45 1.5 1.55 V ITERM Regulated Voltage V ITERM RITERM = 4.99kΩ to GND 1.45 1.5 1.55 V RTIME Regulated Voltage V RTIME RRTIME = 37.4kΩ to GND 1.475 1.56 1.625 V Precharge Fault Time-Out t PreQF RRTIME = 37.4kΩ to GND 38 47 57 mins RRTIME connected to VSYS 32 42 53 mins Charge Complete Time-Out t QComp RRTIME = 37.4kΩ to GND 2.50 3.10 3.70 hrs RRTIME connected to VSYS 2.10 2.67 3.50 hrs EN_NTC Thresholds VTNTC_DIS Charger Disable/Reset (Falling) 9 10 11.5 %V VSYS VTNTC_HF NTC Hot (Falling) 27.5 30 31.5 %V VSYS VTNTC_CR NTC Cold (Rising) 74 75 76.5 %V VSYS EN_NTC Hysteresis VT NTC_HYS VVAD = 5V 45 mV EN_NTC Disable/Reset Hold Time tNTC_DIS_H Momentary disable resets charger 500 ns Charger Over-Temperature Shut- down Temperature (Rising) TCHRGR_OT Hysteresis = 10°C typical 145 °C Electrical Characteristics (continued)
Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Core Functions (Excluding Charger) Core Circuits Quiescent Current (4) IQ-Core VVAD = VSEN = 0V, VLEN = VBAT = 4.2V 100 μA VREF Reference Voltage V VREF 0.75 V VREF Power Supply Rejection PSRR REF VBAT = 3.7V with 0.5VP-to-P ripple, f ≤ 10kHz, CVREF = 10nF 70 dB VREF Reference Voltage Start-Up Time (5, 10) tSU_REF Delay from first of SEN high LEN high, VBAT = 3.7V CVREF = 10nF VREF from 0V to 95% of fi nal 0.4 ms DC-DC Buck Converter Buck Converter Input Voltage V SVIN BAT pin is also the switching regulator supply input VBAT V Buck Converter Under-Voltage Lockout Rising Threshold VTSUVLO-R 2.8 V Buck Converter Under-Voltage Lockout Falling Threshold VTSUVLO-F 2.55 V Buck Converter Under-Voltage Lockout Hysteresis VTSUVLO-HYS 84 mV Buck Converter Quiescent Current (2) IBAT-Q VSEN = VBAT, ISVOUT = 10mA Low IQ mode of PSAVE 115 μA Buck Converter Minimum On-Time tSON_MIN 60 ns Buck Converter Maximum Duty Cycle (10) SDCMAX 92 % Buck Converter Program Output Voltage Minimum (6,10) VSVOUT_MIN 1V Buck Converter Program Output Voltage Maximum(6,7,8,10) VSVOUT_MAX VBAT ≥ VSVOUT_MAX/SDCMAX+150mV 3 V Buck Converter Feedback Regulation Voltage VSFB 0.480 0.500 0.520 V Buck Converter Output Voltage(6) VSVOUT VBAT = 3.7V, L = 4.7μH ISVOUT = 100mA RS1 = 340kΩ, RS2 = 100kΩ 2.2 V Buck Converter Line Regulation(6) VSVOUT_LINE 2.8V ≤ VBAT ≤ 4.5V ISVOUT = 100mA RS1 = 340kΩ, RS2 = 100kΩ -0.3 0.3 %/V Buck Converter Load Regulation (6) VSVOUT_LOAD 5mA ≤ ISVOUT ≤ 150mA VBAT = 3.7V RS1 = 340kΩ, RS2 = 100kΩ 0.002 %/mA
Parameter Symbol Conditions Min Typ Max Units DC-DC Buck Converter (continued) Buck Converter P-Channel Peak Current Limit ILIM_P 410 440 470 mA Buck Converter P-Channel On-Resistance RDS(ON)P ISVOUT = 150mA 0.75 Ω Buck Converter N-channel On-Resistance RDS(ON)N ISVOUT = 150mA 1.05 Ω Buck Converter Oscillator Frequency fOSC 0.85 1.00 1.15 MHz Buck Converter Start-Up Time (5,10) tSU-SVOUT ISVOUT = 150mA, VSVOUT to 95% VSVOUT = 1V VSVOUT = 1.8V VSVOUT = 2.2V VSVOUT = 3.0V 0.3 1.3 1.45 1.8 2 ms Linear Low Drop-Out (LDO) Regulator LDO Input Voltage V LVIN VBAT ≥ 2.8V 2.2 VBAT V LDO Under Voltage Lockout Rising Threshold VTLUVLO-R 1.95 2.05 V LDO Under Voltage Lockout Falling Threshold VTLUVLO-F 1.75 1.85 V LDO Under Voltage Lockout Hysteresis VTLUVLO-HYS 120 mV LDO Nominal Output Voltage Minimum (10) VLVOUT_MIN VLVIN > VLVOUT +300mV 1.5 V LDO Nominal Output Voltage Maximum (10) VLOUT_MAX VLVIN > VLVOUT +300mV 3.3 V LDO Feedback Regulation Voltage VLFB VLVIN = 3.7V, ILVOUT = 1mA 0.75 V LDO Output Voltage V LVOUT RL1 = 54.9kΩ, RL2 = 39.2kΩ VLVIN = 3.7V, ILVOUT = 1mA 1.73 1.8 1.85 V LDO Dropout Voltage V L_DO VLVOUT = 2.2V, ILVOUT = 100mA 115 200 mV VLVOUT = 3.0V, ILVOUT = 150mA 130 225 mV LDO Load Regulation (with respect to 1mA load) (9) ΔVLVOUT_LOAD RL1 = 54.9kΩ, RL2 = 39.2kΩ (VLVOUT = 1.8V), VLVIN = 2.2V 1mA ≤ ILVOUT ≤ 100mA -10 10 mV RL1 = 54.9kΩ, RL2 = 39.2kΩ (VLVOUT = 1.8V), VLVIN = 3.7V 1mA ≤ ILVOUT ≤150mA -10 10 mV Electrical Characteristics (continued)
Parameter Symbol Conditions Min Typ Max Units Linear Low Drop-Out (LDO) Regulator (continued) LDO Line Regulation (9) ΔVLVOUT_LINE 2.2V ≤ VLVIN ≤ 4.2V referenced to 3.7V, ILVOUT = 1mA, RL1 = 54.9kΩ, RL2 = 39.2kΩ -5 5 mV LDO LVOUT/LVIN Power Supply Rejection Ratio PSRRLLVIN VLVIN = 3.7VDC with 0.5V P-to-P Ripple, f ≤ 10kHz, VBAT = 3.7VDC VLVOUT = 1.8V, ILVOUT = 30mA 60 dB LDO LVOUT/(BAT and LVIN) Power Supply Rejection Ratio PSRRLBAT VLVIN = VBAT = 3.7VDC with 0.5V P-to-P Ripple, f ≤ 10kHz VLVOUT = 1.8V, ILVOUT = 30mA 60 dB LDO Output Noise Voltage (9) VL_NOISE 10Hz ≤ f ≤ 100kHz CLVOUT = 1μF, VLVOUT = 3.0V VLVIN = 3.7V, ILVOUT = 50mA 50 μV RMS LDO Quiescent Current (ILVIN - ILVOUT) (4) ILQ VLVIN = VLEN = VBAT = 4.2V, VVAD = 0V, ILVOUT = 1mA 91 μA LDO Current Limit I L_LIM VLVOUT = 0V, VLEN = VBAT 300 380 450 mA LDO Start-Up Time (5, 10) tSU-LVOUT Time from LEN (with VSEN = VBAT, disregard tSU_REF), VLVOUT from 0V to 95% of fi nal 0.1 ms Time from LEN (with VVAD = VSEN = 0, tSU_REF dominates) VLVOUT from 0V to 95% of fi nal 0m s LDO Turn-Off Time t TO-LVOUT Time from LEN = 0, VLVOUT from 100% to 10% of regulation 0.5 ms Battery Voltage Detector Battery Detector Minimum Operating Voltage VDET_MINOP 2.3 V Battery Detector Maximum Operating Voltage VDET_MAXOP 4.5 V Battery Detector Voltage Warning, Decreasing VWARN VDET_MINOP ≤ VBattery ≤ VDET_MAXOP 3.21 3.28 3.35 V Battery Detector Voltage Fault, Decreasing VDET RRLBAT = 309kΩ 2.92 V Battery Detector Threshold Hysteresis, Warning or Fault VDET_HYS VDET_MINOP ≤ VBattery ≤ VDET_MAXOP 150 200 250 mV Electrical Characteristics (continued)
Notes: (1) VAD OP is the “Maximum Vsupply” as defined in EIA/JEDEC Standard No. 78, paragraph 2.11. (2) The value of the buck converter disabled battery leakage current is included in the charger section battery leakage since i t cannot be independently measured (because SVIN is tied to BAT internally). The buck converter contribution to this value is also include d in the Buck Converter section for design guidance only. (3) VSYS regulation voltage assumes that V VAD exceeds V VSYS by the VSYS regulator dropout (typically 0.5V at 5mA, for a minimum regulator RDS = 71Ω). If this condition is not met, then VVSYS = VVAD minus the VSYS regulator dropout. (4) I Q-Core is the supply current from the battery for common reference circuits into the BAT pin when either the buck converter or LDO or charger are enabled. (5) t SU_REF is the start-up time of the voltage reference buffer for both the DC-DC buck converter and the LDO, and should be added to the start-up time (tSU-SVOUT or tSU-LVOUT respectively) of the first regulator enabled. In the case of the LDO start-up with the switcher disabled, the LDO start-up time tSU-LVOUT is concurrent with the reference start-up time tSU_REF, and so tSU-LVOUT is specifi ed as typically zero. (6) SVOUT is the buck converter output node, which is the node at which the output inductor is connected to the load. It is th e top of the feedback resistor divider network. See the Typical Application Circuit. (7) To guarantee positive load threshold hysteresis for PSAVE-to-PWM mode switching with SVOUT > 2.2V, contact your Semtech rep resentative for application assistance. (8) If V BAT < VSVOUT_Max / SDCMAX + 150mV, then the maximum output setting is VBAT x SDCMAX + 150mV. Higher output voltage settings are feasible, but are subject to load-dependent dropout. (9) Specified with V BAT = VLVIN. (10) Guaranteed by design. Parameter Symbol Conditions Min Typ Max Units Logic Control Inputs & Status Outputs Battery Detector Sense Leakage (BSEN Current) IBSEN_DET VVAD > VADUVLO, or SEN or LEN high, VBSEN = 4.2V 51 0μ A Battery Detector Activation Delay(10) VDET_DEL Time from fi rst of LEN or SEN high until LBATB/FAULTB valid, VVAD = 0V 70 μs Logic Input Low V IL LEN, SEN; VBAT = 2.7V 0.4 V Logic Input High V IH LEN, SEN; VBAT = 2.7V 1.5 V Logic Input Current High I IL LEN, SEN; VBAT = 2.7V 1 μA Logic Input Current Low I IH LEN, SEN; VBAT = 2.7V 1.5 μA CPB, CHRGB, FLTB, LBATB Outputs VOL ISINK = 2mA 0.5 V IOH V = 5V (VVAD = 8V for CPB) 1 μA Electrical Characteristics (continued)
4.5 5 5.5 6 6.5 74.18 4.181 4.182 4.183 4.184 4.185 4.186 4.187 4.188 4.189 4.19 VVAD (V) VBAT (V) TA = 25οC, IBAT = 50mA 0 50 100 150 200 250 300 350 400 450 5004.18 4.181 4.182 4.183 4.184 4.185 4.186 4.187 4.188 4.189 4.19 IBAT (mA) VBAT (V) TA = 25οC, VVAD = 5V -40 -20 0 20 40 60 80 100 120 1404.172 4.174 4.176 4.178 4.18 4.182 4.184 4.186 Junction Temperature ( o VBAT (V) VVAD = 5V, IBAT = 50mA 175 176 177 178 179 180 181 182 183 184 -40οC 0οC TA = 25οC 85οC VVAD (V) IBAT (mA) VBAT = 3.75V, RIPRGM = 6.04kΩ 176 176.25 176.5 176.75 177 177.25 177.5 177.75 178 178.25 178.5 178.75 179 -40οC 0οC TA = 25οC 85οC VBAT (V) IBAT (mA) VVAD = 5V, RIPRGM = 6.04kΩ 2 4 6 8 10 12 14 16 100 150 200 250 300 350 400 450 500 RIPRGM (kΩ) IBAT (mA) TA = -40, 0, 25, 85 οC, VVAD = 5V, VBAT = 3.75V Charger CV Line Regulation Charger CV Load Regulation Charger CV Temperature Regulation Charger CC VBAT Regulation Charger CC IFQ Programming Charger CC Line Regulation
IBAT (mA) 0.5 1.5 2.5 3.5 4.5 Time (hrs) VBAT (V), Internal Power Dissipation (W) 700mAhr battery, RITERM = 3.48kΩ, VVAD = 5.0V, TA = 25οC, Load = 10mA VBAT IBAT PWR 410 420 430 440 450 460 470 480 490 500 510 IBAT (mA) 56 56.5 57 57.5 58 58.5 59 59.5 60 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 Time (min) VBAT (V) 700mAhr battery, RIPRGM = 2.15kΩ, RITERM = 3.48kΩ, VVAD = 5.0V, TA = 25οC VBAT IBAT 100 150 200 250 300 350 400 450 500 550 IBAT (mA) 0 2 4 6 8 1 01 21 41 61 82 00 0.5 1.5 2.5 3.5 4.5 5.5 Time (s) VBAT (V), Internal Power Dissipation (W) 700mAhr battery, RIPRGM = 2.15kΩ, RITERM = 3.48kΩ, VVAD = 5.0V, TA = 25οC VBAT IBAT PWR 100 150 200 250 300 350 400 450 500 550 IBAT (mA) 0.5 1.5 2.5 3.5 4.5 5.5 Time (hrs) VBAT (V), Internal Power Dissipation (W) 700mAhr battery, RIPRGM = 2.15kΩ, RITERM = 3.48kΩ, VVAD = 5.0V, TA = 25οC VBAT IBAT PWR Typical Characteristics (continued) 2 4 6 8 10 12 14 16 18 200 -40οC 25οCTA = 85οC RITERM (kΩ) IBAT (mA) VVAD = 5V, VBAT = 2.6V Charger IPreQ Line Regulation 38.5 39.5 40.5 41.5 -40οC 0οC TA = 25οC 85οC VVAD (V) IBAT (mA) VBAT = 2.6V, RITERM = 4.99kΩ Charger IPreQ Programming Charging Cycle Battery Voltage and Current Pre-Charging Battery Voltage and Current CC-to-CV Battery Voltage and Current Re-Charge Cycle Battery Voltage and Current
1.796 1.797 1.798 1.799 ILVOUT = 10mA ILVOUT = 50mA ILVOUT = 100mA ILVOUT = 150mA VLVIN (V) VLVOUT (V) RL1 = 54.9kΩ, RL2 = 39.2kΩ, TA = 25οC 0 20 40 60 80 100 120 1401.797 1.7975 1.798 1.7985 1.799 ILVOUT (mA) VLVOUT (V) RL1 = 54.9kΩ, RL2 = 39.2kΩ, TA = 25οC, VLVIN = 3.75V -40 -20 0 20 40 60 80 100 1201.77 1.775 1.78 1.785 1.79 1.795 1.8 ILVOUT = 10mA ILVOUT = 50mA ILVOUT = 100mA ILVOUT = 150mA Junction Temperature ( o VLVOUT (V) RL1 = 54.9kΩ, RL2 = 39.2kΩ, VLVIN = 3.75V LDO Line Regulation LDO Load Regulation LDO Temperature Regulation LDO PSRR, LVIN to LVOUT LDO PSRR, LVIN and BAT to LVOUTLDO PSRR, BAT to LVOUT 10 100 1000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 Frequency (Hz) LDO PSRRLLVIN (dB) TA = 25οC, VLVOUT = 1.8V, VLVIN = 3.7VDC + 0.5VAC, VBAT = 3.7V 10 100 1000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 Frequency (Hz) LDO PSRRBAT (dB) TA = 25οC, VLVOUT = 1.8V, VLVIN = 3.7VDC, VBAT = 3.7VDC + 0.5VAC 10 100 1000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 Frequency (Hz) LDO PSRRLBAT (dB) TA = 25οC, VLVOUT = 1.8V, VLVIN = VBAT = 3.7VDC + 0.5VAC
Typical Characteristics (continued) 2.18 2.19 2.2 2.21 2.22 2.23 ISVOUT = 10mA ISVOUT = 35mA ISVOUT = 100mA ISVOUT = 150mA PSAVE Mode PWM Mode VBAT (V) VSVOUT (V) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), TA = 25οC -40 -20 0 20 40 60 80 100 1202.18 2.19 2.2 2.21 2.22 2.23 ISVOUT = 10mA ISVOUT = 35mA ISVOUT = 100mA ISVOUT = 150mA PSAVE Mode PWM Mode Junction Temperature ( o VSVOUT (V) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), VBAT = 3.7V DC/DC Converter Line Regulation DC/DC Converter Load Regulation DC/DC Converter Effi ciencyDC/DC Converter Temperature Regulation 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 15085 ISVOUT (mA) Efficiency (%) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), VBAT = 3.6V, L = 4.7 μH PSAVE Mode PSAVE Mode PWM Mode PWM Mode 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 1502.15 2.16 2.17 2.18 2.19 2.2 2.21 2.22 2.23 2.24 2.25 Increasing LoadDecreasing Load ISVOUT (mA) VSVOUT (V) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), TA = 25οC, VBAT = 3.7V DC/DC Converter Effi ciency Detail 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 1500 100 ISVOUT (mA) Efficiency (%) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), VBAT = 3.6V, L = 4.7 μH PSAVE Mode PWM Mode DC/DC Converter Effi ciency — Low Loads 1 10 100 0 100 ISVOUT (mA) Efficiency (%) VSVOUT = 2.2V (RS1 = 340kΩ, RS2 = 100kΩ), VBAT = 3.6V, L = 4.7 μH
Pin # Pin Name Pin Function 1V A D Charger input pin 2 VSYS Adapter input internal-regulation node which also serves as supply for EN_NTC, RTIME, and all input-referenced (vs. battery-referenced or regulated output-referenced) pull-ups; load must not exceed 5mA. 3 IPRGM Pin for setting constant current charging current — connect resistor to ground to set current. 4 ITERM Pin for setting termination and precharge current — connect resistor to ground to set current. 5 RTIME Charge timer pin — connect a resistor to ground to set timer, ground to disable the timer. Timer enabled with internally programmed default time is selected with RTIME tied to VSYS. 6 RLBAT Resistor is connected to ground to set Low Battery voltage threshold. 7 LVIN LDO voltage input — can be connected to either the battery supply (BAT) or the switching regulator output (SVOUT). No other connections are permitted.
8 LVOUT LDO voltage output
9 LFB LDO feedback voltage input
10 VREF Bandgap reference bypass pin — connected to a 10nF capacitor to analog ground. No other connections are permitted. 11 AGND Analog ground pin — refer to grounding considerations in application section. 12 DGND Digital ground pin — refer to grounding considerations in application section.
13 LEN LDO enable pin — active high
14 SFB
DC-DC converter feedback input — connect voltage divider from output to this pin to set output voltage. 15 FLTB Charging Fault indicator — open drain output is active low when a charging fault has occurred. Also, together with LBATB, indicates when battery discharges below a programmable voltage set by RLBAT resistor. 16 LBATB Low Battery indicator — open drain output is active low when battery discharges below 3.3V, and, together with LBATB, indicates when battery discharges below a programmable voltage set by RLBAT resistor. 17 CPB Charger Present indicator — open drain output is active low when a valid VAD input voltage is present.
18 SEN DC-DC converter enable pin — active high
19 CHRGB
Charging-In-Progress indicator — open drain output is active low when charging until charging current drops below the programmed termination current, or until charging is disabled by charge timeout or EN_NTC disable or NTC temperature fault.
20 PGND
DC-DC converter power ground pin — No other connection is permitted. 21 SLX DC-DC converter output — connect to an inductor between this point and SVOUT (the DC-DC converter load con- nection). 22 BAT Charger output pin, also DC-DC converter input pin — connect to the positive battery terminal. 23 EN_NTC NTC thermistor input — charger is enabled if voltage is between 0.3 × VSYS and 0.75 × VSYS. Charger is disabled if voltage is below 1V. Battery temperature fault otherwise. 24 BSEN Battery Kelvin sense pin — independent connection is tied directly to the battery positive terminal. T Thermal Pad Connect to ground plane with thermal vias directly under pad.
Block Diagram With Typical Application Circuit LDO Fast Charge Ref Pre-Charge Ref BAT IPRGM ITERM DGND EN_NTC CHRGB VSYS 4.2V Fast Charge Ref Pre-Charge Ref RTIME Pre-Charge On Fast Charge On Over Temp Under Voltage Over Voltage VTH-hot (0.3VCC) VTH-cold (0.75VCC) RIPRGM CVOUT VREF VREF LVIN LVOUT LEN SEN SFB PGND SVIN SLX AGND RRTIME RNPU RNTC FLTB LBATB CLVIN CPB CVREF VREF LFB RLBAT RITERM BSEN VSYS Regulation CVSYS RRLBAT VAD CVADQpass Qterm VSYS Reference Voltages Timer NTC Interface Control Buck Converter Control Block LDO Supply from battery or SVOUT 1412 Charging Adapter 20 LS CSVOUT SVOUT RS1RS2 CSFB CLVOUT RL1 RL2 CSFG
The SC908 Li-Ion battery charger can be confi gured inde- pendently with respect to fast-charge, termination current, and timing. The charging and battery voltage status are indicated by the four status outputs. A charge cycle is initiated when the power adapter is con- nected to the device and the SC908 VAD pin voltage is between the Under-Voltage LockOut (UVLO) rising thresh- old and the input Over Voltage Protection (OVP) threshold. If the battery voltage is less than the pre-charge threshold, the output current is regulated to the programmed pre- charge current. When the pre-charge threshold voltage is exceeded, the fast-charge Constant Current (CC) mode begins, with the charge current rising to the programmed fast-charge current in three soft-start current steps. The charger enters the Constant Voltage (CV) mode when the battery voltage rises to its fi nal value (V CV), typically 4.2V. In the CV mode the BAT voltage is regulated to VCV, and as the battery continues to charge it accepts decreasing current. The CHRGB output turns off when I BAT drops below the programmed termination current. If the charge timer is active, the battery is held in the CV charge mode until the timer cycle ends. The charger then enters the monitor mode, where the output remains off until the voltage at BAT drops by VT ReQ, and a new charge cycle is initiated. If the charge timer is disabled, the monitor mode is immediately entered upon charge termination. Pre-Charge Mode The pre-charge mode is automatically entered when the battery voltage is below the pre-charge threshold voltage, which preconditions the battery for fast charging. The pre-charge current value is set by the resistor on the ITERM pin, and is programmable from 14mA to 65mA. The pre- charge current is determined by 130R VI ITERM Typ_ITERM eQPr u where VITERM_Typ designates the typical value of VITERM. (See the Termination Current section for precharge current accuracy.) When the timer is enabled, there is a maximum allowed pre-charge duration. If the pre-charge time exceeds 25% of the total charge cycle, the charger will turn off due to a pre-charge fault. This fault is cleared when VAD is cycled off and on, or when the EN_NTC pin is forced low to disable the charger. Fast-Charge Constant Current Mode The fast-charge CC mode is active when the battery voltage is above VT PreQ and less than VCV. The current can be set to a maximum of 0.5A and is selected by the program resistor on the IPRGM pin. The voltage on this pin represents the charger output current. This allows the charging current to be measured by sensing the IPRGM pin voltage using a general purpose Analog-to- Digital Converter (ADC) and the host microporocessor. The fast-charge current is determined by 697R VI IPRGM Typ_IPRGM FQ u Excellent fast-charge current accuracy is obtained by the use of a patented polarity-switched current sense amplifier (US Patent 6,836,095). This nullifies current measurement offset errors, leaving only a small gain error. The range of expected fast-charge output current versus programming resistance R IPRGM is shown in Figures 1a and 1b. 2 2.5 3 3.5 4 4.5 5 5.5 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 520 RIPRGM (kΩ) Fast Charge Current (mA) Figure 1a — Fast-charge Current Variation vs. IPRGM Resistance, Low Resistance Range Applications Information
the battery voltage falls below the recharge threshold (VCV - VReQ), the charger will clear the charge timer and ini- tiate a charge cycle. The status of the charger output as a function of the Charge Complete timer status and I BAT is shown in Table 1. Timer Iout Output State t < Timeout N/A On t > Timeout N/A Off Disabled < I termination Off Table 1 — Charger Output Status Remote Kelvin Sensing at the Battery The BSEN pin provides for Kelvin sensing of the battery positive terminal voltage. This prevents feedback error due to charging, battery load, and switching regulator input currents fl owing over resistive PCB traces. Optimal PCB layout routes the BSEN trace directly to the battery positive terminal connection on the PCB to achieve the most accurate sensing of battery cell voltage. Connecting BSEN to BAT directly at the SC908 will intro- duce battery voltage measurement error that can cause an improper transition from CC to CV regulation, length- ening the charge time. This error could also raise or lower the final battery voltage, and may alter the final state-of-charge. EN_NTC Interface The EN_NTC pin is the interface to a battery pack temper- ature sensing Negative Temperature Coefficient (NTC) thermistor, which can be used to suspend charging if the battery pack temperature is outside of a safe-to-charge range. It is also the charger-disable input. The typical EN_NTC network is a fixed resistor from VSYS to the EN_NTC pin, and the battery pack EN_NTC thermistor from the EN_NTC pin to ground. In this confi guration, an increasing battery temperature produces a decreasing NTC pin voltage. When V EN_NTC is greater than the high (cold) threshold or less than the low (hot) threshold, the charge cycle is sus- pended by turning off the output. This suspends but does not reset the charge timer, and indicates a fault on the FLTB pin. Hysteresis is included for both high and low RITERM (kΩ) Precharge/Termination Current (mA) Figure 2b — Pre-charge and Termination Current Variation vs. ITERM Resistance, High Resistance Range Charge Timer The timer provides over-charging protection in the event of a faulty battery and maximizes charging capacity. The RTIME pin is connected to VSYS to select the internal (default) time duration of three hours, and to GND to disable the timer. Connecting a resistor between RTIME and GND will program the Charge Complete Time-Out, in hours, according to the equation 3600 334.3 Rt RTIME QComp u The timer is programmable over the range of 2 to 6 hours. The output is automatically turned off when the charge timer cycle ends. If the charge cycle remains in precharge for longer than one fourth of the Charge Complete Time-Out period, a charging fault is detected and the charger turns off . The Precharge Fault Time-Out period, in minutes, is 604 tt QComp eQFPr u Monitor Mode When a charge cycle is complete (termination if the timer is disabled, charge timeout if the timer is enabled), the output turns off and the device enters monitor mode. If Applications Information (continued)
Applications Information (continued) NTC thresholds to avoid chatter at the NTC fault thresh- olds. When VEN_NTC returns to the valid range, the charge timer resumes and the charge cycle continues. The charge timer will expire when the output on-time exceeds the timer setting, regardless of how long it has been disabled due to an NTC fault. Using the recommended NTC external network, the EN_NTC pin voltage and the internal hot and cold NTC thresholds are all ratios of V VSYS, rather than absolute volt- ages. This ensures that the hot and cold OK-to-charge thresholds are insensitive to the VSYS pin output voltage. The ratiometric thresholds are given by the parameters RT NTCH and RT NTCC. EN_NTC pin voltage V EN_NTC between RTNTCH×VVSYS and RTNTCC×VVSYS enables charging. When VEN_NTC is outside this range, charging is suspended and the FLTB output is asserted (pulled low). When V EN_NTC < VTNTCDIS (nominally 0.6V), the SC908 charger is disabled. The EN_NTC pin can be pulled to ground by an external n-channel FET or microprocessor GPIO to asnychronously disable or reset the device. When V EN_NTC < VTNTC_DIS, the charger is turned off , the charge timer is reset, and the CHRGB status output is turned off . While disabled, the VAD input UVLO and OVP threshold detectors remain active, and the CPB pin continues to indicate whether the VAD input voltage is valid for charging. The response of the SC908 to an EN_NTC pin voltage above the high threshold or below the low threshold (but above VT NTCDIS) is the same. Therefore the EN_NTC network can be configured with the battery pack thermistor between EN_NTC and VSYS, and a fi xed resistor between EN_NTC and ground. This confi guration may be used to reset the charge timer (and the CHRGB output) when the battery pack is removed; the fi xed resistor pulls the NTC pin to ground to disable the charger without indicating a fault. NTC Design Example This example uses the conventional NTC network confi gu- ration shown in the block diagram. A fi xed resistor (RNPU) is connected between EN_NTC and VSYS, and a battery NTC thermistor (R NTC) is connected between the EN_NTC pin and ground. The battery temperature range over which charging is permitted is from 0°C to 40°C. The data- sheet for the proposed NTC thermistor, the Mitsubishi TH11-3T223F, indicates that R NTC = 11.93k Ω at 40°C, and RNTC = 69.41k Ω at 0°C, with a dissipation constant Step 1 Select R NPU to obtain one of the desired temperature thresholds. This example will solve for the hot threshold for the normal (NTC thermistor to ground) confi guration, then evaluate the cold threshold. Solve the NTC network voltage divider for R NPU to place the NTC voltage at RTNTC_HF × VVSYS when RNTC = RHOT. HOTNPU HOTVSYS VSYSHF_NTC RR RVVRT u u or, solving for RNPU, HOT HF_NTC HF_NTC NPU RRT RTR u 1 Using RT NTC_HF = 0.3, we obtain R NPU = 27.837k Ω exactly. The closest 1% standard nominal value is RNPU = 28.0kΩ. Step 2 Evaluate the NTC network at the cold threshold. Compute the NTC network resistor divider voltage as a function of V VSYS at the desired cold threshold. VSYS COLDNPU COLDVSYS COLD V7126.0RR RVNTC u u The value 0.7126 should be close to the nominal value of RT NTC_CR = 0.75. To evaluate the signifi cance of the discrep- ancy, an estimate of the actual cold threshold is obtained by evaluating the value of R NTC_Cold_Actual that produces the nominal value of RT NTC_CR = 0.75. NPUActual_Cold_NTC Actual_Cold_NTC CR_NTC RR RRT The solution shows RNTC_Cold_Actual = 84.0kΩ. Examination of the thermistor specifi cation resistance versus temperature data indicates that the resulting actual cold threshold is approximately -4°C, compared to the target of 0°C.
Applications Information (continued) Step 3 With the example thermistor, there is no choice of R NPU that will yield the specifi ed results at both hot and cold limits. A more sensitive thermistor, one with a wider per- centage variation in resistance at the desired threshold temperatures, may provide a better solution. Steps 1 and 2 are repeated using other devices from the same vendor, seeking a closer match at the cold threshold. The Mitsubishi TH11-4C153F was the fi nal selection. Its characteristics are: R HOT is 7.73kΩ (at 40°C), RCOLD is 53.94kΩ (at 0°C). Its dissipation constant DC = 3.0mW/°C. Step 1 yields R NPU = 18.2kΩ, with the result that NTC COLD/VVSYS = 0.748 ≈ RTNTC_CR, NTCHOT/VVSYS = 0.298 ≈ RTNTC_HF. The NTC resistances that give the exact cold and hot thresholds RT NTC_CR and RT NTC_HF are 54.6kΩ (which is R NTC at approxi- mately -0.5°C) and 7.80kΩ respectively, closely matching the resistance of the thermistor at the targeted threshold temperatures. Step 4 Verify acceptable thermistor self heating. The dissipation constant is the power rating of the thermistor resulting in a 1°C self heating error. Since accuracy is important only at the thresholds, self heating is assessed only at 0°C and 40°C. For V VSYS = 4.6V, the 0°C NTC network current is INTC_COLD = VVSYS/(RNPU + RCOLD) = 63.8μA Power dissipation in the thermistor at this temperature is PCOLD = RCOLD × (INTC_COLD)2 = 0.219mW The self heating error is C073.03 mW219.0T CmWCOLD_SH q The 40°C NTC network current INTC_HOT = VVSYS/(RNPU + RHOT) = 0.177mA Power dissipation in the thermistor at this temperature is PHOT = RHOT × (INTC_HOT)2 = 0.243mW for self heating of approximately 0.081°C. The actual cold and hot thresholds will be 0.073 and 0.081 degrees lower than designed, respectively, which are negligible errors. Logical CC-to-CV Transition The SC908 diff ers from most monolithic linear single cell Li-Ion chargers, which implement a linear transition from CC to CV regulation. The linear transition method uses two simultaneous feedback signals — output voltage and output current — to the closed-loop controller. When the output voltage is sufficiently below the CV regulation voltage, the infl uence of the voltage feedback is negligible and the output current is regulated to the desired current. As the battery voltage approaches the CV regulation voltage (4.2V), the voltage feedback signal begins to infl u- ence the control loop, which causes the output current to decrease although the output voltage has not reached 4.2V. The output voltage limit dominates the controller when the battery reaches 4.2V and eventually the control- ler is entirely in CV regulation. This system may be characterized as a dual-constraint (voltage and current) controller, with a soft transition between constraints. The soft transition effectively reduces the charge current below that which is permitted for a portion of the charge cycle, which increases charge time. In the SC908, a logical transition is implemented from CC to CV to recover the charge current lost due to the soft transition. The controller regulates only current until the output voltage exceeds the transition threshold voltage. It then asynchronously switches to CV regulation. The transition voltage from CC to CV regulation is typically less than 10mV higher than the CV regulation voltage, which provides a sharp and clean transition free of chatter between regulation modes. The diff erence between the transition voltage and the regulation voltage is the CC/CV overshoot. While in CV regulation, the output current is limited to approximately 105% of the fast-charge current programmed by the IPRGM pin or the IPUSB pin, depend- ing on the charging input selected, providing mode transition hysteresis. If the output current exceeds this current limit threshold, the controller asynchronously reverts to current regulation. The logical transition from CC to CV results in the fastest possible charging cycle that is compliant with the speci-
fi ed current and voltage limits of the Li-Ion cell. The output current is constant at the CC limit, then decreases abruptly when the output voltage steps from the overshoot voltage to the regulation voltage at the transition to CV control. This can be compared to voltage and current trajectories for other monolithic charger devices to show the softness of the linear crossover. This explains the charge-time advantage of the SC908 logical crossover method. Charger Protection Features The protection features are: Short Circuit Protection Over Current and Max Temperature Protection Input Overvoltage Protection Thermal Protection Short Circuit Protection The BAT output can tolerate an indefi nite short circuit to ground. The current into a ground short will be equal to the precharge current. The ITERM pin voltage prior to termination, and the IPRGM pin voltage while in CC mode, are regulated to 1.5V. Precharge current and termination current are propor- tional to the resulting ITERM current, and CC current is proportional to the resulting IPRGM current. High battery current is prevented by pinshort detectors on both pro- gramming pins. Pinshort detection asynchronously forces the charger into reset, turning off the output and clearing the charge timer. When the pinshort condition is removed, the charger begins normal operation automatically. Over Current and Max Temperature Protection Over current protection is provided in all modes of opera- tion. When the device is in the charge mode the output is current-limited to either the programmed pre-charge current or the programmed fast charge current, depend- ing on the voltage at the output. Junction over-temperature protection allows operation with maximum power dissi- pation by disabling the charger output current when the die temperature reaches the maximum operating tem- perature. This results in operation as a pulse charger in extreme power dissipation applications, delivering the maximum allowable output current while limiting the internal die temperature to a safe level. Input Over-Voltage Protection The VAD input is protected from adapter over-voltage to at least 28V above V DGND. When VVAD exceeds its OVP rising threshold VADOVP-R the charger turns off its output while the charge timer continues to run, and the FLTB status indicator is asserted. When V VAD subsequently falls below the VAD OVP falling threshold VADOVP-F, charging continues normally and FLTB is released. Thermal Protection The charger’s internal over-temperature (OT) threshold is set to approximately 145°C. If the temperature exceeds this threshold prior to termination, the charger output is turned off . All other functions remain active, the charger logical state is preserved, and no fault is indicated. This allows thermal pulse charging in conditions of high power dissipation. Following termination, a charger OT condi- tion will be indicated as a fault. Refer to the Indicator Flags subsection for more information. A second high OT threshold is set to approximately 165°C. Should the die temperature exceed this threshold, all SC908 functions are disabled, and the status outputs indi- cate an exceptional condition fault. Refer to the Indicator Flags subsection for more information. Low Battery Detector Operation The low battery detector provides two low battery detec- tion voltage thresholds: a fi xed warning threshold and a resistor programmable detection (shutdown request) threshold. The low battery detector is enabled when either the buck converter is enabled (SEN is high) or the LDO regulator is enabled (LEN is high). The warning and shutdown request are provided by the status output pins FLTB and LBATB, as described in the Status Outputs sub- section. When a charging adapter is present (V VAD > VADUVLO-x), the FLTB and LBATB outputs are redefi ned to reflect the interaction of battery voltage and charging state. The low battery detector warning threshold is fixed at 3.28V ± 70mV. The battery voltage fault threshold is pro- grammable, with a resistor from the RLBAT pin to ground, Applications Information (continued)
Applications Information (continued) from 2.77V to 2.98V, ±10%. The low battery fault threshold is set by the relationship VDET = 3.9 μA × RRLBAT × 2.42 RRLBAT must satisfy the condition 294kΩ ≤ RRLBAT ≤ 316kΩ Connect RLBAT to GND to disable the Low Battery Detector fault. The Low Battery Detector warning remains active. Status Outputs Four charger status outputs/LED drivers are provided. CPB (Charger Present) CHRGB (Charge Active) FLTB (Fault) LBATB (Low Battery Warning) These outputs are active-low, open drain NMOS drivers capable of sinking up to 2mA each. The state of each, in various operating conditions, is defined in Tables 2, 3, and 4. When the VAD voltage is below its UVLO threshold (no charging adapter is present), the CPB and CHRGB outputs are off (high impedance). The FLTB and LBATB outputs indicate the battery voltage as defi ned in Table 2. When VVAD is between its UVLO and OVP thresholds, V VAD is valid to charge, and the CPB output is low indicating that a charging adapter is present. The CHRGB output indicates the battery charging status. The charger-present status output states are described in Table 3. When pre-charging or when the output current (mutually exclusive) Battery Voltage (mutually exclusive) CPB CHRGB FLTB LBATB VVAD < VADUVLO VADUVLO < VVAD < VADOVP VVAD > VADOVP VBSEN ≥ VWARN VWARN > VBSEN > VDET VDET ≥ VBSEN on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition off off off off T T No Charging Adapter, Battery Voltage Good off off off on T T No Charging Adapter, Low Battery Voltage Warning off off on on T T No Charging Adapter, Low Battery Shutdown Request
Applications Information (continued) The fault modes signaled by FLTB are: input over-voltage battery NTC temperature out of range pre-charge timeout. charger-only over-tempera ture (low OT, post- termination only) When any of these conditions occurs the FLTB output goes low; otherwise it remains high impedance. The LBATB output is active when the battery voltage is below the low-battery warning voltage, VWARN, if the charg- ing adapter is absent. If CPB and CHRGB outputs are both active, LBATB indicates when the charger is in precharge mode. However, LBATB and FLTB active together always Table 3 — Status Output State, Charging Adapter Present Status Pins Output State (on = low) Conditions (mutually exclusive) Battery Voltage (mutually exclusive) EN_NTC (mutually exclusive) Charging State, Charging Faults (Internal signals) CPB CHRGB FLTB LBATB VVAD < VADUVLO VADUVLO < VVAD < VADOVP VVAD > VADOVP VBSEN ≥ VWARN VWARN > VBSEN > VDET VDET ≥ VBSEN Disable NTC OK NTC Hot or Cold Charger OT BAT Short-to-GND Pre-Charging Pre-Term Charging Pre-Charge Timeout on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition on off off off TT T- - - - F V VAD valid, Charger Disable/Reset OR Charging Done (Die Temperature OK)F-- FF F F on off off on T T T -- - - F VVAD valid and Low Battery Warning, Charger Disable/Reset OR Charge Cycle Pending (about to begin)T on off on off T- - F F-- F V VAD valid, Battery Temperature Fault OR Charger Over-Temp Fault (Die Temp > T CHRGR_OT)TT on off on on T T T- - - - F VVAD valid, Low Battery Detected, with either Charger Disable/Reset OR Battery Temperature Fault OR Charger Over-Temp Fault OR BAT short-to-ground T-- - - TT - F F F-- - T -- on on off off T- - FT - F F T F V VAD valid, Pre-termination Charging, Battery Voltage > VDET on on off on T - - F T F F T T F VVAD valid, Pre-Charging (trickle charging), Battery Voltage > VDET on on on off T- - FTT F T T F VVAD valid, Pre-Charging with Charger Over-Temp Fault, Battery Voltage > VDET on on on on T T T - F - T F VVAD valid, Battery Voltage < VDET Pre-Charging or Pre-Termination Charging
Applications Information (continued) indicates that the battery voltage is below the low-battery detect threshold, V DET. Table 3 gives a comprehensive description of all combinations of status output states while the adapter input is valid for charging. Exceptions to these charging conditions occur when certain events happen in combination. Table 4 describes status condition exceptions. These exceptions include V VAD > OVP threshold; a high over temperature condition, in which device temperature exceeds the higher of two over-temperature thresholds, causing charging and both regulators to be disabled; a precharge timeout, which may indicate a faulty battery. VSYS pin The voltage of the VSYS pin is regulated from the VAD input and is present only when VAD is powered. VSYS provides an external voltage reference and supply for the NTC network, and a pull-up supply voltage for the CPB status indicator. A capacitor of at least 0.1uF should be con- nected from VSYS to ground near the pin. The load on VSYS should not exceed 5mA. If CHRGB is used to operate an indicator LED, it is recommended that the CHRGB status pin be pulled up to the battery or to a battery-powered regulated supply. Since CHRGB is asserted only while charging the battery, the current sunk by CHRGB will be sourced by the charger output and will not discharge the battery. Because VSYS is powered from VAD, it is unsuitable as a pullup source for the FLTB and LBATB status pins. These status pins must be powered from the battery or battery- powered regulated supply to function as battery level indicators when the charging adapter is not present. Capacitor Selection Low cost, low ESR ceramic capacitors such as the X5R and X7R dielectric material types are recommended. The BAT pin capacitor, C BAT, range is 1μF to 22μF. This capacitor functions as both the charger output capacitor and as the switching regulator input capacitor. The VAD pin input capacitor C VAD is typically between 0.1μF to 2.2μF; however, larger values will not degrade performance. Status Pins Out- put State (on = low) Conditions (mutually exclusive) Battery Voltage (mutually exclusive) EN_NTC (mutually exclusive) Charging State, Charging Faults (Internal signals) CPB CHRGB FLTB LBATB VVAD < VADUVLO VADUVLO < VVAD < VADOVP VVAD > VADOVP VBSEN ≥ VWARN VWARN > VBSEN > VDET VDET ≥ VBSEN Disable NTC OK NTC Hot or Cold Charger OT, (High OT) BAT Short-to-GND Pre-Charging Pre-Term Charging Pre-Charge Timeout on = open drain output driver is active off = output is not active T = listed condition is true F = listed condition is false - = don’t care Blank = mutually exclusive with another condition off off on off T T - - --- - - F VAD Overvoltage, Battery Voltage Good or WarningT off off on on T T - - - - - - - F VAD Overvoltage, Low Battery Detect temperature > T OT; all functions shutdown.) off o n o n o n F-----F-- - --- T Pre-charge Timeout, NTC Not Disable, Adapter Voltage Good or OVP Table 4 — Status Output State, Exception Conditions
Applications Information (continued) LDO Regulator The low-noise low-dropout (LDO) voltage regulator oper- ates from an LVIN pin input voltage range of 2.2V up to the battery voltage (V BAT), and an output voltage from 1.5V to 3.3V, programmable with external resistors. The SC908 has a VREF bypass pin to enable the user to capacitively decouple the bandgap reference (10nF recommended) for very low output noise (50μV RMS typically). The output voltage of the LDO regulator is divided exter- nally using a resistor divider and compared to the buff ered bandgap voltage, typically 0.75V. The error amplifier drives the gate of a low R DS(ON) P-channel MOSFET pass device. Enabling the LDO The LDO has an independent enable input pin (active high). The LDO can be enabled only if V LVIN ≥ VTLUVLO, typi- cally 2.0V, although performance specifications are guaranteed for V LVIN ≥ 2.2V. The LDO output will settle to within 5% of its fi nal value in 0.1ms (typically) when the bandgap reference buff er has already settled (when the switching regulator is already enabled, or when the charg- ing adapter is present). A fast start-up circuit is used to speed the initial charging time of the VREF pin bypass capacitor. This is done so that the LDO output voltage will settle to within 5% of its fi nal value in 0.4ms (typically) when the LDO is the first resource enabled. When the battery charger is in its precharge mode of operation (trickle charging of a deeply discharged battery), the LDO enable signal will be disregarded until fast-charging begins (at a battery voltage of 2.8V typically). An excep- tion occurs when either the LDO or switching regulator are already enabled. At this time when a charging source is applied and the charger enters precharge mode, the LDO will remain enabled (or can become enabled). Precharge mode is indicated by the status outputs. (Refer to Table 3.) The LDO provides active shutdown. The capacitance on LVOUT will be discharged by an on-chip FET when the LDO is disabled. Programming the LDO Output Voltage The LDO regulates its output to obtain 0.75V at the LFB pin. The output can be programmed to any voltage from 1.5V to 3.3V by an external resistor divider network from LVOUT to LFB. The output voltage is set by § u /)%/9287 599 LFB is a high impedance input, so large value resistors, even on the order of 500k Ω, may be used to meet the noise specifi cation. When considering the eff ect of LDO load current on performance specifi cations, the current flowing in the feedback divider network should be included in the load. The LDO is internally compensated. No feedback capacitor is required for stability. LDO Dropout The LDO dropout voltage is the product of the minimum R DS(ON) of the P-channel MOSFET pass device and the LDO output current. As VLVIN decreases, the achievable source- to-gate voltage of the pass device decreases, so the minimum achievable R DS(ON) becomes larger. This is the reason for the two-tier dropout specifi cation. Minimum RDS(ON) increases with die temperature, which is aff ected not only by LDO power dissipation, but also by switching regulator and charger power dissipation. The maximum dropout is specifi ed for a temperature of 85°C. LDO Reference Voltage The internal bandgap reference voltage must be exter- nally bypassed to meet the LDO noise specifi cation. A 10nF ceramic capacitor from the VREF pin to AGND is rec- ommended to bypass the bandgap reference buffer. Increasing this capacitor to 100nF will improve power supply rejection, but at the cost of slower turn-on settling time. All noise and turn-on settling time specifi cations assume that the VREF bypass capacitor is 10nF. Low cost, low ESR ceramic capacitors such as the X5R and X7R dielectric material types are recommended. The bandgap reference is trimmed and buff ered to obtain 0.75V typically at the LFB pin with respect to AGND while the LDO is operating. V VREF is the reference voltage for LFB, so VVREF will be equal to V LFB within the off set error of the LDO feedback error amplifi er. The bandgap reference and reference buffer are powered from the greater of V VSYS (derived from VAD, when present) and V BAT (the battery voltage). The PSRRREF specifi cation is with respect to V BAT. It is evaluated while the charging adapter is not present.
Applications Information (continued) VREF power supply rejection with respect to VAD will be similar. The VREF pin is a high impedance source. Any load on VREF will degrade LDO and switching regulator voltage accuracy. Note that the 10MΩ impedance of a typical oscilloscope probe is not large enough to prevent loading of the VREF pin. LDO Power Supply Rejection Power supply rejection must be considered with respect to two inputs. The buff ered bandgap reference is powered by the greater of two possible sources, V VSYS (an internal/ external supply voltage, derived from VAD when present) and V BAT. The LDO is powered from the LVIN pin. PSRRL is defi ned as the power supply rejection from LVIN to LVOUT with the reference and reference buff er powered from BAT as DC voltage. The reference voltage VREF power supply rejection specifi cation (PSRR REF) is with respect to BAT. Any reference voltage power supply noise or ripple is seen in the LDO as noise on the LFB reference voltage. This noise is then gained-up to the output by the reciprocal of the LFB divider network, or by the gain (1 + R L1/RL2). In the special case V LVIN = VBAT (the LVIN pin is connected directly to the battery), the power supply rejection of the LDO, PSRR LBAT, is determined by § u¸¸ PSRR PSRR 10LBAT LREF 1010R R1log20PSRR LDO Current Limit and Short-Circuit Protection The LDO regulator has current limit circuitry to ensure that the output current will not damage the device during output short-circuit to ground, overload, or start-up. The current limit is guaranteed to be greater than 200mA to allow fast charging of the output capacitor and for high transient load currents. LDO Input and Output Capacitor A minimum LDO input and output capacitance of 1μF with a maximum equivalent series resistance (ESR) of less than 1Ω over temperature is recommended. Increasing the output capacitance will further reduce output noise and improve load transient response. A larger input capacitor will reduce input droop due to load transients, improving overall load transient response, and may also improve input supply rejection. Switching Regulator The SC908 contains a synchronous step-down Pulse Width Modulated (PWM), DC-DC converter (also referred to as a Buck Converter or Switcher) with integrated power devices. The switching frequency is set nominally to 1MHz, allowing the use of small inductors and capacitors. The current limit of the internal PMOS switch (I LIM_P), allows a DC output current of at least 150mA with appropriate external components. For maximum effi ciency over the full load range, the switcher will automatically operate in Power Save (PSAVE) mode with light loads, and in PWM (normal switching) mode for heavier loads. The voltage feedback loop uses an external feedback divider. An internal synchronous NMOS low side switch is used. An external Schottky diode on the LX pin is not required. Switcher Programmable Output Voltage The buck converter regulates its output to obtain 0.5V at the SFB pin. The output can be programmed to any voltage from 1.0V to 3.0V by an external resistor divider network from the external circuit node SVOUT to the SFB pin. The equation for setting the output voltage is § u 6)%69287 599 SFB is a high impedance input, therefore the magnitude of resistances used will be determined by a trade off between feedback network current and product design practice. A 25pF feedback capacitor, designated C SFB, is required for stability in PWM mode. When considering the effect of buck converter load current on performance specifi cations, the current fl owing in the feedback divider network should be included in the load. In most situations, PSAVE mode operation will require a capacitor from SFB to AGND. Refer to the PSAVE mode description. Switcher Power Save (PSAVE) Mode Operation The PSAVE mode is automatically activated or deactivated with light to heavy loads, maximizing effi ciency across the
The inductor should have a low DCR to minimize the con- duction losses and maximize effi ciency. As a minimum requirement, the DC current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple as shown by the equation S S L )MAX(OUT)Peak(L III ' Final inductor selection will depend on various design considerations such as effi ciency, EMI, PSAVE entry, size and cost. C BAT Selection CBAT functions as both the charger output capacitor and as the switching regulator input capacitor. The source input current to a buck converter is non-continuous. To prevent large input voltage ripple a low ESR ceramic capacitor is required. A minimum value of 10μF should be used for sufficient input voltage filtering and a 22μF should be used for improved input voltage fi ltering. C SVOUT Selection The internal compensation is designed to operate with a minimum output capacitor value of 10μF. Larger output capacitor values will improve transient performance. Output voltage ripple is a combination of the voltage ripple from the inductor current charging and discharging the output capacitor and the voltage created from the inductor current ripple through the output capacitor ESR. Selecting an output capacitor with a low ESR will reduce the output voltage ripple component, as can be seen in the equation SVOUTS C)ripple(L)ESR(SVOUT ESRIV u' ' Capacitors with X7R or X5R ceramic dielectric are recom- mended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coeffi cients make them unsuitable for this application. When selecting an output capacitor, it is essential that C SVOUT capacitance be evaluated at the VSVOUT programmed voltage. The specified capacitance of 0402, and even 0603, package size devices is often severely derated at just Switcher Protection Features The protection features are: Current limit Over-voltage protection Soft-start Current Limit The PMOS power device in the buck switcher stage is pro- tected by a current limit function. If a short to ground on the output occurs, the part enters frequency foldback mode, which causes the switching frequency to divide by a factor determined by the output voltage. This prevents the inductor current from stair-casing. Over-Voltage Protection In the event of over-voltage on the output in PWM mode, the PWM drive is disabled. When disabled, the SLX output becomes high impedance (both high-side and low-side switches are turned off ). The switcher will not resume switching until the output voltage has fallen to 2% below the programmed regulation voltage. Soft-Start The soft-start mode is enabled after every shutdown cycle to limit in-rush current. This controls the maximum current during start-up. The PMOS current limit is stepped up using three soft-start levels to the full value by a timer driven from the internal oscillator. During soft-start, the switching frequency is stepped by 1/8, 1/4, and 1/2 of the internal oscillator frequency up to the full value, under control of three output voltage thresholds. When the output voltage rises to 98% of the regulation voltage, soft- start mode is disabled. Switcher External Components The SC908 is designed for use with the inductor LS = 4.7μH, although other values can be used. The magnitude of the inductor current ripple is dependent on the inductor value and can be determined by the equation § u ' VOUT SVOUT oscS SVOUT L V V fL VI S This equation demonstrates the relationship between input voltage, output voltage, and inductor ripple current. Applications Information (continued)
Applications Information (continued) a few volts of bias. This is especially true of inexpensive dielectrics. Insufficient SVOUT capacitance can cause rapid decay of output voltage between PSAVE bursts, resulting in poor low-load effi ciency, PSAVE/PWM mode cycling, and other erratic behaviors. Switcher Grounding and PCB Layout Consider- ations Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce and resistive voltage losses. Poor regulation and instability can result. A few simple design rules can be implemented to ensure good layout: Place the inductor and fi lter capacitors as close to the device as possible and use short wide traces between the power components. Route the output voltage feedback path away from the inductor and LX node to minimize noise and magnetic interference. Maximize ground metal on the component side to improve the return connection and thermal dissipation. Separation between the SLX node and GND should be maintained to avoid cou- pling of switching noise to the ground plane. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Charger Grounding and PCB Layout Consider- ations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. Attaching the part to a larger copper footprint will enable better heat transfer from the device, especially on PCBs with internal ground and power planes. Place the input, output and bypass capacitors close to the device for optimal transient response and device behavior. Connect all ground connections directly to the ground plane. If there is no ground plane, connect to a common local ground point before connecting to board ground. The DGND pin and PGND pin should be con- nected directly to the PCB ground plane as close to the part as possible. The thermal pad should be connected to the ground plane with thermal vias under the SC908. The nodes indicated as AGND in the Block Diagram should be connected together and to the AGND pin. The AGND pin should be tied to the DGND pin at a single point close to the SC908. Route the BSEN trace directly to the battery posi- tive terminal connection on the PCB.
e bxN D/2 LxN INCHES .020 BSC b .007 bbb aaa N E L e D .012 .100 DIM A MIN .000 .031 0.50 2.80 0.30 2.55 .004 .004 .016 .157 .106 .020 .110 0.10 0.10 0.40 4.00 2.70
0.50 BSC
0.05 1.00 DIMENSIONS MIN 0.00 NOM (.008) .035 .001 MAX .002 .039 NOM 0.80 0.02 (0.20) 0.90 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. NOTES: N PIN 1 INDICATOR 4.153.85 4.00 4.153.85.157 .152 .163 .152 .163 aaa C A C (LASER MARK) D E B A SEATING PLANE E/2 bbb C A B Outline Drawing — MLPQ-24 4x4
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com Contact Information SC908 Land Pattern — MLPQ-24 4x4 COMPANY'S MANUFACTURING GUIDELINES ARE MET. 4.80.189Z K G ZH(C) X P FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P C G MILLIMETERSINCHES (3.95) .010 .033 .122 .020 .106 .106 (.156) 0.25 0.85 2.70 0.50 2.70 3.10 DIMENSIONS