SC905

SC905 SEMTECH | Alldatasheet

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2© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Exceeding the speciﬁ cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters speciﬁ ed in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Input Supply Voltage V IN -0.3 to +7 V Digital Input Voltage V DIG -0.3 to VIN+0.3 V Operating Ambient Temperature Range T A -40 to +85 °C Operating Junction Temperature Range T J -40 to +125 °C Peak IR Reﬂ ow Temperature T LEAD 260 °C Storage Temperature T STG -60 to +150 °C Thermal Resistance Junction to Ambient(1) θJA 26 °C/W ESD Protection Level(2) ESD 2 kV Unless otherwise noted VIN = 3.7V, TA = -40 to +85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min Typ Max Units General Supply Voltage V IN 2.7 5.5 V Shutdown Current I SD ON = 0V, HFPWR = 0V, PGOOD = 0V 1 μA Quiescent Supply Current ISU Default Start-up Mode 300 μA ISTBY I2C, VREF Active, All Outputs Disabled 30 60 μA Supply Bypass Capacitor C VCC At Each Power Input Pin 1 μF Start-Up Time t SU CBP = 0.1μF2 5 m s Under-Voltage Lockout UVLO Descending, Hysteresis = 50mV 2.5 V Over-Temperature OT Hysteresis = 20°C 160 °C Digital Inputs Digital Input Voltage (1) VIL 0.4 V VIH 1.25 V Digital Input Current I DIG Logic Level High or Low -0.2 0.2 μA Digital Outputs Digital Output Voltage(2) VOL ISINK = 1.2mA 2 10 %VPAD VOH ISOURCE = 0.5mA, VPAD ≥ 1.8V 90 98 %VPAD LDO Regulator (CORE) - 300mA Output Voltage Accuracy(3) ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VCORE = 0V 350 900 mA Default At Start-Up: ON VOUT-HI VCSEL - High 1.80 V VOUT-LO VCSEL - Low 1.35 V (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B.

Electrical Characteristics

3© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Parameter Symbol Condition Min Typ Max Units LDO Regulator (CORE) - 300mA (Cont.) Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 300mA -3 -30 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 300mA 300 350 mV Power Supply Rejection Ratio PSRR CORE f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 dB LDO Regulator (PAD) - 300mA Output Voltage Accuracy(3) ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT =1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VPAD = 0V 350 900 mA Default at Start-up: ON VOUT-HI VPSEL - High 2.60 V VOUT-LO VPSEL - Low 1.80 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 300mA -3 -30 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 300mA 300 350 mV Power Supply Rejection Ratio PSRR PAD f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 dB LDO Regulator (ANA) - 200mA Output Voltage Accuracy(4) ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VANA = 0V 250 650 mA Default At Start-up: ON V OUT 2.60 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 200mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 200mA 200 250 mV Power Supply Rejection Ratio PSRR ANA f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB Output Voltage Noise e n f = 10Hz to 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 45 μVRMS LDO Regulator (TCXO) - 80mA Output Voltage Accuracy(4) ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VTCXO = 0V 250 650 mA Default At Start-up: ON V OUT 2.85 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 80mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 80mA 200 250 mV Power Supply Rejection Ratio PSRR TCXO f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB Electrical Characteristics (Cont.)

4© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Parameter Symbol Condition Min Typ Max Units LDO Regulator (TCXO) - 80mA (Cont.) Output Voltage Noise e n f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 45 μVRMS LDO Regulator (TX) - 150mA Output Voltage Accuracy(4) ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VTX = 0V 250 650 mA Default At Start-up: OFF V OUT 2.85 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 150mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 150mA 200 250 mV Power Supply Rejection Ratio PSRR TX f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB Output Voltage Noise e n f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 45 μVRMS LDO Regulator (RX) - 150mA Output Voltage Accuracy(4) ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit ILIM VRX = 0V 250 650 mA Default At Start-up: OFF V OUT 2.85 V Line Regulation REG LINE IOUT = 1mA, VOUT+0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 150mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 150mA 200 250 mV Power Supply Rejection Ratio PSRR RX f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB Output Voltage Noise e n f = 10Hz - 100kHz, IOUT = 50mA, CBP= 0.1μF, COUT = 1μF 45 μVRMS LDO Regulator (CAM) - 100mA Output Voltage Accuracy(3) ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VCAM = 0V 250 650 mA Default At Start-up: OFF V OUT 1.80 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 100mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 100mA 200 250 mV Power Supply Rejection Ratio PSRR CAM f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 dB Electrical Characteristics (Cont.)

5© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Parameter Symbol Condition Min Typ Max Units LDO Regulator (PLL) - 80mA Output Voltage Accuracy(4) ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VPLL = 0V 250 650 mA Default At Start Up: OFF V OUT 2.85 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 80mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 80mA 200 250 mV Power Supply Rejection Ratio PSRR PLL f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB Output Voltage Noise e n f = 10Hz - 100kHz, I OUT = 50mA, CBP= 0.1μF, COUT = 1μF 45 μVRMS LDO Regulator (MOT) - 150mA Output Voltage Accuracy(3) ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV Current Limit I LIM VMOT = 0V 250 650 mA Default at Start Up: OFF V OUT 1.40 V Line Regulation REG LINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REG LOAD 1mA < IOUT < 150mA -3 -20 mV Dropout Voltage V DO VOUT = 2.90V, IOUT = 150mA 200 250 mV Power Supply Rejection Ratio PSRR MOT f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 dB Electrical Characteristics (Cont.)

6© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Parameter Symbol Condition Min Typ Max Units I2C Interface(5) Interface complies with slave mode I2C interface as described by Philips I2C speciﬁ cation version 2.1 dated January, 2000. Digital Input Voltage VIL 0.4 V VIH 1.25 V SDA Output Low Level I DIN (SDA) ≤ 3mA 0.4 V Digital Input Current I DG -0.2 0.2 μA Hysteresis of Schmitt Trigger Inputs V HYS 0.1 V Maximum Glitch Pulse Rejection t SP 50 ns I/O Pin Capacitance C IN 10 pF I2C Timing(5) Clock Frequency f SCL 400 440 kHz SCL Low Period t LOW 1.3 μs SCL High Period tHIGH 0.6 μs Data Hold Time t HD_DAT 0 μs Data Setup Time t SU_DAT 100 ns Setup Time for Repeated START Condition t SU_STA 0.6 μs Hold Time for Repeated START Condition t HD_STA 0.6 μs Setup Time for STOP Condition t SU_STO 0.6 μs Bus-Free Time Between STOP and START t BUF 1.3 μs RESET Timeout Delay t RD 75 100 125 ms Power-up Delay Between CORE, ANA, PAD, TXCO tDELAY Delay Between Each Output Activating 100 μs Maximum Glitch Pulse Rejection t SP 50 ns Interface Start-up Time t EN Bus Start-up Time After EN Pin is Pulled High 350 μs Notes: (1) Applies to pin names, CPB, CHRGB, FAULTB, ON, HFPWR, PGOOD, VCSEL, VPSEL. (2) Applies to pin names, PWRON, RESB. (3) For V OUT settings see Table A. (4) For VOUT settings see Table B. (5) Guaranteed by design. Electrical Characteristics (Cont.)

7© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 DEVICE PACKAGE SC905MLTRT(1) MLP 5x5 32L(2) SC905EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. Pin Conﬁ guration Ordering information TOP VIEW 9 10 11 12 13 14 15 16 2526272829303132 IN2 VCORE IN1 VPAD ON HFPWR SDA SCL VTX IN6 VPLL AGND VBAT BP PGOOD RESB DGND DVIN CHRGB CPB FAULTB VPSEL VCSEL PWRON VMOT IN3 VCAM IN4 VANA VRX IN5 VTCXO MLPQ32: 5X5 32 Lead T

8© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Pin Descriptions Pin # Pin Name I/O Pin Function 1 IN2 Input Input voltage terminal to VCORE LDO. 2 VCORE Output 300mA LDO output for MSM core processor supply. 3 IN1 Input Input voltage terminal to VPAD LDO. 4 VPAD Output 300mA LDO PAD output to MSM I/O circuits. 5 ON Input Active high power on/off key. When the push button is closed it is shorted to battery. 6 HFPWR Input Power on input from accessory, active high. 7 SDA Input/Output Bi-directional open drain digital I/O. I2C serial data. 8 SCL Input Digital input. I2C serial clock. 9 DGND - Digital ground. 10 DVIN Input Main digital input voltage terminal. 11 CHRGB Input Logic input. State is recorded in bit 1 of the status register. 12 CPB Input Logic input. State is recorded in bit 0 of the status register. 13 FAULTB Input Logic input. State is recorded in bit 2 of the status register. 14 VPSEL Input Default control for VPAD LDO supply. Ground for 1.80V default, tie high for 2.60V. 15 VCSEL Input Default control for VCORE LDO supply. Ground for 1.35V default, tie high for 1.80V. 16 PWRON Output Logic OR output of ON, HFPWR and PGOOD. Active high. 17 RESB Output Reset output. Active low. 18 PGOOD Input Logic input signal from MSM to indicate power is good, latches the SC905 on. Low disables the SC905. 19 BP Output LDO bypass output. Bypass with a 0.1μF capacitor. 20 VBAT Input Main battery supply input terminal. 21 AGND - Analog ground pin. 22 VPLL Output LDO output for PLL power. 23 IN6 Input Input voltage terminal for VPLL & VTX LDOs. 24 VTX Output LDO output for transmitter power. 25 VTCXO Output LDO output for TCXO power. 26 IN5 Input Input voltage terminal for VTCXO & VRX LDOs. 27 VRX Output LDO output for receiver power. 28 VANA Output LDO output for analog power. 29 IN4 Input Input voltage terminal to VANA LDO. 30 VCAM Output LDO output for camera power. 31 IN3 Input Input voltage terminal to VCAM & VMOT LDOs. 32 VMOT Output LDO output voltage for vibrator motor power. Can also be a general purpose output. T Thermal Pad - Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.

9© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Block Diagram PAD EN CORE EN CAM EN MOT EN ANA EN TCXO EN RX EN PLL EN TX EN I2C Registers Controls I2C Interface EN EN EN CTRLREG RESET17 PWRON logic VREF OT UVLO VPAD VPAD DGND AGND DVIN VBAT SCL SDA VCSEL VPSEL FAULTB CHRGB CPB RESB PWRON PGOOD HFPWR ON BP IN1 VPAD IN2 VCORE IN3 VCAM VMOT IN4 VANA IN5 VTCXO VRX IN6 VPLL VTX

10© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Therefore, if the ON pin transitions high when the PGOOD signal is high, the LDOs and RESB signal will remain in their state until the microprocessor pulls the PGOOD signal low. Once the PGOOD signal is low, all the LDOs immediately power off and all the logic resets to the shutdown condition. The SC905 can be indirectly powered off by using the I command to turn off the core supply. This will result in a loss of power to the MSM causing PGOOD to go low, thus disabling the SC905. The HFPWR pin operates identically to the ON pin. This pin provides a second source for activating power so that remote devices such as battery chargers or system con- nector pins can be used to enable the device. LDO Programmable Output Voltage The output voltage of each LDO regulator is programmable. Each LDO has a program voltage register that can be ac- cessed through the I 2C interface and the output voltage adjusted as necessary. (See the Tables on page 14 and 15 for more information.) ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bits to 1 and disabled by setting the on/off bits to 0. This allows for on/off control with a single write command. When an on/off bit is toggled, the registered data is main- tained. However, all programmed information will be lost when the PGOOD input goes low. VCSEL & VPSEL Pin The VCSEL & VPSEL pins set the default voltage of CORE and PAD LDOs respectively. When the VCSEL pin is set to VIN the default voltage for the CORE LDO is 1.80V. When this pin is set to GND the default voltage for the CORE LDO is 1.35V. Likewise, when the VPSEL pin is set to VIN the default voltage for the PAD LDO is 2.60V. When this pin is set to GND, the default voltage for the PAD LDO is 1.80V. In both cases the VCSEL and VPSEL pins must be tied to GND or VIN prior to the device being powered on. This volt- age cannot change “on the ﬂ y” by switching the pin voltage between VIN or GND once the device is on. General Description The SC905 includes 9 low dropout (LDO) voltage regulators to provide complete power regulation capability for CDMA handsets or other portable electronic equipment. Five of the LDOs are designed to be used with analog cir- cuitry such as audio, radio frequency, or oscillator circuits. These devices have very low noise levels and high power supply rejection. The output voltage range for these LDOs is 2.55V to 2.9V in 50mV steps. The outputs for these LDOs are VANA, VTCXO, VPLL, VTX, and VRX. Three other LDOs are general purpose regulators designed to be used with digital circuits. The noise requirements for these LDOs are relaxed, but their voltage range is expanded to cover the wide range of voltages needed for different types of functions. The outputs for these LDOs are VCORE, VPAD, and VCAM. The VMOT output is speciﬁ cally designed to drive a vibrator motor. This output can supply up to 150mA with voltage set- tings from 1.35V to 2.9V, allowing designers the ﬂ exibility to select the output voltage that provides maximum vibration. When not used in conjunction with a vibrator, this output can be used as a general purpose digital regulator. Power-On Control The SC905 is activated when the ON pin is pulled high, pro- vided that the input voltage is within the speciﬁ ed operating range. The ON pin responds to logic-high edge triggering to power up the handset. The rising edge ON signal is latched when the CORE, PAD, ANA, and TCXO LDOs are turned on and PGOOD goes high. When the PAD LDO output volt- age reaches 77% of its regulation point, the reset timer starts and the RESB signal transitions high after delay of typically 100ms. After a successful power up sequence, any subsequent condition that toggles RESB (e.g. VPAD short-circuit, over-temperature, under voltage lockout, I disable of VPAD) will see a delay in the RESB transition back to high of typically 250ms. The microprocessor then raises PGOOD high to keep the SC905 powered on. There is no time limit for the MSM to activate PGOOD. If the MSM fails to raise PGOOD before the ON switch is released, the SC905 will transition back into standby mode. Once the phone is powered on, the SC905 can only be directly powered off when the PGOOD signal goes low. Applications Information

11© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 The voltage can be changed from its default state after start-up by writing to the appropriate voltage code regis- ter. Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Register 7 is the active shut- down control register and is used to control the shutdown behavior. Each LDO has a speciﬁ c shutdown bit assigned to it. When the active shutdown bit is enabled (set to 1), the output capacitance on the LDO output is discharged by an on-chip FET when the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default state for each LDO active shutdown bit is on. Default Status Bit In many multi-threaded environments it is necessary to maintain synchronization between the host micro-control- ler and the target IC. The SC905 has a default status bit (DSB) that will facilitate this task. The DSB can be useful in keeping the MSM and the SC905 synchronized. However, this is only useful if the MSM is powered by an external switching regulator such as the SC190. The DSB is bit 7 of register 0, and shares this register space with the PAD voltage control bits. The DSB is only set to 1 during power-up to indicate that the part is set to the default state. Moreover, the DSB cannot be written to a 1 through the I 2C interface the way the other bits in this register can; it can only be cleared to 0 through the I2C interface. This feature prevents a software race condition by always writing to register 0 with bit 7 high when changing the PAD control voltage. To clear the bit simply write a 0 to bit 7. Applying the DSB Upon power-up, the SC905 LDOs and internal registers are set to their default state. The DSB is set to a 1 to indicate that the SC905 is in its default state. Upon reading this defaulted state condition, the MSM knows to perform whatever synchronization is needed to set the SC905 into a kno wn user state. This user state is entered by a tw o- stage process. 1) The MSM writes a 0 to the DSB indicating its desire to modify the state of the SC905. It then writes all of the correct register information to the SC905 to set it to the user state. 2) The MSM reads back all of the information to verify the data. Then it reads back the DSB again to ensure it is still set to 0. This veri ﬁ es that no reset took place during the time that the multiple writ es and re ad veri ﬁ cations happened. If the DSB has been reset to 1, this process needs to be repeated since the chip was reset sometime during the initialization. Once the MSM and the SC905 are synchronized, the DSB can be read back as a status check periodically, as needed. If it is ever set back to the default state, a new synchronization process is required. This handshake-style protocol makes sure that the MSM and SC905 are always synchronized. LDO Power-On Sequence When the SC905 ﬁ rst turns on, the four LDOs that default on are sequenced in the following fashion: CORE is the ﬁ rst to turn on, then PAD, then ANA and ﬁ nally TCXO. During the power-on sequence, each LDO has a 100μs delay from one LDO turning on to the other. This process eliminates large voltage spikes across the battery supply during power-up. For further information on LDO power on sequen cing, refer to the Timing Diagram on page 17. Protection Circuitry The SC905 contains protection circuitry that prevents the device from operating in an unspeci ﬁ ed state. These in- clude Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under-Voltage Lockout The SC905 provides an under-voltage lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, as de ﬁ ned in the Electrical Characteristics section, the LDOs are disabled and RESB is held low. When the battery voltage is increased above the hysteresis level, the LDOs are re-enabled into their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. When powering-up with a battery voltage below the UVLO threshold, RESB will be held low. Applications Information (Cont.)

12© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Over-Temperature Protection The SC905 provides an internal over-temperature (OT) protection circuit that monitors the internal junction tem- perature. When the temperature exceeds the OT threshold as deﬁ ned in the Electrical Characteristics section, the OT protection disables all the LDO outputs, holds the RESB signal low and sets the OTF bit low in the status register. When the junction temperature drops below the hysteresis le vel, the OT protection resets the OTF bit high and re-en- ables all the LDOs in their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. This is only useful if the MSM is not powered by the SC905, since during an OT fault the MSM will lose power. An external switching regulator such as the SC190A could power the MSM in the case where monitoring the OTF bit is desired. Short-Circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed. Interfacing to Semtech Battery Chargers The SC905 is designed to interface with Semtech battery chargers by providing three control inputs that map the state of the controls to register bits so the host processor can monitor the charger’s status via the I 2C interface. For open-drain control outputs from the charger, pull-up resis- tors must be connected to the lines for the SC905 registers to display the correct status. Status Register The status register monitors these inputs for changes, and the MSM can periodically poll this register to determine the status of the charger. This is a read-only register. This register is useful when the MSM needs to determine charg- ing status before performing an LCD update. The MSM can control other aspects of the charger with general purpose I/O. These include enable/disable and charge time-out functions. Many of the chargers functions can be statically set and do not need MSM intervention. The amount of MSM intervention is determined by the intended application. The following table is a summary of the status register inputs and their functions: CONDITION FUNCTION FAULTB is Low Charger Fault CPB is Low USB or AC Charger Present CHRGB is Low Charging in Progress CHRGB & FAULTB is Low Battery Fault Applications Information (Cont.) Layout Considerations The PCB layout associated with the SC905 is straight for- ward, with the main consideration being given to the value and position of the input bypass capacitors. The device itself has eight input voltage pins which can be powered from a single supply or from a number of individual supplies depending on how much copper is available on the input voltage feed track and how much real estate is available on the PCB for components. If all the supply inputs are fed from one single supply trace or from a power plane, a 10μF low ESR capacitor or two 4.7 μF low ESR capacitors should be used. Larger input capacitance and lower ESR provide better supply noise rejection and line transient response. The copper trace to the inputs should be fairly thick in order to keep trace inductance to a minimum and the capacitors should be located as close to the SC905 as possible. If the supply trace is thin then the inputs should be treated as if they were powered from individual supplies, each input should be bypassed by at least one 1μF low ESR capacitor located very close to each input pin. The SC905 is designed to have excellent stability with a minimum output capacitance of 1 μF. Low ESR ce- ramic capacitors are recommended and should be located as close to the LDO output pins as possible.

13© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 SC905 Slave Address: Defaults are indicated in BOLD. Notes: (1) The default status bit (DSB) is set to 1 only when the SC905 is enabled by either the HFPWR pin or the ON pin being pulled high, and it cannot be set to one through the I2C interface. When changing the VPAD control voltage, always write to register 0 with bit seven high. Set bit seven low only when the DSB is to be cleared by the MSM. This will prevent any software race condition in a multi-tasking environment. See the applica- tions section for more information on using the DSB. (2) The Active Shutdown defaults ON at power-up, but the registers maintain their settings as the LDOs are enabled and disabled during normal operation. Register Name Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default State VPAD VCORE VMOT VANA/VCAM VTCXO/VRX VPLL/VTX ON/OFF CONTROL ACTIVE(2) SHUTDOWN STATUS (READ ONLY) DSB(1) 1 0 User State X X VPAD4 VPAD3 VPAD2 VPAD1 VPAD0 XXXV C O R E 4 VCORE3 VCORE2 VCORE1 VCORE0 XVMOT_EN VMOT Active SHDN VMOT4 VMOT3 VMOT2 VMOT1 VMOT0 1 0 1 0 OFF OFFON ON VANA2 VANA1 VANA0 VCAM4 VCAM3 VCAM2 VCAM1 VCAM0 VTCXO2 VTCXO1 VTCXO0VRX2 VRX1 VRX0 VPLL2 VPLL1 VPLL0VTX2 VTX1 VTX0 X X X X VPAD_EN OFFON VCORE_EN OFFON VANA_EN OFFON VCAM_EN OFFON VTCXO_EN OFFON VPLL_EN OFFON VTX_EN OFFON VRX_EN OFFON VPAD Active SHDN 1 0 OFFON VCORE Active SHDN OFFON VANA Active SHDN 1 0 OFFON VCAM Active SHDN 1 0 OFFON VTCXO Active SHDN 1 0 OFFON VPLL Active SHDN 1 0 OFFON VTX Active SHDN 1 0 OFFON VRX Active SHDN OFFON FAULTB 1 0 FAULTOK CHRGB 1 0 OFF ON CPB 1 0 OFF ON OTF OK FAULT XXXX DEVICE ADDRESS R/W 0001000 X Register Map

14© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Digital LDO Voltage Table A A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages. TABLE A - Output Voltage Code Bits for VCORE, VPAD, VMOT and VCAM X4 X3 X2 X1 X0 LDO Output Voltage 0 0 0 0 0 1.35V 0 0 0 0 1 1.40V 0 0 0 1 0 1.45V 0 0 0 1 1 1.50V 0 0 1 0 0 1.55V 0 0 1 0 1 1.60V 0 0 1 1 0 1.65V 0 0 1 1 1 1.70V 0 1 0 0 0 1.75V 0 1 0 0 1 1.80V 0 1 0 1 0 1.85V 0 1 0 1 1 1.90V 0 1 1 0 0 1.95V 0 1 1 0 1 2.00V 0 1 1 1 0 2.05V 0 1 1 1 1 2.10V 1 0 0 0 0 2.15V 1 0 0 0 1 2.20V 1 0 0 1 0 2.25V 1 0 0 1 1 2.30V 1 0 1 0 0 2.35V 1 0 1 0 1 2.40V 1 0 1 1 0 2.45V 1 0 1 1 1 2.50V 1 1 0 0 0 2.55V 1 1 0 0 1 2.60V 1 1 0 1 0 2.65V 1 1 0 1 1 2.70V 1 1 1 0 0 2.75V 1 1 1 0 1 2.80V 1 1 1 1 0 2.85V 1 1 1 1 1 2.90V Register Map (Cont.)

15© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Analog LDO Voltage Table B The bit code controls the output voltage of each LDO. The LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table B for the bitcodes and their corresponding voltages. TABLE B - Output Voltage Code Bits for LDOs VANA, VTCXO, VTX, VRX, VPLL X2 X1 X0 LDO Output Voltage 0 0 0 2.55V 0 0 1 2.60V 0 1 0 2.65V 0 1 1 2.70V 1 0 0 2.75V 1 0 1 2.80V 1 1 0 2.85V 1 1 1 2.90V The I2C General Speciﬁ cation The SC905 is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January, 2000. The SC905 has eight user-accessible internal 8-bit registers. The I2C interface has been designed for program ﬂ exibility, in that once the slave address has been sent to the SC905 enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SC905 I 2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC905 Limitations to the I 2C speciﬁ cations: Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SC905. The SC905 is not CBUS compatible. The SC905 can operate in standard mode (100kbit/s) or fast mode (400kbit/s). Supported Formats: Direct Format - Write The simplest format for an I 2C write is given below. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I 2C then acknowledges that it is being addressed, and the master re- sponds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. Register Map (Cont.)

16© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Slave Address Register Address DataS W A AA P S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit A: Acknowledge (sent by slave) Data: 8 bit P: Stop condition I2C Direct Format - Write Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave ad- dress is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. Slave Address Register Address Slave Address Data NACKS W A A Sr R A P S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition I 2C Combined Format - Read Slave Address Register Address Slave Address B Data NACKS W A A S/Sr R A PP Slave Address AS S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition I 2C Stop Separated Format - Read Register Address Setup Access Master Addresses other Slaves Register Read Access Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC905 then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC905 with a read command. The SC905 acknowledges this request and returns the data from the register location that had previously been set up Using the I2C Serial Port

17© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Power On-Off Timing Diagram 77% 77% 77% 25ms 100μs 100μs 100μs 100ms 100μs 100μs 100μs 100ms 25ms MSM DETERMINED MSM DETERMINED ON or HFPWR DSB BP VCORE VPAD VANA VTCXO RESB PGOOD PWRON MSM DETERMINED Timing Diagram

18© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 100 125 150 175 200 80 100 120 140 160 180 200 100 125 150 175 200 225 100 125 150 175 200 225 250 275 300 -18 -15 -12 0 25 50 75 100 125 150 175 200 -15 -12 0 50 100 150 200 250 300 3 3.5 4 4.5 5 5.5 3 3.5 4 4.5 5 5.5 T = -40˚CT = -40˚C T = -40˚C T = -40˚C T = -40˚CT = -40˚C T = 25˚C T = 25˚C T = 25˚C T = 25˚C T = 25˚C T = 25˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C Dropout Voltage vs. Load Current (Analog LDOs) Line Regulation (Analog LDOs) Load Current = 1mA Dropout Voltage vs. Load Current (Digital LDOs) Line Regulation (Digital LDOs) Load Current = 1mA Typical Characteristics Load Current (mA)Load Current (mA) Dropout Voltage (mV) Dropout Voltage (mV) Load Regulation (Analog LDOs) VIN = 3.7V Load Regulation (Digital LDOs) VIN = 3.7V Load Current (mA) Load Current (mA) Input Voltage (V) Input Voltage (V) Ouptut Voltage Variation (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) Output Voltage Variation (mV)

19© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 0.2 0.4 0.6 0.8 1.2 1.4 1.6 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 0 25 50 75 100 125 150 175 200 T = 85˚C T = 25˚C T = -40˚C VOUT = 1.35V VOUT = 2.90V Typical Characteristics PSRR vs. Frequency (Analog LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA Safe Operating Limits PSRR vs. Frequency (Digital LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA Output Noise vs. Load Current (Analog LDOs) VOUT = 2.90V, VIN = 3.7V Typical Characteristics (Cont.) Input Voltage (V) Load Current (mA) Frequency (Hz)Frequency (Hz) Power Supply Rejection (dB) Power Supply Rejection (dB) Maximum Output Current (A) Output Noise (μV) Maximum Recommended Input Voltage

20© 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC905 Marking Information Outline Drawing - MLPQ-32 5x5 Top Marking yyww = Date Code (Example: 0552) xxxxx = Semtech Lot Number (Example: E90101-100)

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 FAX (805)498-3804 Contact Information Land Pattern - MLPQ-32 5x5

Summary

CDMA Cellular Phone Power Management IC

Description

The SC905 is a power management integrated circuit (PMIC) designed for the latest CDMA chip sets. The device provides four general purpose low dropout regulators (LDOs), and five low noise LDOs designed for analog circuits. The VMOT LDO can be used as a general purpose regulator or as an adjustable motor drive output that can supply up to 150mA to drive a vibrator motor.

Source title SC905 Datasheet(PDF) - Semtech Corporation

Read SC905 online.