SC900A

SC900A SEMTECH | Alldatasheet

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www.semtech.com1 POWER MANAGEMENT SC900A Programmable Penta ULDO with RESET and I2C Interface Five LDO regulators in one package I 2C interface with multiple device capability Independent I 2C enable/disable of LDOs Independent I 2C control of output voltages Low thermal impedance of 40°C per watt 150mV dropout at 150mA Input range from 2.7V to 5.5V Programmable power good ﬂ ag Minimal number of external components Over temperature protection Small 4mm x 4mm 20-lead MLPQ package Small input/output ﬁ lter capacitors Programmable VOUT range - 1.45V to 3.00V for LDOs A and B 1.75V to 3.30V for LDOs C, D and E November 14, 2005 Description Features Typical Application Circuit

Applications

The SC900A is a highly integrated power management de- vice for low power portable applications. The device con- tains ﬁ ve adjustable low-dropout linear regulators (LDOs) with CMOS pass-devices as well as a band-gap reference, I 2C interface, and DACs to control the output voltages. Many features of the SC900A are programmable through the I2C interface. These include the ability to independent- ly turn on any combination of the ﬁ ve regulators. All ﬁ ve of the LDO output voltages are programmable in 50mV steps from 1.45V to 3.00V for LDOs A and B, and from 1.75V to 3.30V for LDOs C, D and E. Each LDO can have an active shutdown or nonactive shutdown program op- tion through the interface. There is also a reset monitor ﬂ ag that is associated with LDOA. In addition, the device has a separate programmable power good monitor ﬂ ag that activates when one or more LDOs go out of regula- tion. The SC900A offers signi ﬁ cant quiescent current and space savings to the system designer by sharing refer- ence and biasing among ﬁ ve LDOs. The small and ther- mally ef ﬁ cient 20-lead MLPQ package make it ideal for use in portable products where minimizing layout area is critical. Palmtop/Laptop computers Personal Digital Assistants Cellular telephones Battery-powered equipment High ef ﬁ ciency linear power supplies Keypad VIN INA INB INCD INE EN LDOPGD ARST SDA SCL GND LDOE LDOD LDOA LDOB LDOC VREF VASEL DGND SC900A 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 0.1uF 4.7uF VBAT- Baseband Processor Audio Processing Digital Interface PA TCXO Synthesiser Transmitter Section Receiver Section LNA Camera Processing CCD

2© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Parameter Symbol Maximum Units Input Supply Voltage V IN -0.3 to +7 V Digital Input Voltage V DIG -0.3 to VIN +0.3 V Operating Ambient Temperature Range T A -40 to +85 °C Operating Junction Temperature Range T J -40 to +125 °C Peak IR Flow Temperature T LEAD 260 °C Storage Temperature T STG -60 to +150 °C Thermal Impedance Junction to Ambient(1) θJA 40 °C/W ESD Protection Level(2) ESD 2 kV Exceeding the speciﬁ cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters speciﬁ ed in the Electrical Characteristics section is not implied. Unless otherwise noted VIN = 3.7V, TA = -40 to +85°C. Typical values are at TA = +25°C. (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B.

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units General Supply Voltage V IN All outputs < VIN - dropout 2.7 5.5 V Quiescent Current Shutdown I Q-SHUTDOWN 10 μA Supply Bypass Capacitor C VCC Per input pin 1 μF Digital Inputs Digital Input Voltage VIL 0.4 V VIH 1.6 V Digital Input Current I DIG -0.2 0.2 μA Digital Outputs Digital Output Voltage(1) VOL ISINK= 1.2mA, V ≥ 1.8V 2 10 %LDOB VOH ISOURCE = 0.5mA, V ≥ 1.8V 90 98 %LDOB Referencing and Biasing Circuitry Quiescent Current Reference I Q-REF 25 μA Reference Voltage V REF 1.227 V VREF Start-Up Time I VREF CVREF = 100nF 15 ms VREF Bypass Capacitor C VREF 0.1 μF

3© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Units LDO Regulators Quiescent Supply Current I Q All LDOs active in default states 190 360 μA Quiescent Supply Current at Start-Up IQSUP LDO A, B, C active in default states VOUT + 0.5V < VIN < 5.5V 125 μA Current Limit I LIM 250 410 650 mA Bypass Capacitor C BYP Ceramic, low ESR 2.2 μF LDO Regulator A (Core Supply) Output Voltage Accuracy VOA A 1.45V ≤ VOUT ≤ 3.00V VOUT + 0.2V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 2.80V (DAC = 11011) VOASA IOUT = 1mA -2 +2 % Output Voltage Accuracy at 1.80V (DAC = 00011) IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 2.80V (DAC = 11011) VOUT + 0.5V ≤ VIN ≤ 5.5V, IOUT = 200mA -3.5 +3.5 % Maximum Output Current IOMAX A 200 mA Default Setting: ON VOA-HI VASEL - High 2.80 V VOA-LO VASEL - Low 1.80 V Load Regulation at 1.8V, 2.8V LOADREG A 1mA < IOUT <200mA -3 -20 mV Dropout Voltage V DA VOUT = 3.0V, IOUT = 200mA 200 250 mV Power Supply Rejection Ratio PSRR A f = 10Hz - 1kHz, CBYP = 0.1μF, IOUT = 50mA, 2.5V ≤ VOUT ≤ 3.0V 60 dB Output Voltage Noise(2) en-A f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1μF, COUT = 2.2μF, 2.5V ≤ VOUT ≤ 3.0V 45 μVRMS LDO Regulator B (DIGITAL I/O SUPPLY) Output Voltage Accuracy VOA B 1.45V ≤ VOUT ≤ 3.00V VOUT + 0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 2.80V (DAC = 11011) VOASB IOUT = 1mA -2 +2 % VOUT + 0.5V ≤ VIN ≤ 5.5V, IOUT = 150mA -3.5 +3.5 % Maximum Output Current IOMAX B 150 mA

4© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Units LDO Regulator B (DIGITAL I/O SUPPLY) (Cont.) Default Setting: ON VO B 2.80 mV Line Regulation at 2.8V LINEREG B IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 2.8V LOADREG B 1mA < IOUT <150mA -3 20 mV Dropout Voltage V DB VOUT = 3.0V, IOUT = 150mA 150 190 mV Power Supply Rejection Ratio PSRR B f = 10Hz - 1kHz, CBYP = 0.1μF, IOUT = 50mA, 2.5V ≤ VOUT ≤ 3.0V 60 dB Output Voltage Noise(2) en-B f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1μF, COUT = 2.2μF, 2.5V ≤ VOUT ≤ 3.0V 45 μVRMS LDO Regulator C Output Voltage Accuracy VOA C 1.75V ≤ VOUT ≤ 3.30V VOUT + 0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 2.90V (DAC = 10111) VOASC IOUT = 1mA -2 +2 % VOUT + 0.5V ≤ VIN ≤ 5.5V, IOUT = 150mA -3.5 +3.5 % Maximum Output Current IOMAX C 150 mA Default Setting: ON VO C 2.90 V Line Regulation at 2.90V LINEREG C IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 2.90V LOADREG C 1mA < IOUT <150mA -3 -20 mV Dropout Voltage V DC VOUT = 3.3V, IOUT = 150mA 150 190 mV Power Supply Rejection Ratio PSRR C f = 10Hz - 1kHz, CBYP = 0.1μF, IOUT = 50mA, 2.5V ≤ VOUT ≤ 3.3V 60 dB Output Voltage Noise(2) en-C f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1μF, COUT = 2.2μF, 2.5V ≤ VOUT ≤ 3.3V 55 μVRMS LDO Regulator D Output Voltage Accuracy VOA D 1.75V ≤ VOUT ≤ 3.30V VOUT + 0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 3.10V (DAC = 10111) VOASD IOUT = 1mA -2 +2 % VOUT + 0.5V ≤ VIN ≤ 5.5V, IOUT = 150mA -3.5 +3.5 %

5© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Units LDO Regulator D (Cont.) Maximum Output Current IOMAX D 150 mA Default Setting: OFF VO D 3.10 V Line Regulation at 3.10V LINEREG D IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 3.10V LOADREG D 1mA < IOUT <150mA -3 -20 mV Dropout Voltage V DD VOUT = 3.3V, IOUT = 150mA 150 190 mV Power Supply Rejection Ratio PSRR D f = 10Hz - 1kHz, CBYP = 0.1mF, IOUT = 50mA, 2.5V ≤ VOUT ≤ 3.3V 60 dB Output Voltage Noise(2) en-D f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1μF, COUT = 2.2μF, 2.5V ≤ VOUT ≤ 3.3V 55 μVRMS LDO Regulator E Output Voltage Accuracy VOA E 1.75V ≤ VOUT ≤ 3.30V VOUT + 0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25°C -3 +3 % Output Voltage Accuracy at 3.10V (DAC = 10111) VOASE IOUT = 1mA -2 +2 % VOUT + 0.5V ≤ VIN ≤ 5.5V, IOUT = 150mA -3.5 +3.5 % Maximum Output Current IOMAX E 150 mA Default Setting: OFF VO E 3.10 V Line Regulation at 3.10V LINEREG E IOUT = 1mA, VOUT + 0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 3.10V LOADREG E 1mA < IOUT = 150mA -3 -20 mV Dropout Voltage V DE VOUT = 3.3V, IOUT = 150mA 150 190 mV Power Supply Rejection Ratio PSRR E f = 10Hz - 1kHz, CBYP = 0.1μF, IOUT = 50mA, 2.5V ≤ VOUT ≤ 3.3V 60 dB Output Voltage Noise(2) en-E f = 10Hz - 100kHz, IOUT = 50mA, CVREF = 0.1μF, COUT = 2.2μF, 2.5V ≤ VOUT ≤ 3.3V 55 μVRMS A RESET Reset Threshold RESET THLD 77 % Reset Active Timeout Delay t RD Delay in default state 75 100 125 ms LDO POWER GOOD PGOOD Threshold PGOOD THLD 77 % PGOOD Active Timeout Delay t PG Delay in default state 75 100 125 ms Notes: 1) Digital outputs are powered from LDOB, so LDOB must be active for operation of LDOPGD and ARST. 2) Below 2.5V: becomes digital regulator.

6© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Electrical Characteristics (Cont.) Parameter Symbol Conditions Min Typ Max Units I2C Interface Interface complies with slave mode I2C interface as described by Philips I2C speciﬁ cation version dated January 2000. Digital Input Voltage VIL 0.4 V VIH 1.6 V SDA Output Low Level IDIN (SDA) = 3mA 0.4 V IDIN (SDA) = 6mA 0.6 V Digital Input Current I DG -0.2 0.2 μA I/O Pin Capacitance C IN 10 pF I2C Timing Clock Frequency f SCL 400 440 kHz SCL Low Period t LOW 1.3 μs SCL High Period t HIGH 0.6 μs Data Hold Time T HD_DAT 0 μs Data SetupTime T SU_DAT 100 μs Setup Time for Repeated Start Condition TSU_STA 0.6 μs Hold Time for Repeated Start Condition THD_STA 0.6 μs Setup Time for Stop Condition T SU_STO 0.6 μs Bus-Free Time Between STOP and START tBUF 1.3 μs

7© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A DEVICE PACKAGE SC900AMLTRT(1)(2) MLPQ20L SC900AEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. Pin Conﬁ guration Ordering information TOP VIEW 4 12 109 678 MLPQ 20: 4X4 20 LEAD 17181920 T LDOB INB SDA SCL EN VREF GND VIN INE LDOE LDOA INA LDOC INCD LDODARST LDOPGD VASEL DGND

8© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Pin Descriptions Pin# Pin Name Pin Function 1 LDOB LDO B output. 2 INB Input supply for the digital system logic and the LDO B pass transistor. 3 SDA Bidirectional open drain digital I/O pin. I 2C serial data. 4 SCL Digital input. I2C serial clock. 5 EN Digital input. High to enable part. Low to disable part (sleep mode). Note I2C control is active only when part is enabled.

6 A0 One bit address for connecting two SC900A devices on to the system through

the I2C interface. 7 DGND Digital ground. 8 VASEL LDO A selection default voltage. Tie this pin to ground for 1.8V or INB for 2.8V. 9 LDOPGD Digital output. State change indicates that one of four LDO output voltages (A, C, D or E) is out of spec. Note, desired state of pin is programmable through the I2C interface. 10 ARST Digital output. State change indicates LDO A output voltage is out of spec. Note, desired state of pin is programmable through the I2C interface. 11 VREF Bandgap reference output voltage. Connect at least 0.1 μF to ground (CVREF ≥ 0.1μF). 12 GND Analog ground. 13 VIN Analog supply voltage. 14 INE Input supply for the LDO E pass transistor. 15 LDOE LDO E output. 16 LDOD LDO D output. 17 INCD Input supply for the LDO C and LDO D pass transistors. 18 LDOC LDO C output. 19 INA Input supply for the LDO A pass transistor. 20 LDOA LDO A output. T Thermal Pad Thermal Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.

9© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Block Diagram I2C Interface en vasel scl sda DAC CNTL LDO CNTL reset CNTL VOB LDOA LDOB LDOC LDOD LDOE VREF DGND GND INE INCD INB INA VIN LDOPGD ARST SDA SCL VASEL EN LDO ref dac input out en LDO ref dac input out en LDO ref dac input out en LDO ref dac input out en LDO ref dac input out en Reference INB DACs CNTL Input en DAC A DAC B DAC C DAC D DAC E Reset/SHDN Control reset arst ldopgd INB VOB 7 12

10© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Applications Information General Description Each of the ﬁ ve low-dropout linear regulators (LDOs) can be independently enabled or disabled and their output voltages can each be set by an independent DAC. These controls can be accessed through the I 2C serial port. There are ﬁ ve 8-bit volatile registers in the SC900A; one for each LDO (registers A,B,C,D,E). In addition there is one common reset and power good control register and one on/off control register. The active shutdown circuitry can be accessed through each LDO register (refer to the section “Active Shutdown” on page 11 for more informa- tion). At power-up, the register contents are reset to their de- fault values and the ARST for LDO A has a default start-up delay of 100ms. At any time the part can be put into it’s lowest power state (shutdown) by pulling the EN pin low. Whenever the EN pin is forced low, the previous settings are lost and the part requires reprogramming to return to the desired state. When EN is pulled high, the device starts up in the default state. A detailed description of the protocol used to load the registers with data is described in the section entitled “Using the I 2C Interface” on page 14. VIN and Enable Pin The VIN supply must be ≥ 2.7V before the EN pin can be asserted. This means that the EN pin should not be tied to V IN so that it does not reach a logic high level before the input supply reaches 2.7V. LDOA (Core Supply) LDOA is intended to be used as the core supply. It has an output current capability of 200mA and a dedicated reset signal ARST. INA is the dedicated input supply for this regulator. LDOB (Digital I/O Supply) INB supplies power for the internal I 2C interface and other digital I/O functions, while LDOB supplies power for ARST and LDOPGD output ports (see Block Diagram). There- fore it is imperative that LDOB be operational to make use of ARST and LDOPGD. If LDOB is turned off by the on/off control register, these output ports will not function. LDO RESET Control Register: ARST Pin There are two functions that can be programmed, deﬁ n- ing the ARST pin action:

Set the polarity of the reset signal
Set the reset clear delay time in milliseconds As soon as the LDOA output voltage falls below its pro- grammed value, the ARST pin is asserted. The polarity of the ARST pin can be set to active high or active low during a reset condition, by bit 6 of the LDO Reset Control Reg- ister. Once the error condition is resolved (output rises to the programmed value), a delay is initiated before the ARST pin is cleared. The delay is programmable by bits 0-1 of the LDO Reset Control Register. The Default delay time is 100ms, and the delay can be programmed for 0, 50, 100, or 150ms. LDOPGD Pin There are three functions that can be programmed to deﬁ ne the LDOPGD pin action:
Set which LDOs are to be monitored for power good
Set the polarity of the power good signal
Set the power good delay time in milliseconds Bits 4 and 5 of the LDO Reset Control Register select which LDO or LDOs are monitored. LDO C, D and E can be monitored independently or LDOs A, C, D, and E can be monitored collectively. The polarity of the LDOPGD pin can be set to active high or active low by bit 7 of the LDO Reset Control Register. As soon as any of the selected LDO output voltages which are monitored falls within spec, the LDO power good (LDOPGD) pin is asserted. Once the LDO output power is stable (output rises to the programmed value), a delay is initiated before the LDOPGD pin is set. The delay is programmable by bits 2 and 3 of the LDO Re- set Control Register. The default delay is 100ms, and this delay can be programmed to 0, 50, 100, or 150ms.

11© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A R/W 00 0 1 0 0 Pin A0 to GND = 0 Pin A0 to VIN = 1 X DEVICE TYPE IDENTIFIER DEVICE ADDRESS Applications Information (Cont.) Active Shutdown The shutdown control bits determine how the on-chip ac- tive shutdown switches behave. Each LDO register uses bit 5 of the LDO output voltage data byte to control the shutdown behavior. When the active shutdown bit is en- abled (set to 1), the capacitance on the LDO output will be discharged by an on-chip FET after the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default active shutdown state for all LDOs is on. ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by set- ting their respective on/off bit to 1. Likewise, they can be turned off by setting the on/off bit to 0. This allows for on/off control with a single write command. If the enable (EN) pin is high and data is written to the LDO voltage reg- isters, the LDO outputs will go to the voltage prescribed by the Output Voltage Code bits (0-4). Data will not be lost when toggling the on/off bit from 0 to 1. However, if the EN pin is forced low, all circuitry in the device is disabled. All programmed information is lost when the enable bit is subsequently pulled high. VASEL Pin The VASEL pin sets the default voltage of LDO A, the core supply. When this pin is set to V IN, the default voltage is 2.80V. When this pin is set to GND, the default voltage is 1.80V. The voltage can be changed from its default state after start up by writing to the LDO voltage code register. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The most signi ﬁ cant six bits of the slave are the device type identiﬁ er (ID). For the SC900A this is ﬁ xed at 000100[B]. The next signi ﬁ - cant bit addresses a particular device. A system can have up to two SC900A devices on the bus. The two addresses are deﬁ ned by the state of the A0 input (see Figure 1). Figure 1 - Slave Address Structure When the A0 pin is tied to GND, device 1 has an address of 0 and the combination of device type ID and address is 0x08H. When the A0 pin is tied to V IN, device 2 has and address of 1 and the combination of device type ID and address is 0x09H. The last bit of the slave address de ﬁ nes the operation to be performed. When set to a one a read operation is se- lected; when set to a zero a write operation is selected. Following a start condition, the SC900A monitors the SDA line comparing the slave address being transmitted with its slave address (device type ID and state of A0 input). Upon a correct compare the SC900A outputs an acknowl- edge on the SDA line. Depending on the state of the R/W bit, the SC900A will execute a read or write operation. Protection Circuitry The SC900A provides protection circuitry that prevents the device from operating in an unspeciﬁ ed state. These include Under Voltage Lockout Protection, Over-tempera- ture Protection and Short-circuit Protection. Under Voltage Lockout The SC900A provides an Under Voltage Lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the bat- tery voltage drops below the UVLO threshold, the LDOs are disabled. As the battery voltage increases above the hysteresis level, the LDOs are re-enabled into their previ- ous states, provided ENABLE has remained high. If EN- ABLE goes low, the SC900A will shut down. Over Temperature Protection The SC900A provides an internal Over-temperature (OT) protection circuit that monitors the internal junction tem- perature. When the temperature exceeds the OT thresh- old, the OT protection disables all the LDO outputs. As the junction temperature drops below the hysteresis level the OT protection re-enables all the LDOs in their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900A will shut down. Short-Circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed.

12© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Applications Information (Cont.) Layout Considerations Layout is straightforward if you use the Gerber ﬁ les on page 21 as a reference. Notice that the input voltage feed to the SC900A is on the bottom of the board and vias con- nect this voltage track to the top of the board and then to the SC900A itself. The input bypass can be one 4.7μF capacitor, two 3.3μF capacitors, three 2.2μF capacitors or ﬁ ve 1μF capacitors. The determining factor is how much copper is available on the input voltage feed track and how much room is available. If the input voltage track is very thin, then use ﬁ ve 1μF capacitors placed very close to the input pins of the SC900A. If the input track is fairly thick, then you can use a single 4.7μF capacitor at the be- ginning of the voltage feed track since a wider track has less inductance per inch. The SC900AEVB has ﬁ ve 1μF capacitors, but these can be replaced with one 4.7 μF in place of C1 and opens in place of C9, C14, C15, and C16 (see page 20 for details). Register Name Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDO A LDO B LDO C LDO D LDO E LDO Reset Control On/Off Control Register 0x00 0x01 0x02 0x03 0x04 0x05 0x06 XX XXX LDOPGD Pin Reset Polarity Bit ARST Pin Reset Polarity Bit LDOPGD Monitor Logic Bits LDOPGD Delay Bits LDO (A) Reset Delay Bits ON/OFF Control LDO E ON/OFF Control LDO D ON/OFF Control LDO C ON/OFF Control LDO B ON/OFF Control LDO A Active Shutdown 1 = ON 0 = OFF Output Voltage Codes Table A for LDOs A & B Table B for LDOs C, D & E 101 1 1 1 0000 ON ON ON ON ON OFFOFFOFFOFFOFF LDO Reset Control Logic Table (Defaults are in Bold) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Result Result Resu lt Result Result LDOPGD Pin Polarity ARST Pin Polarity LDOPGD Monitor Logic LDOPGD Delay ARST Delay High: Power Fail Low: Power Good High: Power Good Low: Power Fail High: Power Good Low: Reset High: Reset Low: Power Good LDOs A, C, D & E Good LDO E Good LDO C Good LDO D Good 150ms 100ms 50ms 0ms 150ms 50ms 100ms 0ms LDO Reset Control Logic Table (Defaults are in Bold) Note: Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST. R/W 00 0 1 0 0 A 0 X DEVICE TYPE IDENTIFIER DEVICE ADDRESS SC900A Slave Address

13© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Applications Information (Cont.) Output Voltage Code Bits: A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages for LDOs A and B, and Table B for the bitcodes and corresponding voltages for LDOs C, D and E. BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LDO Output Voltage 0 0 0 0 0 1.45V 0 0 0 0 1 1.50V 0 0 0 1 0 1.55V 0 0 0 1 1 1.60V 0 0 1 0 0 1.65V --- - - - --- - - - 1 1 1 1 0 2.95V 1 1 1 1 1 3.00V Table A - LDO Output Voltage Control Settings for LDOs A and B Table B - LDO Output Voltage Control Settings for LDOs C, D and E BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LDO Output Voltage 0 0 0 0 0 1.75V 0 0 0 0 1 1.80V 0 0 0 1 0 1.85V 0 0 0 1 1 1.90V 0 0 1 0 0 1.95V -- --- - -- --- - 1 1 1 1 0 3.25V 1 1 1 1 1 3.30V

14© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Using the I2C Interface The SC900A is a read-write slave mode I2C device and complies with the Philips I2C standard version 2.1 dated January 2000. The SC900A has six user-accessible internal 8-bit registers. The I 2C interface has been designed for program ﬂ exibility, in that once the slave address has been sent to the SC900A enabling it to be a slave transmitter/receiver, any register can be written to or read from independently of each other. While there is no auto increment/decrement capability in the SC900A I 2C logic, a tight software loop can be designed to randomly access the next register indepen- dent of which register you have been accessing. The start and stop commands frame the datapacket and the repeat start condition is allowed if necessary. SC900A Limitations to the I 2C Speciﬁ cations Seven-bit addressing is required for communication with the SC900A; ten-bit addressing is not allowed. Any general call address will be ignored by the SC900A. Note that the SC900A is not CBUS compatible. Finally, the SC900A can operate in standard mode (100kbit/s) or fast mode (400kbit/s). Supported Formats Direct Format - Write The simplest format for an I 2C write is the direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900A I 2C then acknowledges that it is being addressed, and the master re- sponds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. Slave Address Register Address DataS W A AA P S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit A: Acknowledge (sent by slave) Data: 8 bit P: Stop condition I 2C Direct Format - Write Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900A I 2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the reg- ister address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previ- ously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally the master terminates the transfer with the stop condition [P]. Slave Address Register Address Slave Address Data NACKS W A A Sr R A P S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition I2C Combined Format - Read Applications Information (Cont.)

15© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Applications Information (Cont.) Stop Separated Reads Another read format is available which is, in effect, an extension of the combined format read. This format allows a master to set up the register address pointer for a read and return to that slave some time later to read the data. After the start condition [S], the slave address is sent, followed by a write. The SC900A I 2C then acknowledges that it is being addressed, and the master responds with the 8-bit register address. The master then sends a stop or restart condition, and may address another slave. Some time later the master sends a start or restart condition, and a valid slave address is sent, followed by a read. The SC900A I 2C then acknowledges and returns the data at thee register address location that had previously been set up. I2C Stop Separated Format - Read Slave Address Register Address Slave Address B Data NACKS W A A S/Sr R A PP Slave Address AS S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition Register Address Setup Access Master Addresses other Slaves Register Read Access

16© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Timing Diagrams ARST and LDOPGD Timing LDO On/Off Control via the I2C Interface LDO A: VOUTA VARST 90% VARST VTH(A) VTH(A) 10% VARST TRD LDO A, C, D & E: VOUT VLDOPGD VTH VTH 90% VLDOPGD 10% VLDOPGD TPGD SCL SDA VLDOn STOP START STOP 40us 300us

17© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Timing Diagrams (Cont.) Enable VREF LDO A LDO B LDO C LDO D LDO E ARST LDOPGD 15ms 100ms 100ms 15ms 200us Default Start-up, Shutdown Timing Diagram

18© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A 100 125 150 175 200 0 25 50 75 100 125 150 175 200 100 125 150 175 200 0 25 50 75 100 125 150 -12 -10 0 25 50 75 100 125 150 175 200 -12 -10 0 25 50 75 100 125 150 T = -40˚C T = -40˚C T = -40˚C T = -40˚C T = 25˚C T = 25˚C T = 25˚CT = 25˚C T = 25˚C T = 25˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C T = 85˚C Typical Characteristics Dropout Voltage (LDOA) Dropout Voltage (LDOB-E) Load Regulation (LDOA) VIN = 3.7V Load Regulation (LDOB-E) VIN = 3.7V Load Current (mA) Load Current (mA) Load Current (mA) Load Current (mA) Input Voltage (V) Input Voltage (V) Dropout Voltage (mV) Dropout Voltage (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) Output Voltage Variation (mV) Line Regulation (LDOA-B) Load Current = 1mA Line Regulation (LDOC-E) Load Current = 1mA

19© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 T = -40˚C T = -40˚C T = 25˚C T = 25˚C T = 85˚C T = 85˚C Load Transient (LDOA-E) VIN = 3.7V, Io = 10mA to 150mA step Line Transient (LDOA-E) VIN = 3.7V, Io = 150mA VIN 1V/div VO 10mV/divVO 20mV/div IO 100mA/div 1ms/div 1ms/div Output Noise v Load Current (LDOA-B) VIN = 3.7V, VO = 3V Output Noise v Load Current (LDOC-E) VIN = 3.7V, VO = 3.3V PSRR v Frequency (LDOA-B) VIN = 3.7V, VO = 3V PSRR v Frequency (LDOC-E) VIN = 3.7V, VO = 3.3V Load Current (mA) Load Current (mA) Frequency (Hz) Frequency (Hz) Power Supply Rejection (dB) Power Supply Rejection (dB) Output Voltage Noise (μV) Output Voltage Noise (μV)

20© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A Evaluation Board Schematic VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 GND VBUS VREGIN P3.0/C2D C2CK/RST VIN INB INCD INE EN LDOPGD ARST SDA INA SCL GND LDOA LDOB LDOC LDOD LDOE VREF VASEL DGND

1 LDOA LDOB LDOC LDOD LDOE

(Non-use)R10 R11 SC900A PWR C10 0.1uF 2.2uF NC7S04 U31 3 4 SDASCLTP3 TP4 TP8 TP7 TP1 TP2 AM1 AM2 7.5k 7.5k 150 150 R1 R2 D1 D2 LDOPGD ARST FMMT3904 FMMT3904 7.5k 7.5k C2DAT C2CLK PROGRAM & DEBUG J10 150 R16 USB BUSC13 1uF C12 4.7uF 150 R12 EXTERNAL 150 R13 USB 100k R14 100k R15 +5V USB C11 0.1uF 10uF EXTERNAL SUPPLY +5V EXTERNAL SW1 SC900A PWR SC900A Power Select +5V USB F1J11 USB R18 R17 GND GND 0.1uF 0.1uF C14 0.1uF C15 0.1uF C16 0.1uF VIN INA INB INCD INE SC900A PWR SC900A C8051F320 SC900A PWR ENABLE

22© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A .001 MAX .002 .040 NOM 0.80 0.02 (0.20) 0.90 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. NOTES: N PIN 1 INDICATOR 4.103.90 4.00 4.103.90.157 .153 .161 .153 .161 aaa C A C (LASER MARK) D E B A SEATING PLANE LxN E/2 bxN bbb C A B e D/2 INCHES .020 BSC b .007 bbb aaa N E L e D .011 .100 DIM A MIN .000 .031 0.50 2.80 0.30 2.55 .004 .004 .016 .157 .106 .020 .110 0.10 0.10 0.40 4.00 2.70

0.50 BSC

0.05 1.00 DIMENSIONS MIN 0.00 NOM (.008) .035 Outline Drawing - MLPQ-20L 4 x 4 Marking Information Top Marking yy = two-digit year of manufacture ww = two-digit week of manufacture

23© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC900A DIMENSIONS K H G Z X P (C) COMPANY'S MANUFACTURING GUIDELINES ARE MET. 4.80.189ZY THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P C G MILLIMETERSINCHES (3.95) .010 .033 .122 .021 .106 .106 (.155) 0.25 0.85 2.70 0.50 2.70 3.10 Land Pattern - MLPQ-20L 4 x 4 Semtech Corporation Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 FAX (805)498-3804 Contact Information

Summary

Programmable Penta ULDO with RESET and I2C Interface

Description

The SC900A is a highly integrated power management device for low power portable applications. The device contains five adjustable low-dropout linear regulators (LDOs) with CMOS pass-devices as well as a band-gap reference, I2C interface, and DACs to control the output voltages.

Source title SC900A Datasheet(PDF) - Semtech Corporation

Read SC900A online.