SC667201MMG1

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 120

Technical content

Data Sheet: Technical Data Document Number: MPC5642A Rev. 3.1, 06/2012 © Freescale Semiconductor, Inc., 2009, 2010, 2012. All rights reserved. MPC5642A

208 MAPBGA

176 LQFP

324 TEPBGA

(24 × 24 mm) (23 × 23 mm) (17 x 17 mm)

• 150 MHz e200z4 Power Architecture core – Variable length instruction encoding (VLE) – Superscalar architectur e with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumu late operations per cycle
• Memory organization – 2 MB on-chip flash memory with ECC and read-while-write (RWW) – 128 KB on-chip SRAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM –4  4 crossbar switch (XBAR) – 24-entry MMU
• Fail Safe Protection – 16-entry Memory Protection Unit (MPU) – CRC unit with 3 submodules – Junction temperature sensor
• Interrupt – Configurable interrupt controller (INTC) with non-maskable interrupt (NMI) – 64-channel eDMA
• Serial channels – 3 eSCI modules – 3 DSPI modules (2 of which support downstream Micro Second Channel [MSC]) – 3 FlexCAN modules with 64 message buffers each – 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
• 1 e M I O S – 24 unified channels
• 1 eTPU2 (second generation eTPU) —32 standard channels – 1 reaction module (6 cha nnels with 3 outputs per channel)
• 2 enhanced queued analog-to-digital converters (eQADCs) – Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers – 6 command queues – Trigger and DMA support – 688 ns minimum conversion time
• On-chip CAN/SCI Bootstrap loader with Boot Assist Module (BAM)
• Nexus: Class 3+ for core; Class 1 for eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS) – EVTO pin for communicati on with external tool
• Clock generation – On-chip 4–40 MHz main oscillator – On-chip FMPLL (frequency-modulated phase-locked loop)
• Up to 112 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis)
• Power reduction modes: slow, stop, and standby
• Flexible supply scheme – 5 V single supply with external ballast – Multiple external supply: 5 V , 3.3 V , and 1.2 V Qorivva MPC5642A Microcontroller Data Sheet

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor2 Table of Contents

1.5.6 Frequency-modulat ed phase-locked loop

1.5.11 Enhanced modular input/output system

1.5.12 Second generation enhanced time processing

1.5.14 Enhanced queued analog-to-digital converter

1.5.16 Enhanced serial communications interface

3.3.1 General notes for specifications at maximum

3.4 EMI (electromagnetic interf erence) characteristics . . . 61

3.6 Power management control (PMC) and power on

3.9.1 I/O pad V

3.10 Oscillator and PLLMRFM elec trical characteristics . . . 75

1 Introduction

1.1 Document overview

characteristics. For functional characteristics, refer to the device reference manual.

1.2 Description

transmission control applications. and a 2 MB internal flash memory.

1.3 Device feature summary

Table 1 summarizes the MPC5642A features and compares them to those of the MPC5644A. Table 1. MPC5642A device feature summary

4 Freescale Semiconductor

4 STM channels

1 Software Watchdog

Table 1. MPC5642A device feature summary (continued)

1.4 Block diagram

Figure 1 shows a top-level block diagram of the MPC5642A series.

208 MAPBGA3,4

324 TEPBGA5

176 LQFP3

1 197 interrupt vectors are reserved.

3 Pinout compatible with Freescale’s MPC5634M devices

4 Pinout compatible with Freescale’s MPC5534

6 For Freescale VertiCal Calibration System only

6 Freescale Semiconductor

Figure 1. MPC5642A series block diagram Table 2 summarizes the functions of the blocks present on the MPC5642A series microcontrollers.

3 KB Data

14 KB Code

8 KB I-cache

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 7 Introduction Table 2. MPC5642A series block summary

applications

Enhanced serial communication interface (eSCI) Provides asynchronous serial communication capability with peripheral devices and other microcontroller units Enhanced time processor unit (eTPU2) Second-generatio n co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention Error Correction Status Module (ECSM) The Error Correction Status Module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented Flash memory Provides storage for program code, constants, and variables FlexRay Provides high-speed distributed control for advanced automotive Frequency-modulated phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Memory protection unit (MPU) Provides hardware access control for all memory references generated Nexus port controller (NPC) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2010 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Reaction Module (REACM) Works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop.

8 Freescale Semiconductor

and the system reset operation. Table 2. MPC5642A series block summary (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 9 Introduction

1.5 Feature details

1.5.1 e200z4 core MPC5642A devices have a high performance e200z4 core processor:

• 32-bit Power Architecture technology programmer’s model
• Variable Length Encodi ng (VLE) enhancements
• Dual issue, 32-bit Powe r Architecture technology compliant CPU
• 8 KB, 2/4-way set associ ative instruction cache
• Thirty-two 64-bit general purpose registers (GPRs)
• Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)
• Harvard Architecture: Separate in struction bus and load/store bus
• Vectored interrupt support
• Non-maskable interrupt input
• Critical Interrupt input
• New ‘Wait for Interrupt’ instruction, to be used with new low power modes
• Reservation instructions for im plementing read-modify-write accesses
• Signal processing extension (SPE) APU
• Single Precision Floating point (scalar and vector)
• Nexus Class 3+ debug
• Process ID manipulation for th e MMU using an external tool
• In-order execution and retirement
• Precise exception handling
• Branch processing unit — Dedicated branch address calculation adder — Branch target prefetching using 8-entry BTB
• Supports independent instruction and data accesses to diff erent memory subsystems, such as SRAM and flash memory via independent Instruction and Data BIUs
• Load/store unit — 2-cycle load latency — Fully pipelined — Big and Little endian support — Misaligned access support
• Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose Register file
• Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations, using the 64-bit General Purpose Register file
• Power management — Low power design – extensive clock gating — Power saving modes: wait — Dynamic power management of execution units, cache and MMU
• Testability — Synthesizeable, MuxD scan design — ABIST/MBIST for arrays — Built-in Parallel Signature Unit

MPC5642A Microcontroller Data Sheet, Rev. 3.1

10 Freescale Semiconductor

• Calibration support allowing an external tool to modify address mapping

1.5.2 Crossbar switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between four master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features:

• 4 master ports — CPU instruction bus — CPU data bus —e D M A —F l e x R a y
• 4 slave ports —F l a s h — Calibration bus interface —S R A M — Peripheral bridge
• 32-bit internal address, 64-bit internal data paths

1.5.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation minimizes overall block size. The eDMA module provides the following features:

• All data movement via dual-address transfer s: read from source, write to destination
• Programmable source and destination a ddresses, transfer size, plus support for enhanced addressing modes
• Transfer control descriptor organized to s upport two-deep, nested transfer operations
• An inner data transfer loop defined by a “minor” byte transfer count
• An outer data transfer loop defined by a “major” iteration count
• Channel activation via one of three methods: — Explicit software initiation — Initiation via a channel-to-channel link ing mechanism for continuous transfers — Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• 1 interrupt per channel, optionally asserted at completion of major iteration count
• Error termination interrupts optionally enabled
• Support for scatter/gather DMA processing
• Ability to suspend channel transfers by a higher priority channel

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 11 Introduction

1.5.4 Interrupt controller (INTC)

The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. The INTC provides the following features:

• 9-bit vector addresses
• Unique vector for each interrupt request source
• Hardware connection to proce ssor or read from register
• Each interrupt source can assigned a specific priority by software
• Preemptive prioritized inte rrupt requests to processor
• ISR at a higher priority preempts execu ting ISRs or tasks at lower priorities
• Automatic pushing or popping of preempted priority to or from a LIFO
• Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
• Low latency—3 clocks from receipt of interrupt request from peripheral to interrupt request to processor This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

1.5.5 Memory protection unit (MPU)

The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MPU has these major features:

• Support for 16 memory region descriptors, each 128 bits in size — Specification of start and end addresses provide gr anularity for region sizes from 32 bytes to 4 GB — MPU is invalid at reset, thus no access restrictions are enforced — 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (eDMA, FlexRay) support {read, write} attributes — Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor — Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only — For overlapping region descriptors, prio rity is given to permission granting over access denying as this approach provides more flexibility to system software
• Support for two XBAR slave port connections (SRAM and PBRIDGE) — For each connected XBAR slave por t (SRAM and PBRIDGE), MPU hardware monitors every port access using the preprogrammed memory region descriptors

MPC5642A Microcontroller Data Sheet, Rev. 3.1

12 Freescale Semiconductor

— An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device — 64-bit error registers, one for each XB AR slave port, capture the last faulting address, attributes, and detail information

1.5.6 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features:

• Input clock frequency from 4 MHz to 40 MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
• 3 modes of operation — Bypass mode with PLL off — Bypass mode with PLL running (default mode out of reset) — PLL normal mode
• Each of the 3 modes may be run with a crysta l oscillator or an external clock reference
• Programmable frequency modulation — Modulation enabled/disabled through software — Triangle wave modulation up to 100 kHz modulation frequency — Programmable modulation depth (0% to 2% modulation depth) — Programmable modulation frequency dependent on reference frequency
• Lock detect circuitry reports when the PLL has achieved fr equency lock and continuously monitors lock status to report loss of lock conditions
• Clock Quality Module — Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected — Detects the quality of the PL L output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request
• Programmable interrupt request or system reset on loss of lock
• Self-clocked mode (SCM) operation

1.5.7 System integration unit (SIU)

The MPC5642A SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core is via the crossbar switch. The SIU provides the following features:

• System configuration — MCU reset configuration via external pins — Pad configuration control for each pad — Pad configuration control for virtual I/O via DSPI serialization
• System reset monitoring and generation — Power-on reset support — Reset status register provides last reset source to software

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 13 Introduction — Glitch detection on reset input — Software controlled reset assertion

• External interrupt — Rising or falling edge event detection — Programmable digital filter for glitch rejection — Critical Interrupt request — Non-Maskable Interrupt request
• G P I O — Centralized control of I/O and bus pins — Virtual GPIO via DSPI serialization (r equires external deserialization device) — Dedicated input and output registers fo r setting each GPIO and Virtual GPIO pin
• Internal multiplexing — Allows serial and parallel chaining of DSPIs — Allows flexible selection of eQADC trigger inputs — Allows selection of interrupt requests between external pins and DSPI — From a set of eTPU output channels, allows selectio n of source signals for decimation filter integrators

1.5.8 Flash memory

The MPC5642A provides 2 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses. The flash memory provides the following features:

• Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.
• Fetch Accelerator — Architected to optimize th e performance of the flash — Configurable read buffering and line prefetch support — 4-entry 128-bit wide line read buffer — Prefetch controller
• Hardware and software configur able read and write access protections on a per-master basis
• Interface to the flash array controller pi pelined with a depth of one, allowing overlapped accesses to proceed in parallel for pipelined flash array designs
• Configurable access timing usable in a wide range of system frequencies
• Multiple-mapping support and mapping- based block access timing (0–31 additional cycles) usable for emulation of other memory types
• Software programmable block progr am/erase restriction control
• Erase of selected block(s)
• Read page size of 128 bits (4 words)
• ECC with single-bit correction, double-bit detection
• Program page size of 128 bits (4 words) to accelerate programming
• ECC single-bit error correcti ons are visible to software
• Minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC

MPC5642A Microcontroller Data Sheet, Rev. 3.1

14 Freescale Semiconductor

• Embedded hardware program and erase algorithm
• Erase suspend, program suspe nd and erase-suspended program
• Shadow information stored in non-volatile shadow block
• Independent program/erase of the shadow block

1.5.9 Static random access memory (SRAM)

The SRAM provides 128 KB of general purpose system SRAM. The first 32 KB block of the SRAM is powered by its own power supply pin only during standby operation. The SRAM controller includes these features:

• 128 KB data RAM implemented as eight 16 KB (2048  78 bits) blocks
• Each 16 KB block has 2 rows repairable (RAMs with internal repair feature)
• Supports read/write accesses mapped to the SRAM memory from any master
• 32 KB block powered by separate supply for standby operation
• Byte, halfword, word and doubleword addressable
• ECC performs single bit correction, double bit detection

1.5.10 Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once by Freescale and is identical for all MPC5642A MCUs. The BAM program is executed every time the MCU is powered on or reset in normal mode. The BAM supports different modes of booting. They are:

• Booting from internal flash memory
• Serial boot loading (boot code is downloaded into RAM via eSCI or the FlexCAN and then executed) The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5642A hardware accordingly. The BAM provides the following features:
• Sets up MMU to cover all resources and mapping of all phy sical addresses to logical addresses with minimum address translation
• Sets up MMU to allow user boot code to execute as either Power Architecture technology code (default) or as Freescale VLE code
• Location and detection of user boot code
• Automatic switch to serial boot mode if internal flash is blank or invalid
• Supports user programmable 64-bit password protection for serial boot mode
• Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol
• Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
• Supports serial bootloading of either Power Archit ecture technology code (default) or Freescale VLE code
• Supports booting from calibration bus interface
• Supports censorship protection for internal flash memory
• Provides an option to enable the core watchdog timer
• Provides an option to disable the system watchdog timer

1.5.11 Enhanced modular inpu t/output system (eMIOS)

The eMIOS timer module provides the capability to generate or measure events in hardware. The eMIOS module features include:

• Twenty-four 24-bit wide channels

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 15 Introduction

• 3 channels’ internal timebases sharable between channels
• 1 timebase from eTPU2 can be im ported and used by the channels
• Global enable feature for all eMIOS and eTPU timebases
• Dedicated pin for each channel (n ot available on all package types)
• Each channel (0–23) supports the following functions: — General Purpose Input/Output (GPIO) — Single Action Input Capture (SAIC) — Single Action Outp ut Compare (SAOC) — Output Pulse Width Modulation Buffered (OPWMB) — Input Period Measurement (IPM) — Input Pulse Width Measurement (IPWM) — Double Action Output Compare (DOAC) — Modulus Counter Buffered (MCB) — Output Pulse Width & Frequency Modulation Buffered (OPWFMB)
• Each channel has its own pin (not available on all package types)

1.5.12 Second generation enhanced time processing unit (eTPU2)

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2. MPC5642A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard eTPU include:

• The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
• Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
• A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.
• Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction.
• Channel Flags 0 and 1 can now be tested for bran ching, in addition to selecting the entry point.
• Channel digital filters can be bypassed. The eTPU2 includes these distinctive features:
• 32 channels; each channel associated with one input and one output signal — Enhanced input digital filters on the input pins for improved noise immunity — Identical, orthogonal channels: each channel can perform an y time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. — Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. — Input and output signal states visible from the host
• 2 independent 24-bit time bases for channel synchronization: — First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler

MPC5642A Microcontroller Data Sheet, Rev. 3.1

16 Freescale Semiconductor

— Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time — Both time bases can be exported to the eMIOS timer module — Both time bases visible from the host

• Event-triggered microengine: — Fixed-length instruction execution in two-system-clock microcycle — 14 KB of code memory (SCM) — 3 KB of parameter (data) RAM (SPRAM) — Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected combinations — 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution — Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.
• Resource sharing features support ch annel use of common channel registers, memory and microengine time: — Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined, host-configured priority — Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another begins to service a request from other channel: channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel — SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel — Hardware implementation of 4 semaphores support cohe rent parameter sharing between both eTPU engines — Dual-parameter coherency hardware support a llows atomic access to 2 parameters by host
• Test and development support features: — Nexus Class 1 debug, supporting single-step executi on, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions — Software breakpoints — SCM continuous signature-check built-in self test MISC (multiple input signature calculator), runs concurrently with eTPU2 normal operation

1.5.13 Reaction module (REACM)

The REACM provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop. The REACM has the following features:

• 6 reaction channels with peak and hold control blocks
• Each channel output is a bus of 3 signals, providing ability to control 3 inputs.
• Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels Target applications include solenoid control for direct injection systems and valve control in automatic transmissions.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 17 Introduction

1.5.14 Enhanced queued analog -to-digital converter (eQADC)

The eQADC block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog-to-digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels. The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC. The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully process the digitized waveform. The eQADC provides the following features:

• Dual on-chip ADCs —2  12-bit ADC resolution — Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) – 12-bit conversion time – 938 ns (1M sample/s) – 10-bit conversion time – 813 ns (1.2M sample/s) – 8-bit conversion time – 688 ns (1.4M sample/s) — Up to 10-bit accuracy at 500K sample/s and 8-bit accuracy at 1M sample/s — Differential conversions — Single-ended signal range from 0 to 5 V — Sample times of 2 (d efault), 8, 64, or 128 ADC clock cycles — Provides time stamp info rmation when requested — Allows time stamp information relative to eT PU clock sources, such as an angle clock — Parallel interface to eQADC command FI FOs (CFIFOs) and result FIFOs (RFIFOs) — Supports both right-justified unsigned and signed formats for conversion results
• 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports 4 external 8-to-1 muxes)
• 8 channels can be used as 4 pairs of differential analog input channels
• Differential channels include variable gain amplifier for improved dynamic range ( 1, 2, 4)
• Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
• Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the device
• An internal bandgap reference to allow absolute voltage measurements
• Silicon die temperature sensor

MPC5642A Microcontroller Data Sheet, Rev. 3.1

18 Freescale Semiconductor

— Provides temperature of silicon as an analog value — Read using an internal ADC analog channel — May be read with either ADC

• 2 decimation filters — Programmable decimation factor (1 to 16) — Selectable IIR or FIR filter — Up to 4th order IIR or 8th order FIR — Programmable coefficients — Saturated or non-saturated modes — Programmable Rounding (Convergent; Two’s Complement; Truncated) — Prefill mode to precondition the filter before the sample window opens — Supports Multiple Cascading Decimation Filters to implement more complex filter designs — Optional Absolute Integrators on the output of Decimation Filters
• Full duplex synchronous serial in terface (SSI) to an external device — Free-running clock for us e by an external device — Supports a 26-bit message length
• Priority based queues — Supports 6 queues with fixed priority. When commands of distinct queues are bound for the same ADC, the higher priority queue is always served first — Queue_0 can bypass all prioritization, buffering and abor t current conversions to start a Queue_0 conversion a deterministic time after the queue trigger — Supports software and hardware trigger modes to arm a particular queue — Generates interrupt when comm and coherency is not achieved
• External hardware triggers — Supports rising edge, falling edge, high level and low level triggers — Supports configurable digital filter

1.5.15 Deserial serial pe ripheral interface (DSPI)

The DSPI block provides a synchronous serial interface for communication between the MPC5642A MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical DSPI blocks on the MPC5642A MCU. The DSPI pins support 5 V logic levels or Low V oltage Differential Signalling (LVDS) to improve high speed operation. DSPI module features include:

• Selectable LVDS pads working at 40 MHz for SOUT and SCK pins for DSPI_B and DSPI_C
• Support for downstream Micro Second Channel (MSC) with Timed Serial Bus (TSB) configuration on DSPI_B and DSPI_C
• 3 sources of serialized data: eTPU_A, eMIOS output channels, and memory-mapped register in the DSPI
• 4 destinations for deserialized data: eTPU_A and eMIO S input channels, SIU external Interrupt input request, memory-mapped register in the DSPI
• 32-bit DSI and TSB modes require 32 PCR registers, 32 GPO an d GPI registers in the SIU to select either GPIO, eTPU or eMIOS bits for serialization
• The DSPI module can generate an d check parity in a serial frame

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 19 Introduction

1.5.16 Enhanced serial commun ications interface (eSCI)

Three eSCI modules provide asynchronous serial communications with peripheral devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block provides the following features:

• Full-duplex operation
• Standard mark/space non-ret urn-to-zero (NRZ) format
• 13-bit baud rate selection
• Programmable 8-bit or 9-bit data format
• Programmable 12-bit or 13-bit data format for Timed Seri al Bus (TSB) configuration to support the Microsecond bus standard
• Automatic parity generation
• LIN support — Compatible with LIN slaves from revisions 1.x and 2.0 of the LIN standard — Autonomous transmission of entire frames — Configurable to support all revisions of the LIN standard — Automatic parity bit generation — Double stop bit after bit error — 10- or 13-bit break support
• Separately enabled tr ansmitter and receiver
• Programmable transmitter output parity
• 2 receiver wake-up methods: — Idle line wake-up — Address mark wake-up
• Interrupt-driven operation with flags
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• DMA support for both transmit and receive data — Global error bit stored with r eceive data in system RAM to allow post processing of errors

1.5.17 Controller area network (FlexCAN)

The MPC5642A MCU includes three FlexCAN blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64 message buffers. The FlexCAN modules provide the following features:

• Based on and including all existing feat ures of the Freescale TouCAN module
• Full Implementation of the CAN protocol specification, Version 2.0B — Standard data and remote frames — Extended data and remote frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbit/s
• Content-related addressing
• 64 message buffers of 0 to 8 bytes data length
• Individual Rx Mask Register per message buffer

MPC5642A Microcontroller Data Sheet, Rev. 3.1

20 Freescale Semiconductor

• Each message buffer configurable as Rx or Tx , all supporting standard and extended messages
• Includes 1088 bytes of embedded memory for message buffer storage
• Includes 256-byte memory for storing individual Rx mask registers
• Full-featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
• Powerful Rx FIFO ID filterin g, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
• Selectable backwards compatibility with previous FlexCAN versions
• Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
• Listen only mode capability
• Programmable loop-back mode supporting self-test operation
• 3 programmable Mask Registers
• Programmable transmit-first scheme: lowest ID , lowest buffer number or highest priority
• Time Stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Warning interrupts when the Rx and Tx Error Counters reach 96
• Independent of the transmission medium (an external transceiver is assumed)
• Multi-master concept
• High immunity to EMI
• Short latency time due to an arbitr ation scheme for high-priority messages
• Low power mode, with programmable wakeup on bus activity

1.5.18 FlexRay

The MPC5642A includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. Features include:

• Single channel support
• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
• 128 message buffers, each configurable as: — Receive message buffer — Single-buffered transmit message buffer — Double-buffered transmit message buffer (combines two single-buffered message buffers)
• 2 independent receive FIFOs — 1 receive FIFO per channel — Up to 255 entries for each FIFO
• ECC support

1.5.19 System timers

The system timers include two distinct types of system timer:

• Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
• Operating system task monitors using the System Timer Module (STM)

1.5.19.1 Periodic interrupt timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 21 Introduction triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power stop mode. The following features are implemented in the PIT:

• 5 independent timer channels
• Each channel includes 32-bit wide down counter with automatic reload
• 4 channels clocked from system clock
• 1 channel clocked from cr ystal clock (wake-up timer)
• Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined time-out period
• Each channel optionally able to generate an interrupt requ est or a trigger event (to trigger eQADC queues) when timer reaches zero

1.5.19.2 System timer module (STM)

The STM is designed to implement the software task monitor as defined by AUTOSAR1. It consists of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value. The following features are implemented in the STM:

• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode

1.5.20 Software watchdog timer (SWT)

The SWT is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. The following features are implemented:

• 32-bit modulus counter
• Clocked by system clock or crystal clock
• Optional programmable watchdog window mode
• Can optionally cause system reset or interrupt request on timeout
• Reset by writing a software key to memory mapped register
• Enabled out of reset
• Configuration is protected by a software key or a write-once register

1.5.21 Cyclic redundancy check (CRC) module

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

• Support for CRC-16-CCITT ( x25 protocol): — x16 + x12 + x5 + 1
• Support for CRC-32 (E thernet protocol): — x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 1. AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

22 Freescale Semiconductor

• Zero wait states for each write/read operations to th e CRC_CFG and CRC_INP registers at the maximum frequency

1.5.22 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores. The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes these features:

• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
• For test purposes, optional registers to specify the ge neration of double-bit memory errors are enabled on the MPC5642A. The sources of the ECC errors are:
• Flash memory
• S R A M
• Peripheral RAM (FlexRay, CAN, eTPU2 parameter RAM)

1.5.23 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

• Duplicated periphery
• Master access privilege level per peripheral (per master: read access enable; write access enable)
• Write buffering for peripherals
• Checker applied on PBRIDGE output toward periphery
• Byte endianess swap capability

1.5.24 Calibration bus interface

The calibration bus interface controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal connector in the calibration address space. The calibration bus interface is only available in the VertiCal Calibration System. Features include:

• Memory controller supports various memory types
• 16-bit data bus, up to 22-bit address bus
• Pin muxing supports 32-bit muxed bus
• Selectable drive strength
• Configurable bus speed modes
• Bus monitor
• Configurable wait states

1.5.25 Power management controller (PMC)

The PMC contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the 3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1), and the 5 V supply of the regulators (VDDREG).

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 23 Pinout and signal description

1.5.26 Nexus port controller (NPC)

The NPC block provides real-time Nexus Class3+ development support capabilities for the MPC5642A Power Architecture technology-based MCU in compliance with the IEEE-ISTO 5001-2010 standard. MDO port widths of 4 pins and 12 pins are available in all packages.

1.5.27 JTAG controller (JTAGC)

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features:

• IEEE 1149.1-2001 Test Access Port (TAP) in terface 4 pins (TDI, TMS, TCK, and TDO)
• A 5-bit instruction register th at supports the following IEEE 1149.1-2001 defined instructions: — BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
• A 5-bit instruction register that supports the additional following public instructions: — ACCESS_AUX_TAP_NPC — ACCESS_AUX_TAP_ONCE — ACCESS_AUX_TAP_eTPU — ACCESS_CENSOR
• 3 test data registers to support JTAG Boundary Scan mode — Bypass register — Boundary scan register — Device identification register
• A TAP controller state machine that cont rols the operation of the data registers, instruction register and associated circuitry
• Censorship Inhibit Register — 64-bit Censorship password register — If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset.

1.5.28 Development trigger semaphore (DTS)

MPC5642A devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables user software to signal to an external tool—by driving a persis tent (affected only by reset or an external tool) signal on an external device pin—that data is available. The DTS includes a register of semaphores (32-bits) and an identification register. There are a variety of ways this module can be used, including as a component of an external real-time data acquisition system.

2 Pinout and signal description

This section contains the pinouts for all production packages for the MPC5642A device. For pin signal descriptions, please refer to Table 3 NOTE Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage.

24 Freescale Semiconductor

Figure 2. 176-pin LQFP pinout (top view) Note: Pin 96 (VSS) should be tied low.

Figure 3. 208-pin MAPBGA package ballmap (viewed from above)

26 Freescale Semiconductor

Figure 4. 324-pin TEPBGA package ballmap (northwest, viewed from above)

Figure 5. 324-pin TEPBGA package ballmap (southwest, viewed from above)

28 Freescale Semiconductor

Figure 6. 324-pin TEPBGA package ballmap (northeast, viewed from above)

Figure 7. 324-pin TEPBGA package ballmap (southeast, viewed from above)

2.4 Signal summary

Table 3. MPC5642A signal properties

85 M15 U21

340 I/O

345 I/O

Table 3. MPC5642A signal properties (continued)

102 I/O

105 I/O

114 I/O

61 N3 Y12

115 I/O

60 M3 W12

116 I/O

59 P2 AA11

117 I/O

118 I/O

56 N2 W11

119 I/O

54 M4 AB11

120 I/O

53 L3 AB10

121 I/O

52 K3 AA10

122 I/O

51 N1 Y10

123 I/O

50 M2 AA9

124 I/O

49 M1 AA4

125 I/O

48 L2 AB4

126 I/O

47 L1 AB3

127 I/O

46 J4 AB2

128 I/O

42 J3 AA2

129 I/O

40 K2 AA1

130 I/O

39 K1 Y2

131 I/O

38 H3 Y1

132 I/O

37 H4 W3

133 I/O

36 J2 W2

134 I/O

35 J1 W1

135 I/O

34 G4 N4

136 I/O

32 H2 N3

137 I/O

30 H1 M1

138 I/O

28 G1 M2

139 I/O

27 G3 M3

140 I/O

26 F3 L2

141 I/O

25 G2 L1

142 I/O

24 F1 M4

143 I/O

23 F2 L3

144 I/O

22 E1 L4

145 I/O

21 E2 K1

179 I/O

180 I/O

181 I/O

182 I/O

66 R6 AA13

183 I/O

67 R5 AB13

184 I/O

185 I/O

186 I/O

187 I/O

188 I/O

189 I/O

73 N8 AA15

190 I/O

75 R8 AB15

191 I/O

76 N10 AB16

192 I/O

77 T8 AA16

193 I/O

194 I/O

195 I/O

196 I/O

197 I/O

198 I/O

199 I/O

200 I/O

201 I/O

202 I/O

1 The suffix “_O” identifies an output-only eTPU channel

function or GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal. appropriate number of leading zeroes from these values. 4 The Pad Configuration Register (PCR) PA field is used by software to select pin function. example, PCR[190] refers to the SIU register named SIU_PCR190. range (10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/ 10%).

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Pinout and signal description Freescale Semiconductor48 7 See Table 4 for details on pad types. 8 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O (output), I (input), Up (weak pull up enabled), Down (weak pull down enabled), Low (output driven low), High (output driven high). A dash for the function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the pin is enabled. 9 When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.

10 Maximum frequency is 50 kHz

11 PCR219 controls two different pins: MCKO and GPIO[219]. Please refer to Pad Configuration Register 219 section in SIU chapter of device reference manual for details. 12 On 176 LQFP and 208 MAPBGA packages, this pin is tied low internally. 13 These pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of this pin once enabled. 14 The BAM uses this pin to select if auto baud rate is on or off.

15 Output only

16 This signal name is used to support legacy naming. 17 Do not use VRC33 to drive external circuits. 18 VDDEH1A, VDDEH1B and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 19 VDDEH4, VDDEH4A, VDDEH4B and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 20 VDDEH6, VDDEH6A, VDDEH6B and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 21 VDDEH7, VDDEH7A and VDDE7B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

2.5 Signal details

Table 4. Pad types

1 Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function

is selected, otherwise they are high swing. 2 VDDEH7 supply cannot be below 4.5 V when in low-swing mode. Table 5. Signal details for compatibility with MPC55xx devices. If RSTCFG is 1, XTAL oscillator mode is selected.

50 Freescale Semiconductor

an external Analog Mux for expansion channels. Table 5. Signal details (continued)

which is used for timing of the MDO and MSEO signals. oscillator clock achieves stability and is then negated. read/write access registers.

52 Freescale Semiconductor

initiate a FlexCAN or eSCI boot. the boot modes specified by the BOOTCFG1 pin. cycles before the negation of the RSTOUT pin. Register (SIU_EIISR)” for more information.

configured using a dedicated SIU_PCR register. the device is in reset causes the reset cycle to start over. switch point of the input buffer logic of the VDDEH input pins. VIH specifications for the VDDEH input pins. BOOTCFG[0:1] configuration signals.

54 Freescale Semiconductor

Table 6. Power/ground segmentation

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 55

Electrical characteristics

3 Electrical characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5642A series of MCUs. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.

3.1 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 7 are used and the parameters are tagged accordingly in the tables where appropriate. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. Table 7. Parameter classifications P Those parameters are guaranteed during production testing on each individual device. relevant sample size across process variations. D Those parameters are derived mainly from simulations.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

56 Freescale Semiconductor

3.2 Maximum ratings

Table 8. Absolute maximum ratings1 device reliability or cause permanent damage to the device.

0.3 V10

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 57 6 All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH. 7 Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. 8 AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 9 Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 10 Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 11 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 12 Total injection current for all analog input pins must not exceed 15 mA. 13 Lifetime operation at these specification limits is not guaranteed.

14 Solder profile per IPC/JEDEC J-STD-020D

15 Moisture sensitivity per JEDEC test method A112

MPC5642A Microcontroller Data Sheet, Rev. 3.1

58 Freescale Semiconductor

3.3 Thermal characteristics

Table 9. Thermal characteristics for 176-pin LQFP1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. meets JEDEC specification for this package. specification for the specified package. temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. parameter is written as Psi-JT. Table 10. Thermal characteristics for 208-pin MAPBGA 1, 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization.

3 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal

4 Per JEDEC JESD51-6 with the board horizontal

measured on the top surface of the board near the package. method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 59

3.3.1 General notes for specification s at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: TJ = TA + (RJA * PD) Eqn. 1 where: TA = ambient temperature for the package (°C) RJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the application board (number of planes)
• Effective size of the boar d which cools the component
• Quality of the thermal and elect rical connections to the planes
• Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. 7 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 11. Thermal characteristics for 324-pin TEPBGA1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. meets JEDEC specification for this package. specification for the specified package. temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. parameter is written as Psi-JT.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

60 Freescale Semiconductor

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

• One oz. (35 micron nominal thickness) internal planes
• Components that are well separated
• Overall power dissipation on the board is less than 0.02 W/cm 2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed-box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using Equation 2: TJ = TB + (RJB * PD) Eqn. 2 where: TB = board temperature for the package perimeter (°C) RJB = junction-to-board thermal resistance (°C/W) per JESD51-8S PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA Eqn. 3 where: RJA = junction-to-ambient thermal resistance (°C/W) RJC = junction-to-case thermal resistance (°C/W) RCA = case to ambient thermal resistance (°C/W) RJC is device-related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using Equation 4: TJ = TT + (JT x PD) Eqn. 4 where: TT = thermocouple temperature on top of the package (°C)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 61 JT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References:

• Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134 USA Phone (+1) 408-943-6900

• MIL-SPEC and EIA/JESD (JEDEC) speci fications available from Global Engineering Documents (phone (+1) 800-854-7179 or (+1) 303-397-7956)
• JEDEC specifications available on the Web at http://www.jedec.org
• C.E. Triplett and B. Joiner, “ An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
• G . Kromann, S. Shidore, and S. Addison, “ Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic Packaging and Production, pp. 53-58, March 1998.
• B. Joiner and V . Adams, “ Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

3.4 EMI (electromagnetic interference) characteristics

Table 12. EMI testing specifications1 1 EMI testing and I/O port waveforms per standard IEC 61967-2.

30 MHz–1 GHz —

16 MHz crystal

40 MHz bus

MPC5642A Microcontroller Data Sheet, Rev. 3.1

62 Freescale Semiconductor

3.5 Electrostatic discharge (ESD) characteristics

3.6 Power management control (PMC) and power on reset (POR)

Table 13. ESD ratings 1,2 Table 14. PMC operating conditions and external regulators supply voltage 1 An internal regulator controller can be used to regulate the core supply. 2 The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V. 3 An internal regulator can be used to regulate the 3.3 V supply.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 63 Table 15. PMC electrical characteristics

MPC5642A Microcontroller Data Sheet, Rev. 3.1

64 Freescale Semiconductor

5d Idd3p3 CC C Voltage regulator 3.3 V maximum DC output current 80 — — mA 5e Vdd33 ILim CC C Voltage regulator 3.3 V DC current limit — 130 — mA 6 Lvi3p3 CC C Nominal LVI for rising 3.3 V supply 6 — 3.090 — V 6a — CC C Variation of LVI for rising 3.3 V supply at power-on reset7 Lvi3p3 6% Lvi3p3 Lvi3p3 +6 % V 6b — CC C Variation of LVI for rising 3.3 V supply after power-on reset7 Lvi3p3 3% Lvi3p3 Lvi3p3 +3 % V 6c — CC C Trimming step LVI 3.3 V — 20 — mV 6d Lvi3p3_h CC C LVI 3.3 V hysteresis — 60 — mV 7 Por3.3V_r CC C Nominal POR for rising 3.3 V supply 8 —2 . 0 7—V 7a — CC C Variation of POR for rising 3.3 V supply Por3.3V_r  35% Por3.3V_r Por3.3V_r +3 5 % V 7b Por3.3V_f CC C Nominal POR for falling 3.3 V supply — 1.95 — V 7c — CC C Variation of POR for falling 3.3 V supply Por3.3V_f  35% Por3.3V_f Por3.3V_f +3 5 % V 8 Lvi5p0 CC C Nominal LVI for rising 5 V VDDREG supply — 4.290 — V 8a — CC C Variation of LVI for rising 5 V VDDREG supply at power-on reset Lvi5p0 6% Lvi5p0 Lvi5p0 +6 % V 8b — CC C Variation of LVI for rising 5 V VDDREG supply power-on reset Lvi5p0 3% Lvi5p0 Lvi5p0 +3 % V 8c — CC C Trimming step LVI 5 V — 20 — mV 8d Lvi5p0_h CC C LVI 5 V hysteresis — 60 — mV 9 Por5V_r CC C Nominal POR for rising 5 V VDDREG supply — 2.67 — V 9a — CC C Variation of POR for rising 5 V VDDREG supply Por5V_r  35% Por5V_r Por5V_r +3 5 % V 9b Por5V_f CC C Nominal POR for falling 5 V VDDREG supply —2 . 4 7—V 9c — CC C Variation of POR for falling 5 V VDDREG supply Por5V_f  35% Por5V_f Por5V_f +3 5 % V 1 Using external ballast transistor. 2 Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset. 3 LVI for falling supply is calculated as LVI rising – LVI hysteresis. 4 Lvi1p2 tracks DC target variation of internal VDD regulator. Minimum and maximum Lvi1p2 correspond to minimum and maximum VDD DC target respectively.

5 With internal load up to Idd3p3

6 The Lvi3p3 specs are also valid for the VDDEH LVI

7 Lvi3p3 tracks DC target variation of internal VDD33 regulator. Minimum and maximum Lvi3p3 correspond to minimum and maximum VDD33 DC target respectively. Table 15. PMC electrical characteristics (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 65

3.6.1 Regulator example

In designs where the MPC5642A microcontroller’s internal regulators are used, a ballast is required for generation of the 1.2 V internal supply. No ballast is required when an external 1.2 V supply is used. Figure 8. Core voltage regulator controller external components preferred configuration Table 16. MPC5642A External network specification

MPC5642A Microcontroller Data Sheet, Rev. 3.1

66 Freescale Semiconductor

3.6.2 Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor™ BCP68T1 or NJD2873 as well as Philips Semiconductor™ BCP68. The collector of th e external transistor is preferably connected to the same voltage supply source as the output stage of the regulator.

3.7 Power up/down sequencing

There is no power sequencing required among power sources during power up and power down, in order to operate within specification. Although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes, the state of the I/O pins during power up/down varies according to Table 18 for all pins with pad type fast, and Table 19 for all pins with pad type medium, slow, and multi-voltage. Creg — 10 F — It depends on external Vreg. Rc 1.1 — 5.6 May or may not be required. It depends on the allowable power dissipation of T1. Table 17. Transistor recommended operating characteristics Table 18. Power sequence pin states—Fast type pads Table 16. MPC5642A External network specification (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 67

3.8 DC electrical specifications

Table 19. Power sequence pin states—Medium, slow and multi-voltage type pads Table 20. DC electrical specifications1

MPC5642A Microcontroller Data Sheet, Rev. 3.1

68 Freescale Semiconductor

VIL_LS SR P Multi-voltage I/O pad input low voltage in Low-swing-mode7,8,9,10 Hysteresis enabled V SS  0.3 — 0.8 V P Hysteresis disabled V SS  0.3 — 0.9 VIL_HS SR P Multi-voltage pad I/O input low voltage in high-swing-mode Hysteresis enabled V SS  0.3 — 0.35 V DDEH V P Hysteresis disabled V SS  0.3 — 0.4 V DDEH VIH_S SR P Slow/medium pad I/O input high voltage Hysteresis enabled 0.65 V DDEH —V DDEH +0 . 3 V P Hysteresis disabled 0.55 V DDEH —V DDEH +0 . 3 VIH_F SR P Fast I/O input high volt age Hysteresis enabled 0.65 V DDE —V DDE +0 . 3 V P Hysteresis disabled 0.58 V DDE —V DDE +0 . 3 VIH_LS SR P Multi-voltage pad I/O input high voltage in low-swing-mode 7,8,9,10 Hysteresis enabled 2.5 — V DDE +0 . 3 V P Hysteresis disabled 2.2 — V DDE +0 . 3 VIH_HS SR P Multi-voltage I/O input high voltage in high-swing-mode Hysteresis enabled 0.65 V DDEH —V DDEH +0 . 3 V P Hysteresis disabled 0.55 V DDEH —V DDEH +0 . 3 VOL_S CC P Slow/medium pad I/O output low voltage11 —— — 0 . 2 * V DDEH V VOL_F CC P Fast I/O output low voltage11 —— — 0 . 2 * V DDE V VOL_LS CC P Multi-voltage pad I/O output low voltage in low-swing mode 7,8,9,10,11 —— — 0 . 6 V VOL_HS CC P Multi-voltage pad I/O output low voltage in high-swing mode —— — 0 . 2 V DDEH V VOH_S CC P Slow/medium I/O output high voltage11 —0 . 8 V DDEH —— V VOH_F CC P Fast pad I/O output high voltage11 —0 . 8 V DDE —— V VOH_LS CC P Multi-voltage pad I/O output high voltage in low-swing mode7,8,9,10,11 —2 . 3 3 . 1 3 . 7 V VOH_HS CC P Multi-voltage pad I/O output high voltage in high-swing mode11 —0 . 8 V DDEH —— V VHYS_S CC P Slow/medium/multi-voltage I/O input hysteresis —0 . 1 * V DDEH —— V VHYS_F CC P Fast I/O input hysteresis — 0.1 * V DDE —— V VHYS_LS CC C Low-swing-mode multi-voltage I/O input hysteresis Hysteresis enabled 0.25 — — v Table 20. DC electrical specifications1 (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 69 IDD+IDDPLL CC P Operating current 1.2 V supplies VDD @1.32 V @8 0M H z — — 300 mA PV DD @ 1.32 V @ 120 MHz — — 360 mA PV DD @ 1.32 V @ 150 MHz — — 400 mA IDDSTBY CC T Operating current 0.95-1.2 V VSTBY at 55 oC — 35 100 A T Operating current 2–5.5 V VSTBY at 55 oC — 45 110 A IDDSTBY27 CC P Operating current 0.95-1.2 V VSTBY 27 oC — 25 90 A P Operating current 2-5.5 V VSTBY 27 oC — 35 100 A IDDSTBY150 CC P Operating current 0.95-1.2 V VSTBY 150 oC — 790 2000 A P Operating current 2–5.5 V VSTBY at 150 oC — 760 2000 A IDDPLL CC P Operating current 1.2 V supplies VDDPLL, 80 MHz, VDD=1.2 V — — 15 mA IDDSLOW IDDSTOP CC C V DD low-power mode operating current @ 1.32 V Slow mode12 — — 191 mA C Stop mode 13 — — 190 IDD33 CC P Operating current 3.3 V supplies VRC33 2 —— 6 0 m A IDDA IREF IDDREG CC P Operating current 5.0 V supplies VDDA — — 30.0 mA P Analog reference supply current (transient) —— 1 . 0 PV DDREG —— 7 0 14 IDDH1 IDDH4 IDDH6 IDDH7 IDD7 IDDH9 IDD12 CC P Operating current V DDE supplies VDDEH1 — — See note 15 mA PV DDEH4 —— PV DDEH6 —— PV DDEH7 —— PV DDE7 —— PV DDEH9 —— PV DDE12 ——

MPC5642A Microcontroller Data Sheet, Rev. 3.1

70 Freescale Semiconductor

IACT_S CC P Slow/medium I/O weak pull-up/down current16 3.0 V–3.6 V 15 — 95 µA P4 . 7 5 V –5.25 V 35 — 200 IACT_F CC P Fast I/O weak pull-up/down current16 1.62 V–1.98 V 36 — 120 µA P2 . 2 5 V –2.75 V 34 — 139 P3 . 0 V –3.6 V 42 — 158 IACT_MV_PU CC C Multi-voltage pad weak pull-up current VDDE =3 . 0–3 . 6V7, multi-voltage, high swing mode only 10 — 75 µA C4 . 7 5 V –5.25 V 25 — 175 IACT_MV_PD CC C Multi-voltage pad weak pull-down current VDDE =3 . 0–3 . 6V7, multi-voltage, all process corners, high swing mode only 10 — 60 µA C4 . 7 5 V –5.25 V 25 — 200 IINACT_D CC P I/O input leakage current 17 — –2.5 — 2.5 µA IIC SR T DC injection current (per pin) — –1.0 — 1.0 mA IINACT_A SR P Analog input current, channel off, AN[0:7]18 — –250 — 250 nA P Analog input current, channel off, all other analog pins18 — –150 — 150 CL CC D Load capacitance (fast I/O)19 DSC(PCR[8:9]) = 0b00 — — 10 pF D DSC(PCR[8:9]) = 0b01 —— 2 0 D DSC(PCR[8:9]) = 0b10 —— 3 0 D DSC(PCR[8:9]) = 0b11 —— 5 0 C IN CC D Input capacitance (digital pins) —— — 7 p F CIN_A CC D Input capacitance (analog pins) —— — 1 0 p F CIN_M CC D Input capacitance (digital and analog pins20) —— — 1 2 p F RPUPD200K SR C Weak pull-up/down resistance21, 200 k option — 130 — 280 k 

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 71 RPUPD100K SR C Weak pull-up/down resistance21, 100 k option — 65 — 140 k  RPUPD5K SR C Weak pull-up/down resistance21, 5 k option 5 V ± 10% supply 1.4 — 5.2 k  C 3.3 V ± 10% supply 1.7 — 7.7 RPUPD5K SR C Weak Pull-Up/Down Resistance21, 5k  Option 5 V ± 5% supply 1.4 — 7.5 k  RPUPDMTCH CC C Pull-up/Down Resistance matching ratios (100K/200K) Pull-up and pull-down resistances both enabled and settings are equal. –2.5 — 2.5 TA (TL to TH) SR P Operating temperature range - ambient (packaged) — –40.0 — 125.0 °C — SR D Slew rate on power supply pins —— — 2 5 V / m s 1 These specifications are design targets and subject to change per device characterization. 2 These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG =0 ) . 3 ADC is functional with 4 V VDDA  4.75 V but with derated accuracy. This means the ADC will continue to function at full speed with no undesirable behavior, but the accuracy will be degraded. 4 The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package devices only. 5 VFLASH is available in the calibration package only. 6 Regulator is functional, with derated performance, with supply voltage down to 4.0 V 7 Multi-voltage power supply cannot be below 4.5 V when in low-swing mode 8 The slew rate (SRC) setting must be 0b11 when in low-swing mode. 9 While in low-swing mode there are no restrictions in transitioning to high-swing mode.

10 Pin in low-swing mode can accept a 5 V input

11 All VOL/VOH values 100% tested with ± 2 mA load except where otherwise noted

12 Bypass mode, system clock @ 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code, 4 x ADC conversion every 10 ms, 2 x PWM channels @ 1 kHz, all other modules stopped. 13 Bypass mode, system clock @ 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped 14 If 1.2V and 3.3V internal regulators are on,then iddreg=70mA If supply is external that is 3.3V internal regulator is off, then iddreg=15mA 15 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 21 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

72 Freescale Semiconductor

3.9 I/O pad current specifications

The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 21 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 21. 18 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to analog pads.

19 Applies to CLKOUT, external bus pins, and Nexus pins

20 Applies to the FCK, SDI, SDO, and SDS pins

21 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics. Table 21. I/O pad average IDDE specifications1

1 Numbers from simulations at best case process, 150 °C

3 Average current is for pad configured as output only

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 73

3.9.1 I/O pad V RC33 current specifications

The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VRC33 currents for all I/O segments. The output pin VRC33 current can be calculated from Table 22 based on the voltage, frequency, and load on all fast pins. The input pin VRC33 current can be calculated from Table 22 based on the voltage, frequency, and load on all medium pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 22. Table 22. I/O pad VRC33 average IDDE specifications1 1 These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 4 In low swing mode, multi-voltage pads must operate in highest slew rate setting, ipp_sre0 = 1, ipp_sre1 = 1.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

74 Freescale Semiconductor

3.9.2 LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz. Table 23. VRC33 pad average DC current1 1 These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. Table 24. DSPI LVDS pad specification

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 75

3.10 Oscillator and PLLMRF M electrical characteristics

TSKEW CC D Differential skew Itphla-tplhbI or Itplhb-tphlaI —— — 0 . 5 n s Termination CC D Transmission line (differential Zo) — 95 100 105 W CC D Temperature — –40 — 150 C Table 25. PLLMRFM electrical specifications1 Table 24. DSPI LVDS pad specification (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

76 Freescale Semiconductor

VILEXT CC D EXTAL input low voltage Crystal mode 13 —V x t a l – 0.4 V TE x t e r n a l reference13,14 0V RC33/2 – 0.4 — CC T XTAL load capacitance — 5 30 pF — CC C XTAL load capacitance 11 4M H z 5 3 0 p F 8M H z 5 2 6

12 MHz 5 23

16 MHz 5 19

20 MHz 5 16

40 MHz 5 8

t lpll CC P PLL lock time 11,15 —— 2 0 0 µ s tdc CC D Duty cycle of reference — 40 60 % fLCK CC D Frequency LOCK range — –6 6 % f sys fUL CC D Frequency un-LOCK range — –18 18 % f sys fCS fDS CC D Modulation depth Center spread ±0.25 ±4.0 % f sys D Down spread –0.5 –8.0 fMOD CC D Modulation frequency 16 —— 1 0 0 k H z 1 All values given are initial design targets and subject to change.

2 Considering operation with PLL not bypassed

3 All internal registers retain data at 0 Hz. 4 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. 5 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. 6 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. 7 This value is determined by the crystal manufacturer and board design. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 9 Proper PC board layout procedures must be followed to achieve specifications. 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 12 Proper PC board layout procedures must be followed to achieve specifications. 13 This parameter is guaranteed by design rather than 100% tested.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 77

3.11 Temperature sensor electrical characteristics

3.12 eQADC electrical characteristics 14 VIHEXT cannot exceed VRC33 in external reference mode. 15 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 16 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 26. Temperature sensor electrical characteristics Table 27. eQADC conversion specifications (operating) the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. Table 28. eQADC single ended conversion specifications (operating)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

78 Freescale Semiconductor

1 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions. 2 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values. 4 Condition applies to two adjacent pins at injection limits. 5 Performance expected with production silicon.

6 All channels have same 10 k <R s<1 0 0k ; Channel under test has Rs=10 k; IINJ=IINJMAX,IINJMIN

Table 29. eQADC differential ended conversion specifications (operating)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 79

3.13 Configuring SRAM wait states

Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no wait state is added. Please see the device reference manual for details. DIFFmax CC C Maximum differential voltage (DANx+ - DANx-) or (DANx- - DANx+)5 PREGAIN set to 1X setting — (VRH - VRL)/2 V DIFFmax2 CC C PREGAIN set to 2X setting — (VRH - VRL)/4 V DIFFmax4 CC C PREGAIN set to 4X setting — (VRH - VRL)/8 V DIFFcmv CC C Differential input Common mode voltage (DANx- + DANx+)/25 —( V RH + VRL)/2 - 5% (V RH + VRL)/2 + 5% V 1 Applies only to differential channels. 2 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated. 3 At VRH – VRL = 5.12 V, one LSB = 1.25 mV. 4 Guaranteed 10-bit mono tonicity. 5 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification. Table 30. Cutoff frequency for additional SRAM wait state 1 Max frequencies including 2% PLL FM. Table 29. eQADC differential ended conversion specifications (operating) (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

80 Freescale Semiconductor

3.14 Platform flash controll er electrical characteristics

3.15 Flash memory electrical characteristics

Table 31. APC, RWSC, WWSC settings vs. frequency of operation1

1 APC, RWSC and WWSC are fields in the flash memory BIUCR register used to

combinations exist—all entries must be taken from the same row. 2 Max frequencies including 2% PLL FM. 3 APC must be equal to RWSC.

20 MHz 0b000 0b000 0b01

61 MHz 0b001 0b001 0b01

90 MHz 0b010 0b010 0b01

123 MHz 0b011 0b011 0b01

153 MHz 0b100 0b100 0b01

Table 32. Flash program and erase specifications1 change pending device characterization. characterized but not guaranteed.

4 Page size is 128 bits (4 words)

5 Time between program suspend resume and the next program suspend request. 6 Time between erase suspend resume and the next erase suspend request.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 81 Table 33. Flash EEPROM module life

48 KB, and 64 KB blocks over

256 KB blocks over the

MPC5642A Microcontroller Data Sheet, Rev. 3.1

82 Freescale Semiconductor

3.16 AC specifications

3.16.1 Pad AC specifications

Table 34. Pad AC specifications (VDDE = 4.75 V)1 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down. with respect to system clock.

8 Can be used on the tester

9 This drive select value is not supported. If selected, it will be approximately equal to 11. 10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.

11 Selectable high/low swing I/O pad with selectable slew in high swing mode only

12 Fast pads are 3.3 V pads. 13 Also has weak pull-up/pull-down.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 83 Table 35. Pad AC specifications (VDDE = 3.0 V)1 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 This parameter is guaranteed by characterization before qualification rather than 100% tested.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

84 Freescale Semiconductor

Figure 9. Pad output delay—Fast pads 6 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down. with respect to system clock. 8 Can be used on the tester. 9 This drive select value is not supported. If selected, it will be approximately equal to 11. 10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down. 11 Selectable high/low swing I/O pad with selectable slew in high swing mode only. 12 Also has weak pull-up/pull-down.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 85 Figure 10. Pad output delay—Slew rate controlled fast, medium, and slow pads

MPC5642A Microcontroller Data Sheet, Rev. 3.1

86 Freescale Semiconductor

3.17 AC timing

3.17.1 Reset and configuration pin timing

Figure 11. Reset and configuration pin timing Table 36. Reset and configuration pin timing1 Table 37. JTAG pin AC electrical characteristics1

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 87 The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG Update-DR state. This prevents the access from being performed and therefore will not signal its completion via the READY (RDY) output unless the JTAG controller receives an additional TCK. In addition, EVTI is not latched into the device unless there are clock transitions on TCK. The tool/debugger must provide at least one TCK clock for the EVTI signal to be recognized by the MCU. When using the RDY signal to indicate the end of a Nexus read/write access, ensure that TCK continues to run for at least one TCK after leaving the Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or by continuing with the next Nexus/JTAG command. Expect the effect of EVTI and RDY to be delayed by edges of TCK. RDY is not available in all device packages. 4t TMSS, tTDIS CC D TMS, TDI Data Setup Time 10 — ns 5t TMSH, tTDIH CC D TMS, TDI Data Hold Time 25 — ns 6t TDOV CC D TCK Low to TDO Data Valid — 22 2 ns 7t TDOI CC D TCK Low to TDO Data Invalid 0 — ns 8t TDOHZ CC D TCK Low to TDO High Impedance — 22 ns 9t JCMPPW CC D JCOMP Assertion Time 100 — ns 10 t JCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 t BSDV CC D TCK Falling Edge to Output Valid — 50 ns 12 t BSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance — 50 ns 13 t BSDHZ CC D TCK Falling Edge to Output High Impedance — 50 ns 14 t BSDST CC D Boundary Scan Input Valid to TCK Rising Edge 25 3 —n s 15 t BSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 25 3 —n s 1 JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA = TL to TH, CL = 30 pF , SRC = 0b11. These specifications apply to JTAG boundary scan only. See Table 38 for functional specifications. 2 Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay. 3 For 20 MHz TCK. Table 37. JTAG pin AC electrical characteristics1 (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

88 Freescale Semiconductor

Figure 12. JTAG test clock input timing Figure 13. JTAG test access port timing

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 89 Figure 14. JTAG JCOMP timing

MPC5642A Microcontroller Data Sheet, Rev. 3.1

90 Freescale Semiconductor

Figure 15. JTAG boundary scan timing

3.17.3 Nexus timing

Table 38. Nexus debug port timing1

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 91 8t EVTOPW CC D EVTO Pulse Width 1 — t MCYC 9t TCYC CC D TCK Cycle Time 4 6,7 —t CYC 9a t TCYC CC D Absolute Minimum TCK Cycle Time 100 8 —n s 10 t TDC CC D TCK Duty Cycle 40 60 % 11 t NTDIS CC D TDI Data Setup Time 10 — ns 12 t NTDIH CC D TDI Data Hold Time 25 — ns 13 t NTMSS CC D TMS Data Setup Time 10 — ns 14 t NTMSH CC D TMS Data Hold Time 25 — ns 15 — CC D TDO propagation delay from falling edge of TCK — 19.5 ns 16 — CC D TDO hold time wrt TCK falling edge (minimum TDO propagation delay) 5.25 — ns 1 All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA =T L to TH, and CL = 30 pF with DSC = 0b10. 2 Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used. 3 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification. 4 This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the actual system frequency being used. 5 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 6 Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 8 This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. Table 38. Nexus debug port timing1 (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

92 Freescale Semiconductor

Figure 16. Nexus output timing Figure 17. Nexus event trigger and test clock timings

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 93 Figure 18. Nexus TDI, TMS, TDO timing Table 39. Nexus debug port operating frequency

208 BGA

324 BGA

1 NPC_PCR[FPM] = 0

2 NPC_PCR[NEXCFG] = 0

496 CSP Reduced port

40 MHz3

MPC5642A Microcontroller Data Sheet, Rev. 3.1

94 Freescale Semiconductor

3 The Nexus AUX port runs up to 40 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than 40 MHz.

4 NPC_PCR[FPM] = 1

5 Set the NPC_PCR[MCKO_DIV] to divide by two if the system frequency is between 40 MHz and 80 MHz inclusive. Set the NPC_PCR[MCKO_DIV] to divide by four if the system frequency is greater than 80 MHz.

6 Pad restrictions limit the Maximum Operation Frequency in these configurations

7 NPC_PCR[NEXCFG] = 1

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 95

3.17.4 Calibration bus interface timing

Table 40. Calibration bus interface maximum operating frequency

66 MHz1

1 Set SIU_ECCR[EBDF] to either divide by two or divide by four if the system frequency is greater than 66 MHz. Table 41. Calibration bus operation timing1

66 MHz2

MPC5642A Microcontroller Data Sheet, Rev. 3.1

96 Freescale Semiconductor

Figure 19. CLKOUT timing (unless stated otherwise), TA =T L to TH, and CL = 30 pF with DSC = 0b10. 66 MHz. The bus division factor should be set accordingly based on the internal frequency being used.

3 Signals are measured at 50% VDDE

4 Refer to fast pad timing in Table 34 and Table 35 (different values for 1.8 V vs. 3.3 V).

5 Measured at 50% of ALE

6 When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns.

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 97 Figure 20. Synchronous output timing

MPC5642A Microcontroller Data Sheet, Rev. 3.1

98 Freescale Semiconductor

Figure 21. Synchronous input timing Figure 22. ALE signal timing

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 99

3.17.5 External interrupt timing (IRQ pin)

Figure 23. External interrupt timing Table 42. External interrupt timing1 2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Table 43. eTPU timing1 TA =T L to TH, and CL = 50 pF with SRC = 0b00. the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5642A Microcontroller Data Sheet, Rev. 3.1

100 Freescale Semiconductor

3.17.7 eMIOS timing

3.17.8 DSPI timing

DSPI channel frequency support for the MPC5642A MCU is shown in Table 45. Timing specifications are in Table 46. Table 44. eMIOS timing1 Table 45. DSPI channel frequency support (scaler value 2) and PBR = 0b01 (prescaler value 3).

80 LVDS 40 Use sysclock /2 divide ratio

Table 46. DSPI timing 1,2

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 101 9t SUI CC Data Setup Time for Inputs D Master (MTFE = 0) VDDEH=4.75–5.25 V 20 — ns D VDDEH=3–3.6 V 22 — DS l a v e 2 — D Master (MTFE = 1, CPHA = 0) 12 8— D Master (MTFE = 1, CPHA = 1) VDDEH=4.75–5.25 V 20 — D VDDEH=3–3.6 V 22 — 10 t HI CC Data Hold Time for Inputs D Master (MTFE = 0) 4— n s DS l a v e 7 — D Master (MTFE = 1, CPHA = 0) 12 21 — D Master (MTFE = 1, CPHA = 1) 4— 11 t SUO CC Data Valid (after SCK edge) D Master (MTFE = 0) VDDEH=4.75–5.25 V — 5 ns D VDDEH=3–3.6 V — 6.3 DS l a v e VDDEH=4.75–5.25 V — 25 D VDDEH=3–3.6 V — 25.7 D Master (MTFE = 1, CPHA = 0) — 21 D Master (MTFE = 1, CPHA = 1) VDDEH=4.75–5.25 V — 5 D VDDEH=3–3.6 V — 6.3 12 t HO CC Data Hold Time for Outputs D Master (MTFE = 0) VDDEH=4.75–5.25 V 5— n s D VDDEH=3–3.6 V 6.3 — DS l a v e 5 . 5 — D Master (MTFE = 1, CPHA = 0) 3 — D Master (MTFE = 1, CPHA = 1) VDDEH=4.75–5.25 V 5— D VDDEH=3–3.6 V 6.3 — 1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type pad_msr. DSPI signals using pad type of pad_ssr have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0 to 3.6 V, TA =T L to TH, and CL = 50 pF with SRC = 0b11. 2 Data is verified at fSYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation). 3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two MPC5642A devices communicating over a DSPI link. 4 The actual minimum SCK cycle time is limited by pad performance. 5 For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output, maximum SCK frequency is 20 MHz. Appropriate clock division must be applied. 6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. Table 46. DSPI timing1,2 (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

102 Freescale Semiconductor

Figure 24. DSPI classic SPI timing (master, CPHA = 0)

7 Timing met when PCSSCK = 3 (01), and CSSCK = 2 (0000)

8 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

9 Timing met when ASC = 2 (0000), and PASC = 3 (01)

10 Timing met when PCSSCK = 3

11 Timing met when ASC = 3

12 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

104 Freescale Semiconductor

Figure 27. DSPI classic SPI timing (slave, CPHA = 1) Figure 28. DSPI modified transfer format timing (master, CPHA = 0)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

106 Freescale Semiconductor

Figure 31. DSPI modified transfer format timing (slave, CPHA = 1) Figure 32. DSPI PCS strobe (PCSS) timing

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 107 3.17.9 eQADC SSI timing Figure 33. eQADC SSI timing Table 47. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)1 CLOAD = 25 pF on all outputs. Pad drive strength set to maximum. 2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

108 Freescale Semiconductor

3.17.10 FlexCAN system clock source

Table 48. FlexCAN engine system clock divider threshold Table 49. FlexCAN engine system clock divider

1 Divides system clock source for FlexCAN engine by 1

2 System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1

3 Divides system clock source for FlexCAN engine by 2

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 109 Packages

4 Packages

4.1 Package mechanical data

4.1.1 176 LQFP

110 Freescale Semiconductor

Figure 34. 176 LQFP package mechanical drawing (part 1) Figure 35. 176 LQFP package mechanical drawing (part 2)

Figure 36. 176 LQFP package mechanical drawing (part 3)

112 Freescale Semiconductor

Figure 37. 208 MAPBGA package mechanical drawing (part 1)

Figure 38. 208 MAPBGA package mechanical drawing (part 2)

114 Freescale Semiconductor

Figure 39. 324 BGA package mechanical drawing (part 1)

Figure 40. 324 BGA package mechanical drawing (part 2)

MPC5642A Microcontroller Data Sheet, Rev. 3.1

116 Freescale Semiconductor

Ordering information

5 Ordering information

Table 50 shows the orderable part numbers for the MPC5642A series. Figure 41. Product code structure Table 50. Orderable part number summary

6 Document revision history

Table 51 summarizes customer facing revisions to this document. Table 51. Revision history

05 Oct 2010 1 Initial release

26 Mar 2012 2 Figure 1 (MPC5642A series block diagram), added ECSM block and its definition in the

minimum value of VDDREG and its footnote. configuration), added “T1” label to indicate the transistor.

118 Freescale Semiconductor

26 Mar 2012 2

04 May 2012 3 Minor editorial changes and improvements throughout.  Added a footnote to the “Nexus” title for this pin group.  Added a footnote to the “Name” entry for EVTO.  Updated the “Status During reset” entry for EVTO. “TBD - To be defined” footnote. removed the “TBD - To be defined” footnote.  Updated values and replaced TBDs with numerical data.  Removed the “TBD - To be defined” footnote.  Updated values and replaced TBDs with numerical data.  Removed the “TBD - To be defined” footnote.  Changed “MPC5642AF0MMG1“ to “SC667201MMG1“.  Changed “MPC5642AF0MMG2“ to “SC667201MMG2“.  Changed “MPC5642AF0MMG3“ to “SC667201MMG3“. 29 Jun 2012 3.1 No content changes, technical or editorial, were made in this revision. Removed the “preliminary” footers throughout. Changed “Data Sheet: Advance Information” to “Data Sheet: Technical Data” on page 1. Removed the “product under development” disclaimer on page 1. Table 51. Revision history (continued)

MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 119 Document revision history

MPC5642A Microcontroller Data Sheet, Rev. 3.1

120 Freescale Semiconductor

Document Number: MPC5642A Rev. 3.1 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2009, 2010, 2012 Freescale Semiconductor, Inc.