SC643EVB

SC643 SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Input supply voltage range — 2.9V to 5.5V Very high effi ciency charge pump driver system with three modes — 1x, 1.5x, and 2x Five programmable current sinks with 29 increments from 0mA to 25mA Four programmable 200mA low-noise LDO regulators Programmable driver confi gurations for main and sub-display backlight Fade-in/fade-out feature for main and sub display backlight SemPulse single wire interface Backlight current accuracy — ±1.5% typical Backlight current matching — ±0.5% typical External enable pin for optional control of LDO4 Automatic sleep mode with LEDs off Shutdown current — 0.1μA typical Ultra-thin package — 3 x 3 x 0.6 (mm) Lead free and Halogen free WEEE and RoHS compliant

Applications

Cellular phones, smart phones, and PDAs LCD display modules Portable media players Digital cameras and GPS units Display backlighting and LED indicators

Description

The SC643 is a high effi ciency charge pump LED driver using Semtech’s proprietary charge pump technology. Performance is optimized for use in single cell Li-ion battery applications. Display backlighting is provided through fi ve matched current sinks with integrated fade-in and fade-out con- trols. The LEDs can be driven as a single set or as two diff erent sets (for main and sub displays) with indepen- dent controls. Four low noise, low dropout (LDO) regulators are provided to supply power for camera module I/O and other peripheral circuits. An external enable pin is also provided for one LDO for added fl exibility. The SC643 uses the proprietary SemPulse ® single wire interface. This interface controls all functions of the device, including backlight currents and LDO voltage outputs. The single wire interface minimizes microcontroller and interface pin counts. The SC643 enters sleep mode when all the LED drivers are disabled. In this mode, the quiescent current is reduced while the device continues to monitor the SemPulse inter- face. Any combination of LDOs may be enabled when in sleep mode. 4.7μF SemPulse Interface Motor Control Main Backlight 4.7μF VBAT = 2.9V to 5.5V 1.0μF1.0μF 22nF 2.2μF2.2μF VLDO1 = 1.5V to 3.3V VLDO2 = 1.2V to 1.8V BL5 BL4 BL3 BL2 BL1 LDO1 LDO2 C2- C2+ C1- C1+ PGND AGND BYP ENL4 SPIF IN OUT LDO3 LDO4 1.0μF1 . 0 μF VLDO3 = 1.5V to 3.3V Motor SC643 Sub Backlight Typical Application Circuit October 8, 2009 US Patents: 6,504,422; 6,794,926

Ordering Information

SC643ULTRT(1)(2) MLPQ-UT-20 3×3 SC643EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. TOP VIEW T IN BL2 PGND BL3 6789 1 0 AGND LDO3 LDO2 SPIF BYP LDO115 1617181920 BL1 LDO4 ENL4 BL5 BL4 OUT C1- C2- C2+ C1+ 643 yyww xxxx MLPQ-UT-20; 3x3, 20 LEAD θJA = 35°C/W yyww = Date Code xxxx = Semtech Lot No.

Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) subscript n = 1, 2, 3, and 4. (2) Tested according to JEDEC standard JESD22-A114-B. (3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Absolute Maximum Ratings OUT , LDOn(1) Recommended Operating Conditions Voltage diff erence between any two LEDs (V) . . . ΔVF ≤ 1.0 Thermal Information Thermal Resistance, Junction to Ambient(3) (°C/W) . . . . 35 Unless otherwise noted, T A = +25°C for Typ, -40ºC to +85°C for Min and Max, T J(MAX) = 125ºC, V IN = 3.7V, C 1= C 2 = 2.2μF, C IN = C OUT = 4.7μF, (ESR = 0.03Ω)(1) Parameter Symbol Conditions Min Typ Max Units Supply Specifi cations Input Supply Voltage V IN 2.9 5.5 V Shutdown Current I Q(OFF) Shutdown, VIN = 4.2V 0.1 2.0 μA Total Quiescent Current I Q Sleep (all LDOs off ), SPIF = VIN (2) 90 135 μA Sleep (all LDOs on), SPIF = VIN (2) 300 450 1x mode, IOUT = 2.5mA, IBLn (3) = 0.5mA, 5 LEDs on 2.5 mA1x mode, IOUT = 125mA, IBLn = 25mA, 5 LEDs on 4.3 1.5x or 2x mode, IOUT = 125mA, IBLn = 25mA, 5 LEDs on 5.1 Charge Pump Electrical Specifi cations Maximum Total Output Current I OUT(MAX) Sum of all active LED currents, VOUT ≤ 4.2V 125 mA Backlight Current Setting Range I BL Nominal setting for BL1 – BL5 0 25 mA Backlight Current Accuracy I BL_ACC IBLn = 12mA -8 ±1.5 8 % Backlight Current Matching(4) IBL-BL IBLn = 12mA -3.5 ±0.5 +3.5 % 1x Mode to 1.5x Mode Falling Transition Voltage VTRANS1x IOUT = 50mA, IBLn = 10mA, VOUT = 3.2V 3.22 V 1.5x Mode to 1x Mode Hysteresis V HYST1x IOUT = 50mA, IBLn = 10mA, VOUT = 3.2V 250 mV

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units Charge Pump Electrical Specifi cations (Cont.) 1.5x Mode to 2x Mode Falling Transition Voltage VTRANS1.5x IOUT = 50mA, IBLn = 10mA, VOUT = 4.2V(5) 2.91 V 2x Mode to 1.5x Mode Hysteresis V HYST1.5x IOUT = 50mA, IBLn = 10mA, VOUT = 4.2V(5) 520 mV Current Sink Off -State Leakage Current IBL/FL(OFF) VIN = VBLn = 4.2V 0.1 1 μA Pump Frequency f PUMP VIN = 3.2V 250 kHz LDO1, LDO3, and LDO4 Voltage Setting Range VLDOm (6) Range of nominal settings 1.5 3.3 V LDO2 Voltage Setting Range V LDO2 Range of nominal settings 1.2 1.8 V Output Voltage Accuracy ΔV LDO ILDO = 1mA, TA = 25°C, 2.9V ≤ VIN ≤ 4.2V -3 ±1.0 +3 % ILDO = 1mA to 100mA, 2.9V ≤ VIN ≤ 4.2V -3.5 +3.5 % Dropout Voltage VDm ILDOm = 150mA, VIN = VLDOm + VDm 150 200 mV VD2 ILDO2 = 100mA, VIN = VLDO2 + VD2 100 150 Current Limit I LIM 200 mA Line Regulation ΔVLINE ILDOm = 1mA, mV ILDO2 = 1mA, Load Regulation ΔVLOAD VLDOm = 3.3V, ILDOm = 1mA to 100mA 25 mV VLDO2 = 1.8V, ILDO2 = 1mA to 100mA 20 Power Supply Rejection Ratio PSRRm 1.5V < VLDOm < 3.0V, f < 1kHz, CBYP = 22nF, ILDOm = 50mA, with 0.5VP-P supply ripple 50 dB PSRR2 1.2V < VLDO2 < 1.8V, f < 1kHz, CBYP = 22nF, ILDO2 = 50mA, with 0.5VP-P supply ripple 60 Output Voltage Noise en-LDOm 10Hz < f < 100kHz, CBYP = 22nF, CLDOm = 1μF, ILDOm = 50 mA, 1.5V < VLDOm < 3.0V μVRMS en-LDO2 10Hz < f < 100kHz, CBYP = 22nF, CLDO2 = 1μF, ILDO2 = 50 mA, 1.2V < VLDO2 < 1.8V Minimum LDO Capacitor (7) CLDO(MIN) Nominal value for CLDOn 1μ F Electrical Characteristics (continued)

Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Digital I/O Electrical Specifi cations (SPIF, ENL4) Input High Threshold (8) VIH VIN = 5.5V 1.6 V Input Low Threshold (8) VIL VIN = 2.9V 0.4 V Input High Current I IH VIN = 5.5V -1 +1 μA Input Low Current I IL VIN = 5.5V -1 +1 μA SemPulse Electrical Specifi cations (SPIF) SemPulse Start-up Time(9) tSU 1m s Bit Pulse Duration (8) tHI 0.75 250 μs Duration Between Bits (8) tLO 0.75 250 μs Hold Time - Address (8) tHOLDA SPIF is held high 500 5000 μs Hold Time - Data (8) tHOLDD SPIF is held high 500 μs Bus Reset Time (8) tBR SPIF is held high 10 ms Shutdown Time(10) tSD SPIF is pulled low 10 ms Fault Protection Output Short Circuit Current Limit I OUT(SC) OUT pin shorted to GND 300 mA Over-Temperature TOTP Rising threshold 165 °C THYS Hysteresis 30 °C Charge Pump Over-Voltage Protection VOVP OUT pin open circuit, VOUT = VOVP 5.7 6.0 V Under Voltage Lockout VUVLO Decreasing VIN 2.4 V VUVLO-HYS 300 mV Notes: (1) Capacitors are MLCC of X5R type. Production tested with higher value capacitors than the application requires. (2) SPIF is high for more than 10ms (3) Subscript for all backlights (BLn), n = 1, 2, 3, 4 and 5. Subscripting for all LDOs (LDOn), n = 1, 2, 3, 4. (4) Current matching is defined as ± [I BL(MAX) - IBL(MIN)] / [IBL(MAX) + IBL(MIN)]. (5) Test voltage is V OUT=4.2V — a relatively extreme LED voltage — to force a transition during test. Typically VOUT=3.2V for white LEDs. (6) Subscript m = 1, 3, and 4 and applies only to LDO1, LDO3, and LDO4. (7) X5R or better “temperature stable” MLCC capacitor. (8) The source driver used to provide the SemPulse output must meet these limits. (9) The SemPulse start-up time is the minimum time that the SPIF pin must be held high to enable the part before commencing communication. (10) The SemPulse shutdown time is the minimum time that the SPIF pin must be pulled low to shut the part down.

Battery Current (5 LEDs) — 25mA Each Backlight Effi ciency (5 LEDs) — 12mA Each Backlight Effi ciency (5 LEDs) — 5.0mA EachBattery Current (5 LEDs) — 5.0mA Each 100 120 140 160 180 200 Battery Current (mA) VOUT = 3.65V, IOUT = 125mA, 25°C VIN(V) Battery Current (5 LEDs) — 12mA Each 100 VIN(V) Battery Current (mA) VOUT = 3.45V, IOUT = 60mA, 25°C 100 VIN(V) % Efficiency VOUT = 3.45V, IOUT = 60mA, 25°C 100 VIN(V) % Efficiency VOUT = 3.28V, IOUT = 25mA, 25°C VIN(V) Battery Current (mA) VOUT = 3.28V, IOUT = 25mA, 25°C Backlight Effi ciency (5 LEDs) — 25mA Each 100 VIN(V) % Efficiency VOUT = 3.65V, IOUT = 125mA, 25°C Typical Characteristics

PSRR vs. Frequency — 2.8VPSRR vs. Frequency — 1.8V Line Regulation (LDO2) LDO Noise vs. Load Current — 1.8V Line Regulation (LDOm) VIN=3.7V, VOUT =1.8V, IOUT = 50mA -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000Frequency (Hz) PSRR (dB) VIN=3.7V, VOUT =2.8V, IOUT = 50mA -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000Frequency (Hz) PSRR (dB) 100 02 0 4 0 6 0 8 0 100 IOUT (mA) VLDO=1.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz Noise (μVRMS) LDO Noise vs. Load Current — 2.8V 100 0 30 60 90 120 150 IOUT (mA) VLDO=2.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz Noise (μVRMS) Typical Characteristics (continued) -0.75 -0.5 -0.25 0.25 0.5 0.75 Output Voltage Variation (mV) ILDO2 = 1mA, VLDO2 = 1.2V to 1.8V, 25°C 1.2V 1.8V VIN (V) Output Voltage Variation (mV) VIN (V) ILDOm = 1mA, 25°C, VLDOm = 1.5V to 3.3V, m = 1, 3, or 4 2.8V

Load Regulation (LDO2) Load Regulation (LDOm) Output Short Circuit Current Limit LDO Load Transient Response (3.3V) Time (1ms/div) VOUT (1V/div) IOUT (200mA/div) VOUT=0V, VIN=4.2V, 25°C Time (20μs/div) VLDO (50mV/div) ILDO (100mA/div) VIN=3.7V, VLDO=3.3V, ILDO=1 to 100mA, 25°C LDO Load Transient Response (1.2V) Time (20μs/div) VLDO (50mV/div) ILDO (100mA/div) VIN=3.7V, VLDO=1.2V, ILDO=1 to 100mA, 25°C LDO Load Transient Response (1.8V) Time (20μs/div) VLDO (50mV/div) ILDO (100mA/div) VIN=3.7V, VLDO=1.8V, ILDO=1 to 100mA, 25°C Typical Characteristics (continued) 1.5V 1.2V -25 -20 -15 -10 0 40 80 120 160 200 ILDO (mA) Output Voltage Variation (mV) VIN=3.6V, 25°C 1.8V -30 -25 -20 -15 -10 0 40 80 120 160 200 ILDO (mA) Output Voltage Variation (mV) VIN=3.6V, 25°C, m = 1, 3, or 4 2.5V 1.8V 3.3V 1.5V 2.8V

Output Open Circuit Protection Time (200μs/div) VBL (500mV/div) VOUT (1V/div) IBL (20mA/div) VIN=3.7V, 25°C Ripple — 1X Mode VIN (50mV/div) VOUT (100mV/div) IBL (20mA/div) VIN=3.8V, 5 Backlights — 25 mA each, 25°C Time (20μs/div) Ripple — 2X Mode VIN (50mV/div) VOUT (100mV/div) IBL (20mA/div) VIN=2.9V, 5 Backlights — 25 mA each, 25°C Time (20μs/div) Ripple — 1.5X Mode VIN (50mV/div) VOUT (100mV/div) IBL (20mA/div) VIN=3.6V, 5 Backlights — 25 mA each, 25°C Time (20μs/div) 5.42V Typical Characteristics (continued)

Pin # Pin Name Pin Function

1 IN Battery voltage input

2 PGND Ground pin for high current charge pump

3 BL3 Current sink output for backlight LED 3 — leave this pin open if unused

4 BL2 Current sink output for backlight LED 2 — leave this pin open if unused

5 BL1 Current sink output for backlight LED 1 — leave this pin open if unused

6 BL4 Current sink output for backlight LED 4 — leave this pin open if unused

7 BL5 Current sink output for backlight LED 5 — leave this pin open if unused

8 ENL4 Enable pin for LDO4 — active high. See LDO4 Control Register Section and Programmable LDO Outputs Section to determine how to use this pin.

9 AGND Analog ground pin — connect to ground and separate from PGND current

10 LDO4 Output of LDO4

11 LDO3 Output of LDO3

12 SPIF SemPulse single wire interface pin — used to enable/disable the device and to confi gure all regis- ters (refer to Register Map and SemPulse Interface sections)

13 BYP Bypass pin for LDO reference — connect a 22nF ceramic capacitor to AGND

14 LDO2 Output of LDO2

15 LDO1 Output of LDO1

16 OUT Charge pump output — all LED anode pins should be connected to this pin

17 C2+ Positive connection to bucket capacitor 2

18 C1+ Positive connection to bucket capacitor 1

19 C1- Negative connection to bucket capacitor 1

20 C2- Negative connection to bucket capacitor 2

T THERMAL PAD Thermal pad for heatsinking purposes — connect to ground plane using multiple vias — not con- nected internally

(1x, 1.5x, 2x) Voltage Setting DAC BL5

This design is optimized for handheld applications sup- plied from a single cell Li-Ion and includes the following key features: A high effi ciency fractional charge pump that supplies power to all LEDs Five matched current sinks that control LED backlighting current, with 0mA to 25mA per LED. Four adjustable LDOs. LDO1 , LDO3, and LDO4 are adjustable with 15 settings from 1.5V to 3.3V. LDO2 is adjustable with 7 settings from 1.2V to 1.8V. An external enable pin for LDO4 allows it to be used as a motor driver with hard-wired control. High Current Fractional Charge Pump The backlight outputs are supported by a high effi ciency, high current fractional charge pump output. The charge pump multiplies the input voltage by 1, 1.5 or 2 times. The charge pump switches at a fi xed frequency of 250kHz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve effi ciency. The mode selection circuit automatically selects the mode as 1x, 1.5x, or 2x based on circuit conditions such as LED voltage, input voltage, and load current. The 1x mode is the most effi cient of the three modes, followed by 1.5x and 2x modes. Circuit conditions such as low input voltage, high output current, or high LED voltage place a higher demand on the charge pump output. A higher numerical mode (1.5x or 2x) may be needed momentarily to main- tain regulation at the OUT pin during intervals of high demand. The charge pump responds to momentary high demands, setting the charge pump to the optimum mode to deliver the output voltage and load current while opti- mizing effi ciency. Hysteresis is provided to prevent mode toggling. The charge pump requires two bucket capacitors for proper operation. One capacitor must be connected between the C1+ and C1- pins and the other must be con- nected between the C2+ and C2- pins as shown in the typical application circuit diagram. These capacitors should be equal in value, with a nominal capacitance of 2.2μF to support the charge pump current requirements. The device also requires a 4.7μF capacitor on the IN pin and a 4.7μF capacitor on the OUT pin to minimize noise and support the output drive requirements. Capacitors with X7R or X5R ceramic dielectric are strongly recom- mended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coeffi cients make them unsuit- able for this application. LED Backlight Current Sinks The backlight current is set via the SemPulse interface. The current is regulated to one of 29 values between 0mA and 25mA. The step size varies depending upon the current setting. Between 0mA and 5mA, the step size is 0.5mA. The step size increases to 1mA for settings between 5mA and 21mA. Steps are 2mA between 21mA and 25mA. The variation in step size allows fi ner adjust- ment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in LED brightness. A zero setting is also included to allow the current sink to be disabled by writing to either the enable bit or the current setting register for maximum fl exibility. All backlight current sinks have matched currents, even when there is variation in the forward voltages (ΔV F ) of the LEDs. A minimum ΔVF of 1.2V is supported when the input voltage (VIN) is at 3.0V. Higher ΔVF LED mis-match is supported when VIN is higher than 3.0V. All current sink outputs are compared and the lowest output is used for setting the voltage regulation at the OUT pin. This is done to ensure that suffi cient bias exists for all LEDs. The backlight LEDs default to the off state upon power- up. For backlight applications using fewer than fi ve LEDs, any unused output must be left open and the unused LED must remain disabled. When writing to the backlight enable register, a zero (0) must be written to the corre- sponding bit of any unused output. Applications Information

Table 1 — Fade-In from Off State Command Sequence Action Data Disable fade for the bank 1. Write to register 09h 00h Set the bank to 0.5mA 2. Write to register 01h and/or 02h(1) 04h Enable fade3. Write to register 09h Binary value xx1xx0, xx1xx1, or xx0xx1 Set BLEN bits4. Write to register 00h Any value from 01h through 1Fh Set new value of backlight current for the bank 5. Write to register 01h and/or 02h Any value from 05h through 1Fh Notes: (1) Write only to the banks which will fade Fade-Out from any On State to Off State Fading the backlight LEDs from any active state to the off state follows a simple procedure. The sequence of com- mands for this action is shown in Table 2. Following these steps explicitly will ensure that the fade-out operation will proceed with no interruption at the rate specifi ed in the Main/Sub Backlight Fade register (09h). This procedure must be followed regardless of the backlight grouping confi guration. Table 2 — Fade-Out from any On State to Off State Command Sequence Action Data Enable fade1. Write to register 09h Any value from 01h through 3Fh (but not 00h) Set Main and/or Sub backlights to 0mA 2. Write to register 01h and/or 02h 00h Fading Between Diff erent On States Fading from one backlight level to another (up or down) also follows a simple procedure. The sequence of com- mands for this action is shown in Table 3. Following these Applications Information (continued) steps explicitly will ensure that the fade-in/fade-out oper- ation will proceed with no interruption at the rate specifi ed in the Main/Sub Backlight Fade register (09h). This proce- dure must be followed regardless of the backlight grouping confi guration. Table 3 — Fading between Diff erent On States Command Sequence Action Data Enable fade1. Write to register 09h Any value from 01h through 3Fh (but not 00h) Set new value of backlight current 2. Write to register 01h and/or 02h Any value from 05h through 1Fh Additional Information For more details about the Fade-in/Fade-out function, refer to the SC643 Backlight Driver Software User’s Guide and SemPulse Interface Specifi cation document and to the associated software drivers available for this device (contact your sales offi ce for more details). Programmable LDO Outputs Four low dropout (LDO) regulators are included to supply power to peripheral circuits. Each LDO output voltage setting has ±3.5% accuracy over the operating tempera- ture range. Output current greater than specifi cation is possible at somewhat reduced accuracy (refer to the typical characteristic section of this datasheet for load regulation examples). LDO1, LDO3, and LDO4 have iden- tical specifi cations, with a programmable output ranging from 1.5V to 3.3V. LDO2 is specifi ed to operate with pro- grammable output ranging from 1.2V to 1.8V. LDO2 also has lower noise specifi cations so that it can be used with noise sensitive circuits. LDO4 is controlled by both the enable pin ENL4 and the LDO4 control register. ENL4 may be permanently con- nected to V IN for software-only control. Alternately, power sequencing logic may be used to enable LDO4 via the ENL4 pin after writing to the LDO4 control register.

Applications Information (continued) Shutdown Mode The device is disabled when the SPIF pin is held low for the shutdown time specifi ed in the electrical characteris- tics section. All registers are reset to default condition at shutdown. Typical current consumption is this mode is 0.1μA Sleep Mode When all backlights are off the charge pump is disabled, and sleep mode is activated. This is a reduced current mode that helps minimize overall current consumption. In sleep mode, the SemPulse interface continues to monitor its input for commands from the host. Typical current consumption in this mode is 90μA. Protection Features The SC643 provides several protection features to safe- guard the device from catastrophic failures. These features include: Output Open Circuit Protection Over-Temperature Protection Charge Pump Output Current Limit LDO Current Limit LED Float Detection Output Open Circuit Protection Over-Voltage Protection (OVP) at the OUT pin prevents the charge pump from producing an excessively high output voltage. In the event of an open circuit between the OUT pin and all current sinks (no loads connected), the charge pump runs in open loop and the voltage rises up to the OVP limit. OVP operation is hysteretic, meaning the charge pump will momentarily turn off until V OUT is suffi ciently reduced. The maximum OVP threshold is 6.0V, allowing the use of a ceramic output capacitor rated at 6.3V with no concern of over-voltage damage. Typical OVP voltage is 5.7V. Over-Temperature Protection The Over-Temperature (OT) protection circuit prevents the device from overheating and experiencing a catastrophic failure. When the junction temperature exceeds 165 °C, the device goes into thermal shutdown with all outputs dis- abled until the junction temperature is reduced. All register information is retained during thermal shutdown. Hysteresis of 30 °C is provided to ensure that the device cools suffi ciently before re-enabling. Charge Pump Output Current Limit The device limits the charge pump current at the OUT pin. When OUT is shorted to ground, the output current will typically equal 300mA. The output current is also limited to 300mA when over loaded resistively. LDO Current Limit The device limits the current at all LDO output pins. The minimum limit is 200mA, so load current of greater than the rated current can be used (with degraded accuracy) without tripping the current limit. LED Float Detection Float detect is a fault detection feature of the LED back- light outputs. If an output is programmed to be enabled and an open circuit fault occurs at any backlight output, that output will be disabled to prevent a sustained output OVP condition from occurring due to the resulting open loop. Float detect ensures device protection but does not ensure optimum performance. Unused LED outputs must be disabled to prevent an open circuit fault from occurring. Thermal Management The device has the potential for peak power dissipation equal to 2.7W when all outputs are simultaneously oper- ating at maximum rated current and powered by a fully charged Li-Ion cell equal to 4.2V. A calculation of the maximum power dissipation of the device should be done to identify if power management measures are needed to prevent overheating. The MLP package is capable of dis- sipating 1.85W when proper layout techniques are used.

tHOLDD when the pulse train is completed. If the proper hold time is not received, the interface will keep counting pulses until the hold time is detected. If the total exceeds 63 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. After the bus has been held high for t HOLDD, the bus will expect the next pulse set to be an address write. Note that this is the same eff ect as the bus reset that occurs when t HOLDA exceeds its maximum specification. For this reason, there is no maximum limit on t HOLDD — the bus simply waits for the next valid address to be transmitted. Multiple Writes It is important to note that this single-wire interface requires the address to be paired with its corresponding data. If it is desired to write multiple times to the same address, the address must always be re-transmitted prior to the corresponding data. If it is only transmitted one time and followed by multiple data transmissions, every other block of data will be treated like a new address. The result will be invalid data writes to incorrect addresses. Note that multiple writes only need to be separated by the minimum t HOLDD for the slave to interpret them cor- rectly. As long as tHOLDA between the address pulse set and the data pulse set is less than its maximum specifi cation but greater than its minimum, multiple pairs of address and data pulse counts can be made with no detrimental eff ects. Standby Mode Once data transfer is completed, the SPIF line must be returned to the high state for at least 10ms to return to the standby mode. In this mode, the SPIF line remains idle while monitoring for the next command. This mode allows the device to minimize current consumption between commands. Once the device has returned to standby mode, the bus is automatically reset to accept the address pulses as the next data block. This safeguard is intended to reset the bus to a known state (waiting for the beginning of a write sequence) if the delay exceeds the reset threshold. Introduction SemPulse is a write-only single wire interface. It provides access to up to 32 registers that control device functional- ity. Two sets of pulse trains are transmitted to generate a complete SemPulse command. The fi rst pulse set is used to set the desired address. After the bus is held high for the address hold period, the next pulse set is used to write the data value. After the data pulses are transmitted, the bus is held high again for the data hold period to signify the data write is complete. At this point the device latches the data into the address that was selected by the fi rst set of pulses. See the SemPulse Timing Diagrams for descrip- tions of all timing parameters. Chip Enable/Disable The device is enabled when the SemPulse interface pin (SPIF) is pulled high for greater than t SU. If the SPIF pin is pulled low again for more than t SD, the device will be disabled. Address Writes The fi rst set of pulses can range between 0 and 31 (or 1 to 32 rising edges) to set the desired address. After the pulses are transmitted, the SPIF pin must be held high for t HOLDA to signal to the slave device that the address write is fi nished. If the pulse count is between 0 and 31 and the line is held high for t HOLDA, the address is latched as the destination for the data word. If the SPIF pin is not held high for t HOLDA, the slave device will continue to count pulses. If the total exceeds 31 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. Note that if t HOLDA exceeds its maximum specifi cation, the bus will reset. This means that the com- munication is ignored and the bus resumes monitoring the pin, expecting the next pulse set to be an address. Data Writes After the bus has been held high for the minimum address hold period, the next set of pulses are used to write the data value. The total number of pulses can range from 0 to 63 (or 1 to 64 rising edges) since there are a total of 6 register bits per register. Just like with the address write, the data write is only accepted if the bus is held high for SemPulse® Interface

Register Map(1) Address(2) D5 D4 D3 D2 D1 D0 Reset Value Description 00h 0 (3) BL5EN BL4EN BL3EN BL2EN BL1EN 00h Backlight Enable 01h 0 (3) MBL4 MBL3 MBL2 MBL1 MBL0 00h Main Backlight Current 02h 0 (3) SBL4 SBL3 SBL2 SBL1 SBL0 00h Sub Backlight Current 05h 0 (3) 0(3) LDO1V3 LDO1V2 LDO1V1 LDO1V0 00h LDO1 06h 0 (3) 0(3) 0(3) LDO2V2 LDO2V1 LDO2V0 00h LDO2 07h 0 (3) 0(3) LDO3V3 LDO3V2 LDO3V1 LDO3V0 00h LDO3 08h 0 (3) 0(3) LDO4V3 LDO4V2 LDO4V1 LDO4V0 00h LDO4 09h SFADE1 SFADE0 SFADE MFADE1 MFADE0 MFADE 00h Main/Sub Backlight Fade 0Ah 0 (3) 0(3) 0(3) MB2 MB1 MB0 00h Main/Sub Bank Select Notes: (1) all registers are write-only (2) Addresses 03h and 04h are not used (3) 0 = always write a 0 to these bits Defi nition of Registers and Bits BL Enable Control Register (00h) This register enables the backlight current sinks. Bit D5 This bit is unused and is always a zero. BL5EN through BL1EN [D4:D0] These bits are used to enable current sinks. These current sinks will then sink whatever current is set in the corre- sponding current control register. Main Backlight Current Control Register (01h) This register is used to set the currents for the LED drivers designated as main backlight current sinks. Note these current sinks can be disabled using register 00h or by writing the 0mA value into this register. Bit D5 This bit is unused and is always a zero.

Register Map (continued) MBL4 through MBL0 [D4:D0] These bits are used to set the current for the main back- light current sinks. All enabled current sinks will sink the same current as shown in Table 4. Table 4 — Main Backlight Current Settings MBL4 MBL3 MBL2 MBL1 MBL0 Backlight Current (mA) 0000 0 0 0 0 0 0 1 See note (1) 0 0 0 1 0 See note (1) 0 0 0 1 1 See note (1) 0 0 1 0 0 0.5 0010 1 1 0 0 1 1 0 1.5 0011 1 2 0 1 0 0 0 2.5 0100 1 3 0 1 0 1 0 3.5 0101 1 4 0 1 1 0 0 4.5 0110 1 5 0111 0 6 0111 1 7 1000 0 8 1000 1 9 1001 0 1 0 1001 1 1 1 1010 0 1 2 1010 1 1 3 1011 0 1 4 1011 1 1 5 1100 0 1 6 1100 1 1 7 1101 0 1 8 1101 1 1 9 1110 0 2 0 1110 1 2 1 1111 0 2 3 1111 1 2 5 (1) Reserved for future use. Sub Backlight Current Control Register (02h) This register is used to set the currents for the LED drivers designated as sub backlight current sinks. Note these current sinks can be disabled using register 00h or by writing the 0mA value into this register. Bit D5 This bit is unused and is always a zero.

Register Map (continued) SBL4 through SBL0 [D4:D0] These bits are used to set the current for the sub backlight current sinks. All enabled current sinks will sink the same current as shown in Table 5. Table 5 — Sub Backlight Current Settings SBL4 SBL3 SBL2 SBL1 SBL0 Backlight Current (mA) 0000 0 0 0 0 0 0 1 See note (1) 0 0 0 1 0 See note (1) 0 0 0 1 1 See note (1) 0 0 1 0 0 0.5 0010 1 1 0 0 1 1 0 1.5 0011 1 2 0 1 0 0 0 2.5 0100 1 3 0 1 0 1 0 3.5 0101 1 4 0 1 1 0 0 4.5 0110 1 5 0111 0 6 0111 1 7 1000 0 8 1000 1 9 1001 0 1 0 1001 1 1 1 1010 0 1 2 1010 1 1 3 1011 0 1 4 1011 1 1 5 1100 0 1 6 1100 1 1 7 1101 0 1 8 1101 1 1 9 1110 0 2 0 1110 1 2 1 1111 0 2 3 1111 1 2 5 (1) Reserved for future use. LDO1 Control Register (05h) This register is used to enable LDO1 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. LDO1V3 through LDO1V0 [D3:D0] These bits set the output voltage of LDO1 as shown in Table 6. Table 6 — LDO1 Control Codes LDO1V3 LDO1V2 LDO1V1 LDO1V0 V LDO1 0000O F F 0001 3.3V 0010 3.2V 0011 3.1V 0100 3.0V 0101 2.9V 0110 2.8V 0111 2.7V 1000 2.6V 1001 2.5V 1010 2.4V 1011 2.2V 1100 1.8V 1101 1.7V 1110 1.6V 1111 1.5V

Register Map (continued) LDO2 Control Register (06h) This register is used to enable LDO2 and set its output voltage level. Bits [D5:D3] These bits are unused and are always zeroes. LDO2V2 through LDO2V0 [D2:D0] These bits are used to set the output voltage of LDO2 in accordance with Table 7. Table 7 — LDO2 Control Codes LDO2V2 LDO2V1 LDO2V0 V LDO2 0 0 0 OFF 0 0 1 1.8V 0 1 0 1.7V 0 1 1 1.6V 1 0 0 1.5V 1 0 1 1.4V 1 1 0 1.3V 1 1 1 1.2V LDO3 Control Register (07h) This register is used to enable LDO3 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. LDO3V3 through LDO3V0 [D3:D0] These bits are used to set the output voltage of LDO3 as shown in Table 8. Table 8 — LDO3 Control Codes LDO3V3 LDO3V2 LDO3V1 LDO3V0 V LDO3 0000O F F 0001 3.3V 0010 3.2V 0011 3.1V 0100 3.0V 0101 2.9V 0110 2.8V 0111 2.7V 1000 2.6V 1001 2.5V 1010 2.4V 1011 2.2v 1100 1.8V 1101 1.7V 1110 1.6V 1111 1.5V

Register Map (continued) LDO4 Control Register (08h) This register is used to enable LDO4 and set its output voltage level. The ENL4 pin must be high for register 08h to control LDO4. ENL4 has a logical AND function with the register contents. Therefore, if ENL4 is low, V LDO4 =0V regardless of the contents of register 08h. Bits [D5:D4] These bits are unused and are always zeroes. LDO4V3 through LDO4V0 [D3:D0] These bits are used to set the output voltage of LDO4 as shown in Table 9. Table 9 — LDO4 Control Codes LDO4V3 LDO4V2 LDO4V1 LDO4V0 V LDO4 0000O F F 0001 3.3V 0010 3.2V 0011 3.1V 0100 3.0V 0101 2.9V 0110 2.8V 0111 2.7V 1000 2.6V 1001 2.5V 1010 2.4V 1011 2.2V 1100 1.8V 1101 1.7V 1110 1.6V 1111 1.5V Fade Control Register (09h) This register contains the fade enables and rate controls for both the main display and sub display LED driver banks. MFADE1 and MFADE0 [D2:D1] These bits are used to set the rise/fall rate between two backlight currents for the main display as show in Table 10. For the fade feature to be active, the MFADE bit must be set. The number of steps required to change the back- light current will be equal to the change in binary count of bits MBL4 through MBL0. Table 10 — Main Display Fade Control Bits MFADE1 MFADE0 Fade Feature Rise/ Fall Rate (ms/step) 00 3 2 01 2 4 10 1 6 11 8 MFADE [D0] This bit is used to enable or disable the fade feature. When MFADE is enabled and a new main backlight current is set, this current will change from its existing value to the new value written in MBL[4:0] at the rate determined by MFADE1 and MFADE0 (in ms/step). A new setting cannot be written during an ongoing fade opera- tion, but an on-going fade operation may be cancelled by writing 0 to the MFADE bit. Clearing the MFADE bit during an ongoing fade operation changes the current immedi- ately to the value of MBL[4:0]. The number of counts to complete a fade operation equals the diff erence between the old and new MBL[4:0] settings. If MFADE is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically by writing new values to the MFADE1 and MFADE0 bits. The total fade time is given by the number of steps between old and new backlight values (see Table 4), mul- tiplied by the rate of fade in ms/step.

SFADE1 and SFADE0 [D5:D4] These bits are used to set the rise/fall rate between two backlight currents for the sub display as show in Table 11. For the fade feature to be active, the SFADE bit must be set. The number of steps required to change the backlight current will be equal to the change in binary count of bits SBL4 through SBL0. Table 11 — Sub Display Fade Control Bits SFADE1 SFADE0 Fade Feature Rise/ Fall Rate (ms/step) 00 3 2 01 2 4 10 1 6 11 8 SFADE [D3] This bit is used to enable or disable the fade feature. When SFADE is enabled and a new main backlight current is set, the current will change from its existing setting to the new setting written in SBL[4:0] at the rate determined by SFADE1 and SFADE0 (in ms/step). A new setting cannot be written during an ongoing fade operation, but an on- going fade operation may be cancelled by writing 0 to the SFADE bit. Clearing the SFADE bit during an ongoing fade operation changes the current immediately to the value of SBL[4:0]. The number of counts to complete a fade operation equals the diff erence between the old and new SBL[4:0] settings. If SFADE is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically by writing new values to the SFADE1 and SFADE0 bits. The total fade time is given by the number of steps between old and new back- light values (see Table 5), multiplied by the rate of fade in ms/step. Register Map (continued) Bank Selection Register (0Ah) This register contains the bits that determine which LED drivers are assigned to the main display and which are part of the sub display bank. Bits [D5:D3] These bits are unused and are always zeroes. MB2, MB1, and MB0 [D2:D0] These bits are used to set the number of LED drivers dedi- cated to a main backlight function. This allows the device to drive two diff erent sets of LEDs with diff erent settings for use in products like clamshell-style mobile phones that have a main display and a sub display with diff erent light- ing requirements. Note that any driver not selected for the main display will automatically be assigned to the sub display set. The code set by these three bits determines which LED drivers are dedicated to the main display according to the assignments listed in Table 12. Table 12 — Main Display Driver Assignment Codes MB2 MB1 MB0 Main Display LED Drivers Sub Display LED Drivers 0 0 1 BL1 - BL5 none 0 1 0 BL1 - BL4 BL5 0 1 1 BL1 - BL3 BL4 - BL5 1 0 0 BL1 - BL2 BL3 - BL5 1 0 1 BL1 BL2 - BL5 000 and 110 through 111 BL1 - BL5 (default) none

e N PIN 1 INDICATOR (LASER MARK) A C SEATING PLANE E/2 D/2 LxN bxN DAP IS 1.90 x 1.90mm.3. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. E BD NOTES: bbb C A B aaa C A INCHES DIMENSIONS NOM e bbb aaa DIM N L E MIN D A MILLIMETERS MAXMINMAX NOM .003 .061 .067 .000 .020 (.006) 0.08 .071 1.55 .024 .002 0.00 0.50 1.801.70 0.05 0.60 (0.152) .004 0.10 1.55 2.90 1.70 1.80 3.00 3.10 0.40 BSC.016 BSC .122.118.114 .071.067.061 Outline Drawing — MLPQ-UT-20 3x3

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200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com Contact Information SC643 Land Pattern — MLPQ-UT-20 3x3 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. K H C Z P Y X G R H .146 .016 .008 .031 .083 .067 .004 3.70 0.20 0.80 0.40 1.70 0.10 2.10 DIM (2.90) MILLIMETERS DIMENSIONS (.114) INCHES K .067 1.70 THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FUNCTIONAL PERFORMANCE OF THE DEVICE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR R (C) X P Y G Z