SC531EVB

SC531 SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Dual 2A Source, 4A Sink FET Drivers Second Channel Enable Independent Drive Supplies Auxiliary 2A Source, 4A Sink FET Driver Precision Reference Output Current Limit Reference Output (Analog) Integrated Current Sense Blanking (Digital Input) Digitally Controlled High Precision Current Limit Current Limit Flag Current Input ZVS Comparator SPI Communications — 25 MHz Thermally Enhanced 4x4 (mm) MLPQ-UT-28 Package Lead-free, Halogen free, and RoHS/WEEE compliant

Applications

Digitally Controlled Power Supplies Flyback Converter Boost Converter Forward Converter DC-DC and AC-DC Converters With Active Clamp PFC Converters With ZVT Constant Current Converter

Description

The SC53 combines three low side drivers with a high speed digitally programmable current limit and a zero voltage switching (ZVS) comparator. Two drivers are nor- mally used to operate the FETs for the power stage. They can operate separately to drive individual power FETs or can be combined to drive a single device. A third, auxil - iary, gate drive is controlled by an independent input and can be used to drive the FET for an active clamp or ZVT switching. All three drivers have an independent supply which allows each drive voltage to be optimized for high efficiency. In addition, the SC53 has an SPI interface, 8-bit DAC, and current limit comparator to provide a high-speed digitally programmable current limit. This circuitry can be used for cycle by cycle current limiting or current waveform shaping. A digital output current limit flag is available for monitoring by the host controller. The SC53 also has a current-input ZVS comparator that can be used to sense changes in high voltage nodes, such as the power FET drain and inductor node (LX) versus the power stage supply, (HV IN in the typical application circuit). Typical Application Circuit Rev 2.0 SC531 GND VCC CSENSE DAC VREFH VREF CSB BLANKB CLK VREFL OE2B IN3 ZVS IN DIN 47nF 8-bit DAC SPI Interface 1µF HVIN 3.3V 15pF 180pF*1kW 200W* VOP VON COUT 2.49W Q3Q2Q1 CLF PVDD3 PGND3 OUT3 1µF PVDD2 PGND2 OUT2 1µF PVDD1 PGND1 OUT1 1µF ZVSP ZVSN 1MW 1MW CIN *optional

Ordering Information

SC53ULTRT()(2) MLPQ-UT-28 4×4 SC53EVB Evaluation Board Notes: () Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. TOP VIEW MLPQ-UT-28; 4x4, 28 LEAD θJA = 32.5°C/W yyww = Date Code XXXXX = Semtech Lot Number XXXXX = Semtech Lot Number SC531 yyww XXXXX XXXXX CLK20 CSB21 DIN19 OE2B VREF GND18 VREFH17 CSENSE16 VREFL15 PGND1 PGND2 OUT2 PVDD2 OUT1 A0 1 ZVSP 2 ZVSN 3 VCC 4 ZVS 5 PGND3 6 OUT3 7 CLF DAC IN BLANKB IN3 PVDD3 PVDD1 T

Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: () Tested according to JEDEC standard JESD22-A4-B. (2) Calculated from package in still air, mounted to 3” x 4.5” , 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. Absolute Maximum Ratings NOTES: Voltages are all referenced to GND (Pin 8). Recommended Operating Conditions NOTES: PGND, PGND2, PGND3 must be tied to GND. Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W) . . . 32.5 Unless otherwise noted, TA = +25°C for Typ, -40ºC to +5°C for Min and Max, TJ(MAX) = 25ºC, PVDD = 6V to 2V, Vcc = 3.5V to 3.46V, bypass capaci- tor on PVDD, VCC = 2.2µF, VREF = VREFH = 0.µF Parameter Symbol Conditions Min Typ Max Units Supply Section Combined PVDD Quiescent Current IPVDDL Not switching, CSB=, IN = IN3 = OE2B = low .5 2.5 mA Combined PVDD Quiescent Current IPVDDH Not switching, CSB=, IN = IN3 = VCC, OE2B = low 2.2 3.5 mA VCC Quiescent Current IVCC Not switching, CSB= 0.8 .4 mA PVDD UVLO Enable Voltage PVENABLE PVDD rising: UVLO sensing on PVDD only 4.25 4.5 4.75 V PVDD UVLO Hysteresis PVHYS UVLO sensing on PVDD only 250 mV VCC UVLO Threshold VCCUVLO(TH) VCC rising 2.65 2.8 2.95 V VCC UVLO Hysteresis VCCUVLO(HYS) VCC falling 00 mV Digital Section Digital Input High VIH IN, DIN, CSB, CLK, A0, IN3, OE2B 2. V Digital Input Low VIL IN, DIN, CSB, CLK, A0, IN3, OE2B 0.8 V Digital Input High (BLANKB) VIH_BLNK 2. V Digital Input Low (BLANKB) VIL_BLNK 0.4 V

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units Digital Section (continued) Digital Output High VOH CLF, ZVS, ILOAD=7mA 2.64 V Digital Output Low VOL CLF, ZVS, ILOAD=-7mA 0.66 V BLANKB pull-up resistance RBLANKB internal pull-up to VCC 2. 3.3 4.5 kW SPI CLK Frequency fCLK 25 MHz SPI CLK High & Low Time tSPI 5 ns CSB, DIN to Clock Falling Edge Setup and Hold Time tSH 5 ns Chip Select Reset Time tCSB 0 ns DAC Section DAC Response Time tRESPONSE Settling to within LSB 0.5 ms DAC INL INL - LSB DAC DNL DNL -0.2 0.2 LSB Voltage Reference VREF VREF/VREFH, HiZ voltmeter 0.245 0.255 V/V Voltage Reference Buffer Offset VBOFFSET -5 5 mV Voltage Ref Divider Resistance RREF 384 640 896 kW Current Sense Comparator Section Current Sense Voltage Range VSENSE 0 .2 V Comparator Offset Voltage VCOFFSET -6 6 mV CSENSE to CLF Propagation Delay tCLF 25 40 ns CSENSE to Driver Output Propaga- tion Delay tDRIV nF load, 60mV overdrive, 0% to 90% of drive output 45 70 ns Driver Section Driver OUT, OUT2, OUT3 Resistance (Sourcing) RDSP,2,3 .5 3 W Driver OUT, OUT2, OUT3 Resistance (Sinking) RDSN,2,3 0.7 .5 W Rise Time — OUT, OUT2, OUT3 tRISE,2,3 PVDD=8V, load capacitance=nF 0 ns Fall Time — OUT, OUT2, OUT3 tFALL,2,3 PVDD=8V, load capacitance=nF 5 ns Propagation Delay from IN to OUT, OUT2 tPROP,2 PVDD=8V, load capacitance=nF 25 45 ns Electrical Characteristics (continued)

Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Driver Section (continued) Propagation Delay from IN3 to OUT3 tPROP3 No load 25 45 ns OUTX Minimum On-time PVDDX = 8V, COUT = nF 25 00 ns Driver ,2,3 Switching Frequency f,2,3 800 kHz ZVS Section ZVSP , ZVSN Offset Current IZVS 0mA < Input current < 40mA -3 0 3 μA ZVSP , ZVSN to GND Voltage VZVS 0mA < Input current < 40mA 5 V Response Time (ZVS falling) tZVS_falling 0mA<Input Current< 40mA, 5mA overdrive 25 40 ns Response Time (ZVS rising) tZVS_rising 0mA<Input Current< 40mA, 0mA overdrive 0.5 μs

Pin # Pin Name Signal Type Pin Function A0 Digital input Address for SPI interface

2 ZVSP Analog input ZVS comparator positive input

3 ZVSN Analog input ZVS comparator negative input

4 VCC Power input Input supply voltage. Connect a 2.2uF bypass capacitor from VCC to GND.

5 ZVS Digital output ZVS comparator output

6 PGND3 GROUND Driver 3 power ground.

7 OUT3 Power output Driver 3 output

8 PVDD3 Power input Driver 3 supply voltage. Connect a 2.2uF bypass capacitor from PVDD3 to PGND3.

9 IN3 Digital input Driver 3 signal input

0 IN Digital input Driver and 2 signal input

BLANKB Digital input Current limit blanking input

2 CLF Digital output Current limit flag

3 DAC Analog output DAC output

4 VREF Analog input/output Reference Voltage

5 VREFL Analog input Low reference for VREF resistor divider and DAC. Typically connected to GND.

6 CSENSE Analog input Current sense input

7 VREFH Analog input High reference for top of VREF resistor divider

8 GND GROUND IC Ground

9 DIN Digital input SPI data input

20 CLK Digital input SPI clock input

2 CSB Digital input SPI chip select input

22 OE2B Digital input Driver 2 enable

23 PGND2 GROUND Driver 2 power ground

24 OUT2 Power output Driver 2 output

25 PVDD2 Power input Driver 2 supply voltage. Connect a 2.2uF bypass capacitor from PVDD2 to PGND2. 26 PVDD Power input Driver supply voltage. Connect a 2.2uF bypass capacitor from PVDD to PGND2.

27 OUT Power output Driver output

28 PGND GROUND Driver power ground

T Thermal Pad GROUND Connected to GND, use multiple thermal vias for heatsinking purposes

Ref. Bufffer VREFH 17 SPI Interface DIN 19 VCC 4 CSB 21 CLK 20 A0 1 VREFL 15 CSENSE 16 BLANKB 11 ZVS 5 IN3 9 8-bit DAC OUT37 PGND36 PVDD38 PGND128 OUT127 PVDD126 PGND2

22 OE2B

R R S Q DAC 13 VCC 3.33kW

OUT1, OUT2 Rise Time IN (2V/div) VCC = 3.3V, PVDD/2/3 = 7.8V, Load = BSC90N5NS3G Time (40ns/div) OUT2 (5V/div) OE2B (V/div) OUT1, OUT2 Fall Time VCC = 3.3V, PVDD/2/3 = 7.8V, Load = BSC90N5NS3G Time (40ns/div) OUT3 Rise Time VCC = 3.3V, PVDD/2/3 = 7.8V, Load = BSC90N5NS3G Time (40ns/div) OUT3 Fall Time VCC = 3.3V, PVDD/2/3 = 7.8V, Load = BSC90N5NS3G Time (40ns/div) SPI to DAC Response Time VCC = 3.3V, PVDD/2/3 = 7.8V Time (4µs/div) CLK (5V/div) LX (50V/div) OUT1 Current Limit With CLF Flag IN (2V/div) VCC = 3.3V, PVDD/2/3 = 7.8V, Emulated CSENSE input Time (1µs/div) OUT (5V/div) OUT (5V/div) CLF (2V/div) CSENSE (500mV/div) DAC (00mV/div) IN (2V/div) OUT3 (5V/div) IN (2V/div) OUT3 (5V/div) IN (2V/div) OUT2 (5V/div) OE2B (V/div) OUT (5V/div)

up resistance of 3.3 kΩ to VCC. If the BLANKB pin is not held low, then the output of the current limit comparator will be determined by the CSENSE and DAC voltages. If the DAC voltage is greater than CSENSE then the output of the comparator will be low. If the CSENSE voltage is greater than the DAC voltage then the output of the com- parator will go high causing the CLF flag to go high and OUT and OUT2 to be driven low. This event is latched and will not be released until CSENSE goes below DAC and the IN pin goes from low to high. SPI Interface A write sequence begins by bringing CSB low. Once CSB is low, the data on the DIN line is clocked into the 6-bit shift register on the falling edges of CLK. On the 6th falling clock edge, the last data bit is clocked in and the DAC is updated. CSB can be held low or high at this point and any data or clock pulses following the 6th falling clock edge are ignored. CSB must be brought high for the minimum specified time before the next write sequence is initiated with the falling edge of CSB. Figure 3 shows the Serial Timing Diagram and Figure 4 shows the Input Register Contents. ZVS Comparator The ZVS comparator is a current-input (Norton) compara- tor that provides information that the ZVS condition has been reached by comparing the LX node to HV IN. The falling edge of the power FET LX node going below HV IN (ZVS output going low) is the faster edge. The structure of the comparator allows fast detection with a large voltage range. Series resistors are placed from LX to ZVSP and HVIN to ZVSN. The resistor value should be chosen based on the voltage levels that are being compared and should be optimized to produce input currents in the 0-40μA range. The ZVSP and ZVSN pins can vary from 2-4V based on this normal input current range. The ZVSN and ZSVP input pins can tolerate currents up to 300μA, but the accuracy and speed specifications are only valid in the 0-40μA range. Gate Drivers 1 and 2 The high-current output stage in the SC53 is capable of providing 2A source, 4A sink peak current and voltage swings from PVDD to PGND for both OUT and OUT2. These outputs can drive individual power FETs which can be used in parallel or can be combined to drive one larger device. The second output (OUT2) can be disabled to save power by setting OE2B input to a logic high. If OE2B is set high during normal switching operation, the OUT2 output is not disabled until the next falling edge of IN. The driver outputs follow the state of the IN pin. When IN is high OUT and OUT2 (if OE2B is low) are high. The outputs will be pulled low when IN goes low or when the current limit is reached. Reference Divider, Buffer, DAC, and Current Limit Comparator The SC53 contains a reference divider, buffer, DAC, and current limit comparator that combine to provide a high- speed and high-accuracy programmable current limit. The reference voltage is generated by a resistive divide by four from VREFH to VREFL. This voltage is referenced at the VREF pin. Alternatively, an external reference can drive the VREF pin if a different value is desired. The equation for the VREF voltage is shown below. 95()/95()+95() ˜ The VREFL input must be within +/-300mV of the GND pin and is typically connected to analog ground. The VREF voltage is buffered and then used as the refer - ence for the 8-bit DAC. The 8-bit DAC is controlled by the SPI (see next section for protocol information). The output of the DAC connects to the DAC pin and to the negative input of the current limit comparator. The positive input of the current limit comparator is con - nected to the CSENSE pin through blanking circuitry. When the BLANKB pin is held low the CSENSE pin is dis - connected from the comparator and the positive input is shorted to ground. The BLANKB pin has an internal pull-

Applications Information (continued) Gate Driver 3 Gate Driver 3 is a third auxiliary gate drive that is controlled by the IN3 pin, an independent input. It has a separate power supply (PVDD3) and ground (PGND3) connection. The output OUT3 is 2A source, 4A sink capable. This output can be used as a general purpose driver which can be used to drive the FET for an active clamp or active snubber. Other uses include driving the FET for soft- switching ZVT or to drive a secondary PWM output. The SC53 is suited for applications which contain a micro- controller or DSP to control PWM switching. The auxiliary OUT3 output and the DAC controlled current limit can be used to implement a variety of switching topologies. By driving the IN3 input with a signal that is inverted from the IN input, the OUT3 driver can be used to drive an external P-channel FET for an active clamp converter. In addition, the DAC can be programmed to vary in real-time as a function of the main error voltage from the system microcontroller. This causes each OUT/2 pulse to termi nate when the peak current reaches the real-time DAC setting, resulting in current-mode operation. Combining the DAC control with the external P-channel FET circuitry results in an Active Clamp Current Mode Converter. Refer to Figure . The above converter can also be used to provide a pro - grammable constant current output by setting the DAC to a constant value. The IN input has a longer duty cycle than is required to maintain the output, but each OUT/2 pulse is terminated early by the current limit function. The average current to the load will equal the peak inductor current reduced by 50% of the inductor ripple current. The OUT3 output can be used to drive the FET for a ZVT switch such as is used in PFC boost converters. The ZVS comparator can be used to detect when the ZVT FET has completed its discharge of the main FET by connecting two additional resistors to the ZVS inputs, RZ and RZ2, and resistors RZ3 and RZ4 should be selected to keep the keep the ZVSP/N input current below 300uA at maximum VIN. Refer to Figure 2. PCB Layout Guidelines Any switch-mode converter requires a good PCB layout to achieve best performance. The following guidelines should be followed to produce an optimum PCB layout. All bypass capacitors should be located close to the pins which they connect to. Use short, direct copper traces to connect between the capacitor and the IC pins. Bypass capacitors should be placed on the same side of the PCB as the IC. Use a 2.2μF minimum capacitor for all bypassing. The pins which require bypass capacitors are shown below: VCC, GND PVDD, PGND PVDD2, PGND2 PVDD3, PGND3 The connections between the PGND pins and the power FETs should be short and direct, using a ground plane if available. If vias are required use multiple vias to reduce impedance between the IC and the FETs. The gate traces should be short and direct. Use wide, short gate traces to reduce susceptibility to noise generated by nearby FET switching. The gate trace routings should avoid any of the FET drain nodes. The CSENSE signal should be referenced to GND (analog ground). A capacitor on the CSENSE input should be located near the CSENSE pin and connected to GND, and connected to the IC with short direct traces. Any VREFH, VREFL, or VREF bypass capacitors should be placed close to the pins, routed with direct traces, and connected to GND.

Outline Drawing – 4x4 MLPQ-UT28 INDICATOR (LASER MARK) PIN 1 DIMENSIONS NOM INCHES N bbb aaa DIM L e E D A b MIN MAX MILLIMETERS MINMAX NOM .003 .006 .100 .008 .104 .000 .020 (.006) 0.08 0.20 .010 .108 0.15 2.55 .024 .001 0.00 0.50 2.75 0.25 2.65 0.02 0.60 (0.152) .004 0.10 2.55 2.65 2.75 0.40 BSC.016 BSC .108.104.100 SEATING PLANE N CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. NOTES: D E A B A aaa C C LxN E/2 e bbb C A BD/2 bxN 3. CENTER PAD IS CONNECTED TO PIN 18(GROUND).

Land Pattern – 4x4 MLPQ-UT28 C Z P Y X G K H .189 .016 .008 .033 .122 .104 .104 4.80 0.20 0.85 0.40 2.65 2.65 3.10 DIM (3.95) MILLIMETERS DIMENSIONS (.156) INCHES FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FUNCTIONAL PERFORMANCE OF THE DEVICE. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. 4. Y ZG P X K H(C) THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES:

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Phone: (805) 498-2 Fax: (805) 498-3804 www.semtech.com Contact Information SC531 © Semtech Corporation All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse - quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.