SC508

SC508 SEMTECH | Alldatasheet

Document overview

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• PDF pages: 32

Technical content

Features

Input voltage — 4.5V to 46V Integrated bootstrap switch Fixed 5V LDO output — 200mA 1% reference tolerance -40 to +85 °C Selectable internal/external bias power supply EcoSpeed® architecture with pseudo-fixed fre- quency adaptive on-time control Logic input and output control Independent control EN for LDO and switcher Programmable soft-start time Programmable VIN UVLO threshold Power Good output Selectable power-save mode Programmable ultrasonic power-save mode Protections Automatic restart on fault shutdown Over-voltage and under-voltage TC compensated RDS(ON) sensed current limit Thermal shutdown Smart power-save Pre-bias start-up Capacitor types: SP , POSCAP , OSCON, and ceramic Package — 3 x 3(mm), 20-pin MLPQ Lead-free and halogen-free RoHS and WEEE compliant AEC-Q100 Qualified available in SC508A

Applications

Office automation and computing Networking and telecommunication equipment Point-of-load power supplies and module replacement Automotive applications

Description

The SC508/SC508A is a synchronous EcoSpeed® buck reg- ulator which incorporates Semtech’s advanced, patented adaptive \`on-time control architecture to provide excel - lent light-load efficiency and fast transient response. It features an integrated bootstrap switch and a fixed 5V LDO in a 3 x 3(mm) package. The device is highly efficient and uses minimal PCB area. The SC508A is available for automotive applications and is qualified to AEC-Q100. The SC508 supports using standard capacitor types such as electrolytic or special polymer, in addition to ceramic, at switch- ing frequencies up to 1MHz. The programmable frequency, synchronous operation, and programmable power-save provide high efficiency operation over a wide load range. Additional features include cycle-by-cycle current limit, programmable soft-start, under and over-voltage protec- tion, programmable over-current protection, start-up into pre-biased output, automatic fault recovery (hiccup restart), soft-shutdown, selectable power-save modes, and pro - grammable ultrasonic power-save. The device also provides separate enable inputs for the PWM controller and LDO as well as a power good output for the PWM controller. Output voltage range is 0.6 to 5V, with output voltages greater than 5V supported using additional components. The input voltage can range from 5V to 46V. The wide input voltage range, programmable frequency, and inte - grated 5V LDO make the device extremely flexible and easy to use in a broad range of applications. Support is provided for multi-cell battery systems in addition to tra - ditional DC power supply applications. Revision 4.1 POWER MANAGEMENT Typical Application Circuit VDDA PGOOD EN TON ENL 1µF VEXT or VLDO PGNDAGND VLDO ENABLE LDO RTON SC508 SC508A VDDP VLDO SS 0.1µF 1µF ENABLE PGOOD PSV PSV LX ILIM RLIM VOUT COUT VOUT FB CIN DH BST DL VINVIN VEXT or VLDO 10nF 3.3O

Pin Configuration Ordering Information Marking Information 508 yyww xxxx AGND PAD FB VLDO VOUT VDDA 6 7 8 9 10 DH PGND PSV DL VDDP PGOOD15 1617181920 VIN LX BST NC SS ILIM TON ENL EN AGND Top View Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. 3) AEC-Q100 Qualified. yyww = Date Code xxxx = Semtech Lot Number MLPQ-UT20 Device Package SC508ULTRT(1)(2) MLPQ-UT20 SC508AULTRT(1)(2)(3) MLPQ-UT20 SC508EVB Evaluation Board SC508AEVB Evaluation Board 508A yyww xxxx yyww = Date Code xxxx = Semtech Lot Number

Absolute Maximum Ratings(1) Recommended Operating Conditions Supports output voltages greater than 5.5V using external components Thermal Information Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) VOUT pin must not exceed (VDDA pin + 0.3V). (3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Unless specified: VIN =12V, VDDA = VDDP = 5V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, Typical Application Circuit

Electrical Characteristics

Parameter Conditions Min Typ Max Units Input Supplies Input Supply Voltage (VIN) VDDA = 5V 4.5 46 V VIN UVLO Threshold(1) Sensed at ENL pin, rising edge 1.50 1.56 1.70 V Sensed at ENL pin, falling edge 1.45 1.52 1.65 VIN UVLO Hysteresis Sensed at ENL pin; EN = 5V 0.04 V VDDA UVLO Threshold Measured at VDDA pin, rising edge 3.7 3.9 4.1 V Measured at VDDA pin, falling edge 3.5 3.7 3.9 VDDA UVLO Hysteresis 0.2 V VIN Supply Current Shutdown mode; ENL, EN = 0V, VIN = 46V 20 35 μA Standby mode; VDDA, VDDP , ENL = 5V, EN = 0V 130

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) VDDA + VDDP Supply Current(2) ENL , EN = 0V 3 7 μA Power-save operation EN = 5V, PSV = open (float), VFB > 600mV 0.4 mA Ultrasonic Power-save operation EN = 5V, RPSV = 115kΩ, VFB > 600mV 2.4 Forced Continuous Mode operation Operating fSW = 220kHz, PSV = VDDA, no load 13 FB Comparator Threshold Static VIN and load, 0 to +85 °C 0.5952 0.600 0.6048 V Static VIN and load, -40 to +85 °C 0.594 0.606 V Frequency Range Continuous mode operation 1000 kHz Timing On-Time Forced Continuous Mode operation VIN = 30V, VOUT = 3 V, RTON = 600kΩ, VDDA = 5V 1530 1700 1870 ns On-time Accuracy; Forced Continuous Mode VIN = 4.5 to 10V, VOUT = 3 V, RTON = 600kΩ, VDDA = 5V ±15 % Minimum On-Time 80 ns Minimum Off-Time 250 ns Ultrasonic Frequency Minimum switching frequency, RPSV = 115kΩ 25 kHz Soft-Start Soft-Start Charge Current 3.0 μA Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero Cross Detector Threshold LX with respect to PGND -3 0 +3 mV Power Good Power Good Threshold Upper limit, VFB > internal 600mV reference +20 Lower limit, VFB < internal 600mV reference -10 Startup Delay Time EN rising edge to PGOOD rising edge, CSS = 10nF 11 ms Fault (noise immunity) Delay Time 5 µs Leakage PGOOD = high impedance (open) 1 µA Power Good On-Resistance PGOOD = pulled low to AGND 10 Ω

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Fault Protection ILIM Source Current 9 10 11 μA ILIM Source Current Temperature Coefficient 0.41 %/°C ILIM Comparator Offset With respect to AGND -8 0 +8 mV Output Under-Voltage Threshold VFB with respect to internal 600mV reference, 8 consecutive cycles -25 % Smart Power-Save Protection Threshold VFB with respect to internal 600mV reference +10 % Over-Voltage Protection Threshold VFB with respect to internal 600mV reference +20 % Over-Voltage Fault Delay 5 μs Over-Temperature Shutdown 10°C hysteresis 165 °C Logic Inputs/Outputs Logic Input High Voltage — EN 1.4 V Logic Input High Voltage — PSV Forced Continuous Mode operation; PSV pin with respect to VDDA -0.4 V Logic Input Low Voltage — EN, ENL(3) With respect to AGND 0.4 V EN Input Bias Current EN = VDDA or AGND -10 +10 μA ENL Input Bias Current VIN = 46V +11 μA FB Input Bias Current FB = VDDA or AGND -1 +1 μA PSV Input Bias Current PSV = VDDA 5 16 μA PSV < 1.5V 1 μA Linear Regulator VLDO Accuracy VLDO load = 10mA 4.875 5.0 5.125 V Current Limit VLDO < 1V start-up 13 mA1V < VLDO < 4.5V (typ) 90 Operating, VLDO > 4.5V (typ) 200 VLDO to VOUT Switch-over Threshold (4) -130 +130 mV VLDO to VOUT Non-switch-over Threshold (4) -500 +500 mV VLDO to VOUT Switch-over Resistance VLDO = VOUT = 5V 2.0 Ω VLDO Drop Out Voltage VIN to VLDO, LDO load = 50mA 1.2 V

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units High-Side Driver (DH, BST, LX) Peak Current VDDP = 5V, DH pin sourcing or sinking 2 A On Resistance RDH_PULL-UP , LX < 0.5V, VDDP = 5V 3.0 6.0 Ω RDH_PULL-UP , LX > 0.5V, VDDP = 5V 1.0 2.0 Ω RDH_PULL-DOWN, VDDP = 5V 0.6 1.2 Ω Rise Time CDH-LX = 3nF, VDDP = 5V 22 ns Fall Time CDH-LX = 3nF, VDDP = 5V 12 ns Propagation Delay From FB Input to DH 45 ns Shoot-thru Protection Delay 45 ns Bootstrap Switch Resistance 16 Ω Low-Side Driver (DL, VDDP , PGND) Peak Current VDDP = 5V, DL sourcing 2 A VDDP = 5V, DL sinking 4 On Resistance RDL_PULL-UP , VDDP = 5V 1.0 2.1 Ω RDL_PULL-DOWN, VDDP = 5V 0.50 0.86 Ω Rise Time CDL = 3nF, VDDP = 5V 7 ns Fall Time CDL = 3nF, VDDP = 5V 3.5 ns Notes: (1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. (2) For UPSV and FCM operation, the VDDA and VDDA supply current includes the DH/DL current required to drive the external MOSFETS. (3) The ENL pin will enable the LDO with 0.8V typical. The ENL pin VIN ULVO function will disable the switcher unless the ENL pin exceeds the VIN UVLO Threshold which is typically 1.56V. (4) The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT.

Typical Characteristics (continued) Efficiency vs Load — PSAVE Mode 15V 28V 42V 100 0 1 2 3 4 5 6 7 8 Efficiency (%) IOUT (ADC) Efficiency vs Load — Forced Continuous Mode 15V 28V 100 0 1 2 3 4 5 6 7 8 Efficiency (%) IOUT (ADC) 42V Efficiency vs Load — Ultrasonic PSAVE Mode 15V 28V 100 0 1 2 3 4 5 6 7 8 Efficiency (%) IOUT (ADC) 42V Efficiency vs Load — 5V output 15V 28V 100 Efficiency (%) IOUT (ADC) 42V 0 1 2 3 4 5 6 Inductor: Cyntec PCMB104E-4R7MS High side MOSFET: Alpha Omega AO4440 Low side MOSFET: Fairchild FMDS5352 Efficiency vs Load — 12V output 28V 100 Efficiency (%) IOUT (ADC) 42V 0 1 2 3 4 5 6 Inductor: Cyntec PCMB104E-4R7MS Low side MOSFET: Fairchild FMDS5352 High side MOSFET: Fairchild FMDS5352 Load Regulation 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 0 1 2 3 4 5 6 7 8 IOUT (ADC) VOUT (V)

15 VIN

42 VIN

28 VIN

VOUT 5V, Internal 5V bias, Power-save, 250kHz Frequency VOUT 12V, External 5V bias, Power-save, 400kHz Frequency VOUT 1.8V, External 5V bias, 220kHz Frequency VOUT 1.8V, External 5V bias, 220kHz Frequency VOUT 1.8V, External 5V bias, 220kHz Frequency VOUT 1.8V, External 5V bias, 220kHz Frequency

Typical Characteristics (continued) Start-up — EN Input EN (5V/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE Time (1miii PGOOD (5V/div) LX (50V/div) Pre-Bias Start- up — EN Input EN (5V/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE Time (1miii VOUT (1V/div) PGOOD (5V/div) Start-up — SS ramp-up SS (5V/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE, startup using EN input Time (1miii Shutdown — EN Input ENL (5V/div) VIN = 5V, VOUT = 1.8V, IOUT = 1A, PSAVE Time (1miii PGOOD (5V/div) LX (50V/div) VOUT (1V/div) Over-current — Automatic Restart VIN = 42V, VOUT = 1.8V, External load = 15A Time (20miii IOUT (10A/div) LX (50V/div) Start-up, Shutdown — ENL Input (VIN UVLO) ENL (5V/div) VIN = 42V, VOUT = 1.8V, IOUT = 1A, PSAVE Time (4miii VOUT (1V/div) VOUT (1V/div) VOUT (1V/div) PGOOD (5V/div) LX (50V/div) PGOOD (5V/div) LX (50V/div) LX (50V/div) VOUT (1V/div) SS (5V/div)

Typical Characteristics (continued) Switching — PSAVE VOUT (50mV/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A Time (10miii DL (5V/div) LX (50V/div) Transient Response — PSAVE VOUT (50mV/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A Time (100µiii LX (50V/div) Switching — UPSAVE VOUT (50mV/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A Time (20μii DL (5V/div) Transient Response — UPSAVE VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A Time (100μii LX (50V/div) IOUT (5A/div) VOUT (50mV/div) Transient Response — FCM VOUT (50mV/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A Time (100μii IOUT (5A/div) LX (50V/div) Switching — FCM VOUT (50mV/div) VIN = 42V, VOUT = 1.8V, IOUT = 0A Time (4μii LX (50V/div) DL (5V/div) LX (50V/div) IOUT (5AV/div)

RPSV(2)100nF SC508 TON VLDO VOUT DL VDDA PGOOD ENL BST PSV EN VDDP AGND FB DH N/C VIN LX SS ILIM PGND EN PGOOD ENABLE LDO VIN VIN RTOP RBOT 1µF VOUT RTON 1µFVLDO 3(1) 5 11 6 7 8 9 10 20 19 18 17 16 COUT + 1µF 154kW 36V to 1.8V @ 8A CTOP* PAD 20kW 10kW np CIN1 CIN2 100nF Component Value Manufacturer Part Number Web CIN1, CIN2 10µF/50V Murata GRM32ER71H106KA12L www.murata.com www.panasonic.comCOUT 330µF/6mW Sanyo 2TPF330M6 www.vishay.comL1 1.8µH Vishay IHLP4040EZER1R8M01 Key Component www.aosmd.comQ1 AO4440 Alpha Omega AO4440 www.fairchildsemi.comQ2 FDMS5352 Fairchild FDMS5352 6.81kW CSS 3.9nF CBST (1) (2) RPSV: Use 115kW for Ultrasonic operation. Remove RPSV for Power-Save operation. Connect PSV pin to VDDA for Forced Continuous Mode operation. (1) 5V: Connect VDDA and VDDP to external 5V supply for external bias. Connect VDDA and VDDP to VLDO for self -biased operation. Notes: RBST 3.3W Detailed Application Circuit

Pin # Pin Name Pin Function 1 FB Feedback input for switching regulator — connect to an external resistor divider from output — used to pro- gram the output voltage.

2 VOUT

Switcher output voltage sense pin — also the input to the internal switch-over MOSFET between VOUT and VLDO. The voltage at this pin must not exceed the VDDA pin. For output voltages up to 5V connect this pin directly to the switcher output. For output voltages exceeding 5V connect this pin to the switcher output through a resistor divider. 3 VDDA Supply input for internal analog circuits — connect to external 5V supply or connect to VLDO — also the sense input for VDDA Under Voltage Lockout (VDDA UVLO). 4 VLDO Output of the 5V LDO — The voltage at this pin must not exceed the voltage at the VDDA pin. 5 VIN Input supply voltage — connect to the same supply used for the high-side MOSFET. Connect a 100nF capaci- tor from this pin to AGND to filter high frequency noise. 6 SS Soft-Start — connect tan external capacitor to AGND to program the soft start and automatic recovery time.

7 NC No Connection

8 BST Bootstrap pin — connect a 100nF minimum capacitor and series resistor from BST to LX to develop the float- ing voltage for the high-side gate drive. A 3.3 ohm resistor is recommended.

9 DH High-side gate drive output

10 LX Switching (phase) node

11 PGND Power ground for the DL and DH drivers and the low-side external MOSFET.

12 DL Low-side gate drive output

13 VDDP 5V supply input for the DH and DL gate drives — connect to the same 5V supply used for VDDA.

14 PSV

Power-save programming input — connect a resistor to AGND to set a minimum (ultrasonic) power-save fre- quency — float pin to select power-save with no minimum frequency — pull up to VDDA to disable power- save and select forced continuous mode. 15 PGOOD Open-drain Power Good indicator — high impedance indicates the switching regulator output is good. An external pull-up resistor is required. 16 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX. 17 EN Enable input for switching regulator — logic low disables the switching regulator — logic high enables the switching regulator.

18 AGND Analog ground

19 TON ON time programming input — set the on-time by connecting through a resistor to AGND.

20 ENL

Enable input for the LDO and VIN UVLO input for the switching regulator — connect ENL to AGND to disable the LDO — drive to logic high (>1.7V) to enable the LDO and inhibit V IN UVLO — connect to resistor divider from VIN to AGND to program the VIN UVLO threshold. PAD AGND Analog ground

Control & Status PGOOD Gate Drive Control VIN TON VOUT Zero Cross Detector Current Limit ILIM ENL VLDO Switchover MUX A Y B 5V LDO VLDO BST FB Comparator VDDA LX EN VLDO Switchover Comparator DL 3 15 17 A VDDP VDDP VIN VDDA PSV PGND11 DL12 DH9 VDDP Bootstrap Switch Reference VIN ULVO detect A = connected to pins 18 and PAD DL VIN To Control & Status VIN ULVO VDDA SS 6

If the internal LDO is used for bias power, the LDO switch- over function must be inhibited by selecting the resistor divider so that the voltage at the VOUT pin does not exceed 4V; this will inhibit the VLDO switch-over func - tion. If the SC508 bias power is from an external 5V supply and the LDO is disabled by grounding the ENL pin, the voltage at the VOUT pin is not limited to 4V and can be as high as the VDDA supply voltage. Note that the VOUT pin has an internal 500k W resistor connected to AGND. To minimize the effect of this resistor on the resistor divider ratio, the maximum recommend value for resistor RV2 in Figure 4 is 10kW. In addition to the resistor divider, the RTON resistor value must be adjusted. The on-time is calculated according to the voltage at the VOUT pin. In order to select the desired on-time and operating frequency, the RTON resistor should be adjusted to a higher value to compensate for the reduced voltage at the VOUT pin. For output voltages exceeding 5V, the required RTON value can be determined by the following equation. § uu u¸¸ § u 287 6:,1 287 721 9S) 9QVI9 For applications where VOUT exceeds 5V, FCM operation is recommended. Forced Continuous Mode Operation The SC508 operates the switcher in Forced Continuous Mode (FCM) by connecting the PSV pin to VDDA. The PSV pin should never exceed the VDDA supply. See Figure 5 for FCM waveforms. In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid cross-conduction. This results in more uniform frequency across the full load range with the trade-off being reduced efficiency at light loads due to the high-frequency switching of the MOSFETs. The PSV pin contains a 5μA current sink to prevent stray leakage current from pulling the PSV pin up to the VDDA supply when the PSV pin is floated to select Power-Save operation. To select Forced Continuous Mode operation, the maximum recommended resistance between the VDDA supply and the PSV pin is 40kW. FB Ripple Voltage (VFB) FB threshold DL DH Inductor Current DC Load Current DH on-time is triggered when VFB reaches the FB Threshold. On-time (TON) DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. Figure 5 — Forced Continuous Mode Operation Programmable Ultrasonic Power-Save Operation The device provides programmable ultrasonic power-save operation at light loads; the minimum operating fre - quency is programmed by connecting a resistor from PSV to AGND. The SC508 uses the PSV resistor to set an inter- nal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds the programmed timer, DL drives high to turn the low-side MOSFET on. This draws current from VOUT through the inductor, forcing both VOUT and VFB to fall. When VFB drops to the 600mV thresh - old, the next DH on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on, and the internal timer is restarted. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. This ends the cycle until VFB again falls below the 600mV threshold, or the internal timer forces another DL turn-on. Applications Information (continued)

SC508 can support soft-start with an output pre-bias. The SS ramp time is the same as a normal start-up when the output voltage starts from zero. Under a pre-bias start-up, the DH and DL drivers inhibit switching until 40% of the ramp at the SS pin equals the pre-bias FB voltage level. Pre-bias start-up is achieved by turning off the lower MOSFET when the inductor current reaches zero during the soft-start cycle. This method prevents the output voltage from decreasing. Power Good Output The PGOOD (power good) output is an open-drain output which requires a pull-up resistor. During start-up, PGOOD is held low and is not allowed to transition high until the output voltage is in regulation and the SS pin has reached 67% of VDDA. The time from EN going high to PGOOD going high is typically 11ms for CSS = 10nF. When the voltage at the FB pin is 10% below the nominal voltage, PGOOD is pulled low. Once PGOOD pulls low there is typically 2% hysteresis to prevent chatter on the PGOOD output. PGOOD will transition low if the FB voltage exceeds +20% of nominal (720mV), which is also the over-voltage shut - down threshold. PGOOD also pulls low if the EN pin is low and VDDA is present. Output Over-Voltage Protection Over-voltage protection (OVP) becomes active as soon as the device is enabled. The OVP threshold is set at 600mV + 20% (720mV). There is a 5μs delay built into the OVP detector to prevent false transitions. When VFB exceeds the OVP threshold, DL is driven high and the low-side MOSFET is turned on. DL remains high and the controller remains off while the device goes through the automatic fault recovery cycle. When the automatic recovery cycle is completed, the device will attempt a new soft-start cycle. At the start of the soft-start cycle, the DL output will go low for typically 30usec while the controller initializes the soft-start sequence. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls 25% below its nominal voltage (falls to 450mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tri- state the MOSFETs. The controller stays off while the device goes through the automatic fault recovery cycle. Automatic Fault Recovery The SC508 includes an automatic recovery feature (hiccup mode upon fault). If the switcher output is shut down due to a fault condition, the device uses the SS capacitor as a timer. Upon fault detection the SS pin is pulled low and then begins charging through the internal 3 μA current source. When the SS capacitor reaches 67% of VDDA, the SS pin is again pulled low, after which the SS capacitor begins another charging cycle. The SS capacitor will be used for 15 cycles of charging from 0 to 67% of VDDA. During these cycles the switcher is off and there is no MOSFET switching. During the 16th SS charging cycle, the normal soft-start routine is implemented and the MOSFETs begin switch - ing. Switching continues until the Power Good Start-up Delay Time is reached. If the switcher output is still in a fault condition, the switcher will again shut down and force 15 cycles of SS charging before attempting another soft-start. The long delay between soft-start cycles reduces the average power loss in the power components. The automatic recovery timing is shown in Figure 12. 15 cycles SS tHICCUP = 15 x tEN_PGOOD tEN_PGOOD 67% x VDDA 1 soft-start cycle fault applied 15 cycles 1 soft-start cycle tEN_PGOOD tEN_PGOOD tHICCUP = 15 x tEN_PGOOD Figure 12 — Automatic Recovery Timing If the fault was due to an over-voltage condition, the DL output will remain high during the 15 SS charging cycles. For all other faults, the DL output will remain low. In all cases, during the 16th SS charging cycle, DL will drive low for typically 30usec as the controller initializes a soft-start cycle. Applications Information (continued)

Applications Information (continued) the ENL pin low (to AGND) will turn off the LDO and the LDO switch-over MOSFET, but the switcher will continue operating. V OUT will feed into the LDO output and the VDDA/VDDP supplies through the internal parasitic diode. This can potentially damage the device, and also prevents the switcher from shutting off until the VDDA supply drops below the VDDA UVLO threshold. For these applications a dedicated logic signal is required to drive EN low and disable the switcher. This signal can be combined with the ENL signal if needed, as long as the EN pin does not exceed Absolute Maximum Ratings. LDO Usage at Low Input Voltage Applications requiring steady-state or transient operation at low input voltages (VIN below 6.5V) may use the internal LDO to bias the VDDA/VDDP pins within limitations. There are limitations to both startup and normal operation as explained below. When starting up using the internal LDO, switcher opera- tion is inhibited until the LDO output reaches 4.5V. During this time, the LDO start-up is implemented using a current source. At low VIN it is important to not apply an external load to the LDO, in order to allow the LDO output to reach the 4.5V threshold and allow switching to begin. Once switching begins, LDO operation transitions from current-source operation to voltage regulation. The minimum operating VIN is then limited by the RDSON of the internal LDO MOSFET. The current required to power the SC508 and external MOSFET gates causes a voltage drop from the VIN pin to the VLDO pin. The VLDO pin must stay above 4.5V, otherwise the LDO control will revert back to current-source operation, causing more voltage drop at the LDO output. The RDSON of the LDO mosfet at low VIN is typically 24 ohms at 25°C. Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is deter- mined by the lowest input voltage including the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design. Nominal output voltage (VOUT) Static or DC output tolerance Transient response Maximum load current (IOUT) There are two values of load current to evaluate — con - tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. VIN = 28V + 10% VOUT = 1.8V + 4% fSW = 220kHz Load = 8A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 220kHz. A resistor, RTON is used to program the on-time (indirectly setting the frequency) using the following equation. OUT INON TON V28pF V)ns10T(R u u To select RTON, use the maximum value for V IN, and for TON use the value associated with maximum VIN. SWINMAX OUT ON fV VT u TON = 266 ns at 30.8VIN, 1.8VOUT, 220kHz Substituting for RTON results in the following solution. RTON = 156kΩ, use RTON = 154kΩ

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Applications Information (continued) Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for power- save operation. The switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then Power-save operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 60% of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is (VIN - VOUT). The following equation for determining induc- tance is shown. RIPPLE ONOUTIN I T)VV(L u In this example the inductor ripple current is set approxi - mately equal to 50% of the maximum load current. Thus ripple current target will be 50% x 8A or 4A. To find the minimum inductance needed, use the VIN and TON values that correspond to VINMAX. QV / u A slightly smaller value of 1.8µH is selected. This will increase the maximum IRIPPLE to 4.3A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. QVQV9 95S)7 ,10,1 287721 21B9,10,1 uu L T)VV(I ONOUTIN RIPPLE u $ȝ+ QV , 0,15,33/(B9,1 u Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is con - trolled by the output ripple requirement and the DC toler- ance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 600mV refer - ence tolerance is 1%. Allowing 1% tolerance from the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 72mV for a 1.8V output. The maximum ripple current of 4.3A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. 9(65 5,33/(0$; 5,33/( 0$; ESRMAX = 16.7 mΩ The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capaci - tance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output capacitor must absorb all the inductor’s stored energy. This will

Applications Information (continued) cause a peak voltage on the capacitor according to the following equation. OUT PEAK RIPPLEMAXOUT MIN VV 1IL COUT § u Assuming a peak voltage V PEAK of 1.98 (180mV rise upon load release), and a 8A load release, the required capaci - tance is shown by the next equation. MIN 1.801.98 4.32 18H1.8 COUT § uP COUTMIN = 272µF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 600mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess induc- tive energy that must be absorbed by the output capaci - tor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capaci- tance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 8 + 1/2 x 4.3 = 10.2A dt dlCurrentLoadofchangeofRate LOAD IMAX = maximum load release = 10A OUTPK LOAD MAX OUT LPK LPKOUT VV2 dtdl I V IL IC uu u Example s A5.2 dt dlLOAD P This would cause the output current to move from 10A to zero in 4µs as shown by the following equation. 1.81.982 s12.5 1.8 10.2H1.8 10.2COUT u PuuP u COUT = 198µF Note that C OUT is much smaller in this example, 198µF compared to 272µF based on a worst-case load release. To meet the two design criteria of minimum 272µF and maximum 16.7mΩ ESR, select a capacitor rated at 330µF and 6mΩ ESR. It is recommended that an additional small capacitor with a value of 1 to 10µF be placed in parallel with COUT in order to filter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect opera - tion. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also impera- tive to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small capacitor across the upper feedback resistor, as shown in Figure 16. This capacitor should be left unpopu- lated unless it can be confirmed that double-pulsing

Applications Information (continued) Dropout Performance The output voltage adjust range for continuous-conduc - tion operation is limited by the fixed 250ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calcu - lated using worst-case values for on and off times. The duty-factor limitation is shown by the following equation. )MAX(OFF)MIN(ON )MIN(ON TT TDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static condi - tions it trips when the feedback pin is 600mV, + 1%. The on-time pulse from the SC508 in the design example is calculated to give a pseudo-fixed frequency of 220kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regu- lation error. For example, if the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to mini - mize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors contributes up to 1% error. If tighter DC accuracy is required, 0.1% resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As VIN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the induc - tor. For a conventional PWM constant-frequency con - verter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). Because the on-time is essentially constant for a given V OUT/VIN combination, to offset the losses the off-time will reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load.

Applications Information (continued) PCB Layout Guidelines A switch-mode converter requires good PCB layout which is essential to achieving high performance. The following guidelines will provide an optimum PCB layout. The device layout recommendations consist of four parts. Grounding for PGND and AGND Power components Low-noise analog circuits Bypass capacitors Grounding for PGND and AGND A ground plane layer for PGND is recommended to minimize the effects of switching noise, resis- tive losses, and to maximize heat removal from the power components. A separate ground plane or island should be used for AGND and all associated components. The AGND island should avoid overlapping switching signals on other layers (DH/DL/BST/LX). Connect PGND and AGND together with a zero ohm resistor or copper trace. Make the connec- tion near the AGND and PGND pins of the IC. Power Components Use short, wide traces between the following power components. Input capacitors and high-side MOSFETs High-side and Low-side MOSFETs and in - ductor (LX connection). Use wide copper traces to provide high current carrying ca- pacity and for heat dissipation. Inductor and output capacitors. All PGND connections — the input capaci- tors, low-side MOSFETs, output capacitors, and the PGND pin of the SC508. An inner layer ground plane is recommended. Each power component requires a short, low impedance connection to the PGND plane. Place vias to the PGND plane directly near the component pins. Use short wide traces for the pin connections from the SC508 (LX, DH, DL and BST). Do not route these traces near the sensitive low-noise analog signals (FB, FBL, SS, TON, VOUT).

• ••• Avoid overlapping of the DL trace with LX/DH/ BST. This helps reduce transient peaks on the gate of the low-side MOSFET during the turn-on of the high-side MOSFET. Low-noise Analog Circuits Low-noise analog circuits are sensitive circuits that are referenced to AGND. Due to their high impedance and sensitivity to noise, it is important that these circuits be located as far as possible from the switching signals. Use a plane or solid area for AGND. Place all components connected to AGND above this area. Use short direct traces for the AGND con- nections to all components. Place vias to the AGND plane directly near the component pins. Proper routing of the VOUT sense trace is essential since it feeds into the FB resistor divider. Noise on the FB waveform will cause instability and multiple pulsing. Connect the V OUT sense trace directly to the output capacitor or a ceramic bypass capacitor. Route this trace over to the VOUT pin, care- fully avoiding all switching signals and power components. Route this trace in a quiet layer if possible. Route this trace away from the switch - ing traces and components, even if the trace is longer. Avoid shorter trace routing through the power switching area. If a bypass capacitor is used at the IC side of the VOUT sense trace, it should be placed near the FB resistor divider. All components connected to the FB pin must be located near the pin. The FB traces should be kept small and not routed near any noisy switch- ing connections or power components. Place the SS capacitor near the SS pin with a short direct connection to the AGND plane. Place the RLIM resistor near the IC. For an accurate ILIM current sense connection, route the RLIM trace directly to the drain of the low-side MOSFET (LX). Use an inner routing layer if needed.

Applications Information (continued) Place the R TON resistor near the TON pin. Route RTON to the TON pin and to AGND using short traces and avoid all switching signals. Bypass Capacitors The device requires bypass capacitors for the following pins. VDDA pin with respect to AGND. This 0.1μF minimum capacitor must be placed and routed close to the IC pins, on the same layer as the IC. This capacitor also functions as bypass for the LDO output, since the VDDA and VLDO pins are adjacent. VDDP with respect to PGND. This 1μF minimum capacitor must be placed and routed close to the IC pins and on the same layer as the IC. BST pin with respect to LX. This 0.1μF minimum capacitor must be placed near the IC, on either side of the PCB. Use short traces for the routing between the capacitor and the IC. VIN pin with respect to AGND. This 0.1μF minimum capacitor must be placed and routed close to the IC pins. This capacitor provides noise filtering for the input to the internal LDO.

Outline Drawing — MLPQ-UT20 3x3 e N PIN 1 INDICATOR (LASER MARK) A C SEATING PLANE E/2 D/2 LxN bxN COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. INCHES DIMENSIONS NOM e bbb aaa DIM N L E MIN D A MILLIMETERS MAXMINMAX NOM E BD NOTES: bbb C A B aaa C .003 .061 .067 .000 .020 (.006) 0.08 .071 1.55 .024 .002 0.00 0.50 1.801.70 0.05 0.60 (0.1524) .004 0.10 1.55 2.90 1.70 1.80 3.00 3.10 0.40 BSC.016 BSC .122.118.114 .071.067.061 A DAP is 1.90 x 190mm.3.

Land Pattern — MLPQ-UT20 3x3 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: C Z R Y X G P H .146 .004 .008 .031 .083 .067 .016 3.70 0.20 0.80 0.10 1.70 0.40 2.10 DIM (2.90) MILLIMETERS DIMENSIONS (.114) INCHES CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). K .067 1.70 THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FUNCTIONAL PERFORMANCE OF THE DEVICE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR H K R (C) X P Y G Z

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