SC5014

SC5014 SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Input Voltage — 4.5V to 27V Output Voltage — Up to 50V Step-up (Boost) Controller Ultra-Fast Transient Response (<00μs) Programmable Switching Frequency Linear Current Sinks

4 Strings, up to 20mA/String

Current Matching ±% Current Accuracy ±2% PWM Dimming String-by-String Phase Shifting Input Dimming Frequency 00Hz-30kHz User Selectable 9 or 0-Bits Dimming Resolution 5-Bits Analog Dimming I2C Interface Fault Status — Open/Short LED, UVLO, OTP Device Control: PLL Setting Protection Features Open/Shorted LED(s) and adjustable OVP Over-Temperature and UVLO Shutdown Protection 4mm X 4mm 20-pin QFN Package

Applications

UltrabooksTM, All-in-One PCs, Monitors, Automotive - Display Backlighting Backlighting for Mid-Size Displays

Description

The SC50 4 is a 4-channel, highly integrated, high-effi - ciency step-up (boost) HB LED driver designed to reduce the thickness of mid-size LCD displays. It features a wide input voltage range (4.5V to 27V), phase-shifted PWM dimming, analog dimming, a flexible output configura - tion, an I2C interface, and numerous protection features. The SC50 4 exhibits 2% to 4% higher efficiency when using the same size inductors as existing LED drivers. But, unlike existing devices, it can also operate with inductors that are up to 0x smaller without sacrificing efficiency. This part can also use very low-profile inductors (as small as 2.2µH, mm height), which allows LED drivers to be built directly into the LCD panel to enable ultra-thin displays. The boost controller, with programmable switching fre - quency from 200kHz to 2.2MHz, maximizes efficiency by dynamically minimizing the output voltage while main - taining LED string current accuracy. It provides excellent line and load response with no external compensation components. An external resistor adjusts the current from 20-20mA per string. It also features PWM dimming reso- lution of 9 or 0-bits (user selectable) over a dimming fre- quency from 00Hz to 20kHz, synchronized to the boost oscillator. String-by-string phase shifting reduces the demand on the input/output capacitance, decreases EMI, and improves dimming linearity. UVLO E-PADISET FSET CPLL SCP SC5014R3 FLT C3 REF FLT VCC PGND R11 R7C4 R10 OVP IO4 VIN=4.5 to 27V Up to 120mA/String IO1 IO2 IO3 PWMIPWMI SDA SCLFor I2C ENEN NDRV CS D1 VOUT up to 50V VCC = 4.5 to 5.5V Typical Application Circuit

Ordering Information

SC504MLTRT()(2) MLPQ-20 4×4 SC504EVB Evaluation Board Notes: () Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. AGND OVP15 IO114 IO213 IO312 IO411 EN CS PGND VCC UVLO 1 SCP 2 REF 3 FSET 4 CPLL 5 PWMI ISET FLT SDA SCL NDRV 5014 yyww xxxxx xxxxx nnnn = Part Number yyww = Date code xxxxx = Semtech Lot No. xxxxx = Semtech Lot No.

Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: () Tested according to JEDEC standard JESD22-A4-B. (2) Calculated from package in still air, mounted to 3 x 4.5in, 4-layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. Absolute Maximum Ratings (refer to PGND) DRVN, OVP , CS, EN, UVLO, SCP , REF, FLT (V) . . -0.3 to +6.0 Recommended Operating Conditions Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . 32 Unless noted otherwise, TA = 25°C for typical, -40°C < TA = TJ < 85°C for min and max. VCC = 5V, RISET = 25.5KΩ, RFSET = 00KΩ. Parameter Symbol Conditions Min Typ Max Units Input Supply VCC Supply Voltage VCC 4.5 5.5 V VCC Under-Voltage Lockout Threshold VCC-UVLO(TH) VCC Voltage Rising 4.2 4.4 V VCC Under-Voltage Lockout Hysteresis VCC-UVLO(HYS) VCC Voltage Falling 80 mV VCC Quiescent Supply Current ICC(Q) EN = 5V, Switching, No Load 2 mA VCC Supply Current in Shutdown ICC(SD) EN = 0V µA VUVLO Under-Voltage Lockout Threshold VUVLO(TH) UVLO Pin Voltage Rising .8 .23 .28 V IUVLO Under-Voltage Lockout Hysteresis IUVLO(HYS) UVLO Pin Voltage Falling 7 0 3 µA VREF Bandgap Voltage VREF .20 .23 .26 V External FET Gate Drive DRVN High Level VDRVN(H) 00mA from DRVN to GND VCC -0.5 VCC -0.2 V DRVN Low Level VDRVN(L) -00mA from DRVN to VCC 0.2 0.5 V DRVN On-Resistance RDRVN DRVN High or Low 2 5 Ω DRVN Sink / Source Current IDRVN DRVN Forced to 2.5V A Boost Converter CS Current Limit Threshold VCS(ILIM) 0.36 0.40 0.44 V Soft-Start Time () tSS From EN to End of Soft-Start 4.4 ms

Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units Boost Oscillator Frequency FSW RFSET = 00kΩ 0.85 .5 MHz Boost Oscillator Frequency FOSC RFSET Varies 0.2 2.2 MHz Maximum Duty Cycle DMAX 88 92 % Control Signals: EN, PWMI, SDA, SCL High Voltage Threshold VIH VCC = 4.5V to 5.5V 2. V Low Voltage Threshold VIL VCC = 4.5V to 5.5V 0.8 V SDA Output Low VSDA(L) -6mA from VCC to SDA 0.3 V Pin Leakage Current ILEAK VEN = 0V, VPWMI = VISET = VFSET = VSDA = VSCL = 5.0V - µA PWM Dimming Input PWMI Input Dimming Frequency FPWMI 00 30k Hz PWMI Input Resolution 00Hz < FPWMI < 0kHz 0 bits 0kHz < FPWMI < 20kHz 9 bits Over-Voltage Protection OVP Trip Threshold Voltage VOVP(TRIG) OVP Rising . .2 .3 V OVP Hysteresis VOVP(HYS) OVP Falling 0 mV OVP Leakage Current IOVP(LEAK) OVP = 5V 0. µA Current Sink (IO1 to IO4) IOx Dimming Minimum Pulse Width TPWM(MIN) FPWM(LED) = 00Hz - 30kHz 300 ns ISET pin Voltage VISET .23 V Regulation Voltage VIOn(REG) Voltage of Regulating String 0.9 V Current Sink Disable Threshold VIOn(DIS) Checked at Power-up 0.6 V Current Sink Rise/Fall Time () tRISE/FALL Rising Edge from 0% to 90% of IO(n) 25 ns LED Current Accuracy IOn(ACC%) PWMI = 00%, TA=+25 °C 98 00 02 mA LED Current Matching (2) IOn(MATCH) PWMI = 00%, TA=+25 °C ±.0 % IOn Off Leakage Current IOn(LEAK) PWMI = 0V, EN = 0V, VIO = 25V 0. µA IO Switching Frequency FPWM(IO) FAST_FREQ = 0 0 kHz FAST_FREQ = (Default Setting) 20 Phase Delay Time Between IO Pins (IO to IO4) tPD FAST_FREQ = (Default Setting) tPD = (/4)*(/FPWM(IO)), 4 Strings On 2.5 µs PWM Output Resolution FPWM(IO) = 0kHz 0 bits FPWM(IO) = 20kHz 9 Electrical Characteristics (continued)

Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Fault Protection LED Short-Circuit Protection Threshold VIOn(SCP) R4 and R5 (3) 7xVSCP 20xVSCP 23xVSCP V LED Open-Circuit Protection Threshold VIO_OCP 0.2 V LED Short-Circuit Fault Delay tSCP(DELAY) VOVP Set to .5V, FLT Goes Low µs FLT Pin Leakage Current IFLT(LEAK) VEN = 0V, VFLT = 5.0V - µA FLT Output Low VFLT(LOW) -5mA from FLT to VCC 0.3 V Over-Temperature Protection Thermal Shutdown Temperature TOTP 50 °C Thermal Shutdown Hysteresis TOTP-H 0 °C I2C Control Interface: SDA, SCL Timing Specifications SCL Clock Frequency FSCL 400 kHz SCL Clock Low Period tLOW(SCL) .3 µs SCL Clock High Period tHIGH(SCL) 0.6 µs Hold Time Start Condition tHD(START) 0.6 µs SDA Setup Time tSU(SDA) 00 ns SDA Hold Time tHD(SDA) 0 0.9 µs Setup Time Stop Condition tSU(STOP) 0.6 µs Bus Free Time Between Stop & Start tBF .3 µs Notes: () Ensured by design and characterization, not production tested. (2) LED current matching for 4 channels is defined as the largest of the two numbers, i.e., (MAX-AVG)/AVG and (AVG-MIN)/AVG; where MAX is the maximum LED channel current, MIN is the minimum LED channel current and AVG is the average of the 4 LED channel currents. (3) Refer to the application circuit on page 23, Figure 2.

VIN(V) ˋ˃ˋ˃ ˋ˃ˋ˃ ˋˈˋˈ ˋˈˋˈ ˌ˃ˌ˃ ˌ˃ˌ˃ ˌˈˌˈ ˌˈˌˈ ˩˜ˡʻ˩ʼ ˉ˃̀˔ Backlight Efficiency vs. Input Voltage 120mA/CH 60mA/CH Backlight Efficiency vs. Input Voltage 10S4P ˋ˃ˋ˃ ˋ˃ˋ˃ ˋˈˋˈ ˋˈˋˈ ˌ˃ˌ˃ ˌ˃ˌ˃ ˌˈˌˈ ˌˈˌˈ ˊ˦ˇˣˊ˦ˇˣˊ˦ˇˣˊ˦ˇˣ Backlight Efficiency vs. Input Voltage 10S4P 7S4P Backlight Efficiency vs. Input Voltage 120mA/CH VIN(V) LED PWM Dimming Duty Cycle (%) Backlight Efficiency vs. LED String Current Backlight Efficiency vs. LED String Current LED PWM Dimming Duty Cycle (%) PWM Dimming Linearity with Phase Shift PWM Dimming Linearity with Phase Shift LED PWM Dimming Duty Cycle (%) Efficiency(%)Efficiency(%) Efficiency(%) Iout (mA)Iout (mA) LED PWM Dimming Duty Cycle (%) PWM Dimming Linearity with Phase Shift ˃˃ ˃˃ ˈ˃ˈ˃ ˈ˃ˈ˃ 60mA/CH, 10S4P , 20KHz Dimming PWM Dimming Linearity with Phase Shift ˃˃ ˃˃ 120mA/CH, 10S4P , 20KHz Dimming ˉˈˉˈ ˉˈˉˈ ˊ˃ˊ˃ ˊ˃ˊ˃ ˊˈˊˈ ˊˈˊˈ ˋ˃ˋ˃ ˋ˃ˋ˃ ˋˈˋˈ ˋˈˋˈ ˌ˃ˌ˃ ˌ˃ˌ˃ ˌˈˌˈ ˌˈˌˈ Backlight Efficiency vs. LED string Current 120mA/CH 60mA/CH Efficiency(%) ˉˈˉˈ ˉˈˉˈ ˊ˃ˊ˃ ˊ˃ˊ˃ ˊˈˊˈ ˊˈˊˈ ˋ˃ˋ˃ ˋ˃ˋ˃ ˋˈˋˈ ˋˈˋˈ ˌ˃ˌ˃ ˌ˃ˌ˃ ˌˈˌˈ ˌˈˌˈ Backlight Efficiency vs. LED string Current 120mA/CH 60mA/CH VIN=6V VIN=12V

Temperature (°C) LED String Current Matching vs. Temperature LED String Current vs. RISET ˃˃ ˃˃ LED String Current vs. RISET RFSET(KΩ) Switching Frequency vs. RFSET IDAC Register Value (in decimal format) Analog Dimming 100 125 0 4 8 12 16 20 24 28 32 DEC ILED(mA) IO1 LED String Current vs. Analog Dimming Control Register (IDAC) Value LED String Current Matching (%) Boost Switching Frequency (KHz) LED String Current (mA) Typical Characteristics (continued) LED String Current Matching vs. Temperature ˃ˁˇ˃ˁˇ ˃ˁˇ˃ˁˇ ˃ˁˉ˃ˁˉ ˃ˁˉ˃ˁˉ ˃ˁˋ˃ˁˋ ˃ˁˋ˃ˁˋ VCC=5V, 120mA/CH LED String Current vs. RISET ˃˃ ˃˃ ˆ˃ˆ˃ ˆ˃ˆ˃ ˉ˃ˉ˃ ˉ˃ˉ˃ ˌ˃ˌ˃ ˌ˃ˌ˃ RISET(KΩ) LED String Current (mA) LED String Current Accuracy vs Temperature Current Accuracy vs. Temperature ˜ˢˆ˜ˢˆ˜ˢˆ˜ˢˆ Temperature (°C) LED String Current Accuracy (mA) VCC=5V, 120mA/CH Time (20ms/div) VIN Start UP Testing condition: VIN=12V,VCC=5V, LEDs=10S4P@120mA, RFSET=100KӨӨ ӨӨ, 25кк кк Iout Vout Vin SW VIN Start Up VIN 10V/div. VSW 20V/div. VOUT 20V/div. IOUT 300mA/div. 10S4P , 120mA/CH

Time (100ms/div) Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120/CH, PWM indirect mode; PWM=10KHz, PWMI on / off, duty=0% to 100% LED Current Fade In/Out (Logarithmic) V_IO4 Iout Vout PWMI LED Current Fade In/Out (Logarithmic) Line Transient Response LED Open Circuit Protection 100% dimming, 120mA/CH X 4 Typical Characteristics (continued) PWMI 5V/div. VIO1 10V/div. VOUT 20V/div. IOUT 200mA/div. Time (100ms/div) Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120/CH, PWM indirect mode; PWM=10KHz, PWMI on / off, duty=0% to 100% Fade in/Fade out (Linear) V_IO4 Iout Vout PWMIPWMI 5V/div. VIO1 10V/div. VOUT 20V/div. IOUT 200mA/div. LED Current Fade In/Out (Linear) Time (4us/div) Test condition: 8Vin to 20Vin, 10S4P@120mA per string, RFSET=100KӨӨ ӨӨ, Vin RT=1us Line Transient Response V_IO4 IL Vout PWMI VIN 10V/div. VOUT 1V/div. VIO1 1V/div. IL 3A/div. Time (20ms/div) LEDs Open-circuit Protection Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, CH4 open, RFSET=100KHz, ROVP2=357KӨӨ ӨӨ EN Iout Vout FLT VEN 5V/div. FLT 5V/div. VOUT 20V/div. IOUT 200mA/div. Starting with one LED string open-circuit Load Transient Response Load Transient Response PWMI(10KHz)=2% to 98%, VIN=12V, 120mA/CH X 4 Fading disabled Time (100us/div) Load Transient Response Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=10K, Duty=2% to 98% Iout Vout PWMI PWMI 5V/div. VOUT 200mV/div. IOUT 200mA/div. Time (100ms/div) Load Transient Response Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=10K, Duty=98% to 2% Iout Vout PWMI 20V PWMI(10KHz)=98% to 2%, VIN=12V, 120mA/CH X 4 Fading disabled PWMI 5V/div. VOUT 200mV/div. IOUT 200mA/div.

Time (2ms/div) LED Dimming Without Phase Shift Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=200HZ, Duty=10% IL V_IO1 V_IO2 Iout LED Dimming Without Phase Shift LED Dimming Without Phase Shift LED Dimming With Phase Shift 35% dimming@200Hz, VIN=12V, 4P10S, 120mA/CH Typical Characteristics (continued) VIO1 10V/div. VIO2 10V/div. IL 1A/div. IOUT 400mA/div. LED Dimming With Phase Shift Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=200HZ, Duty=10% IL V_IO1 V_IO2 Iout LED Dimming With Phase Shift LED Dimming Without Phase Shift Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=200HZ, Duty=35% IL V_IO1 V_IO2 Iout LED Dimming With Phase Shift Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, PWMI=200HZ, Duty=35% IL V_IO1 V_IO2 Iout 35% dimming@200Hz, VIN=12V, 4P10S, 120mA/CH Time (40us/div) Analog Dimming Transient via I2C Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, 60mA/CH to 120mA/CH Iout Vout SDA SW VSW 20V/div. IOUT 300mA/div. Analog Dimming Transient via I2C Testing condition: VIN=12V, 25кк кк, LEDs=10S4P@120mA/CH, RFSET=100KHz, 120mA/CH to 60mA/CH Iout Vout SDA SW Time (2ms/div) VIO1 10V/div. VIO2 10V/div. IL 1A/div. IOUT 400mA/div. 10% dimming@200Hz, VIN=12V, 4P10S, 120mA/CH 10% dimming@200Hz, VIN=12V, 4P10S, 120mA/CH Time (2ms/div) VIO1 10V/div. VIO2 10V/div. IL 1A/div. IOUT 400mA/div. Time (2ms/div) VIO1 10V/div. VIO2 10V/div. IL 1A/div. IOUT 400mA/div. Analog Dimming Transient via I2C Analog Dimming Transient via I2C 60mA/CH to 120mA/CH 120mA/CH to 60mA/CH VSDA 5V/div. VOUT 2V/div. Time (40us/div) VSW 20V/div. IOUT 300mA/div. VSDA 5V/div. VOUT 2V/div.

Pin # (QFN) Pin Name Pin Function UVLO Input under-voltage lockout pin — Device is disabled when this pin is less than .23V (nominal). Add a resistor divider from this pin to the input voltage and AGND, respectively.

2 SCP

Short-circuit LED protection programming pin — Shorted LED protection disables the individual channel when the current sink voltage exceeds the programmed voltage threshold. Adding a resistor divider from this pin to REF and PGND programs the shorted-LED protection up to 20x the VSCP voltage. Pulling the pin high to VCC disables the SCP feature on all channels. 3 REF .23V reference voltage output pin — Connect a µF ceramic bypass capacitor from this pin to ground. 4 FSET Step-up (boost) frequency set pin — Connect a resistor from this pin to ground to set the frequency from 200kHz to 2.2MHz. 5 CPLL Compensation for the internal PLL — Connect a compensation resistor and capacitor from this pin to ground. This pin can be left floating if not used. 6 SCL I2C serial clock input — This pin must be connected to ground if not used. 7 SDA I2C serial data input — This pin must be connected to ground if not used. 8 ISET LED current programming pin — Connect an external resistor to ground to program the current in the LED strings. For more details please refer to LED String Peak Current Programming on page 3.

9 FLT

Logic low fault status pin — Open-drain output is latched low when fault condition is detected: Open/Short LED, Shorted String, OVP or OTP . Fault status can be reset by removing fault condition(s) and toggling the EN, VCC or UVLO pins. This pin can be left floating if not used. 0 PWMI LED string PWM dimming control input. ~4 IO4 ~ IO Regulated current sink LED channel 4 to channel respectively — Connect the related IO pin to the cathode of the bottom LED in string 4 to string respectively. Connect the related IO pin to ground to disable the related LED string during power on. 5 OVP Over-voltage feedback pin — Over-voltage activated when pin voltage exceeds .2V. Use a resistor divider tied to the output and GND to set the OVP level. 6 CS Step-up (boost) switch current sense pin — Connect a resistor from this pin to ground for current sense - utilized in peak current mode control loop and over-current sense circuitry. 7 PGND Power ground — Tie this pin to the power ground plane close to input and output decoupling capacitors. 8 NDRV Gate drive for the external step-up (boost) N-Channel MOSFET. 9 VCC Input bias voltage supply for the IC — Accepts 4.5-5.5V inputs. Add a µF or larger ceramic bypass capacitor from this pin to ground. 20 EN Logic high enable pin — Pull logic high to enable the device or pull low to disable and maintain low shutdown current. - PAD AGND thermal pad for heatsinking purposes — It should be connected to ground plane for proper circuit operation.

(PLL range) PWM Freq. Adjust 5-bit DAC UVLO Boost Oscillator VBG SCPREF X20 SC_REF Duty Cycle Extractor Recycle Generator I2C Interface and LED Control Logic Control Logic FLT OC/SC Detection SC_REF IO4 COMP OSC CLIM + +- PWM COMP Slope Comp 10MHz (System Clk) PGND DC DC BG ILIM OVP

The SC50 4 contains a high frequency, current-mode, internally compensated boost controller with 4 constant current sinks for driving LED strings. The LED current for all strings is programmed by an external resistor. The boost converter operates to maintain minimal required output voltage for regulating the LED current to the programmed value. A typical backlight application uses 3 to 4 LEDs per each string, with current driven up to 20mA. The unique control loop of the SC50 4 allows fast transient response in dealing with line and load disturbances. The SC504, operating with an external power MOSFET, regu- lates the boost converter output voltage based on the instantaneous requirement of the 4 string current sources. This provides power to the entire lighting subsystem with increased efficiency and reduced component count. It supports PWM dimming frequencies from 00Hz to 30kHz and the supply current is reduced to 2mA typical when all LED strings are off. Start-Up When the EN pin is pulled up high (>2. V), the device is enabled and the UVLO and VCC pin voltages are checked. The VCC voltage has fixed under-voltage rising and falling trip points. If the VCC pin is higher than 4.2V and the UVLO pin voltage is greater than .23V, the SC504 goes into a start-up sequence. The UVLO pin voltage can be used to program the input power source voltage VIN turn-on threshold and its hysteresis (refer to the detailed applica - tion circuit on page 23, Figure 2) as shown by the follow - ing equations: VIN_TurnOn [V] = .23 X (R + R2) / R VIN_Hysteresis [V] = 0-5 X R2 [Ω] In the next phase, the SC504 checks each IO pin to deter- mine if the respective LED string is enabled. Each IO pin is pulled up with a 00µA current source. If any IO pin is con- nected to ground, it will be detected as an unused string, and will be turned off. This unused string checking proce- dure typically takes ms. After this, the SC504 enters into a soft-start sequence. The soft-start function helps to prevent excess inrush current through the input rail during start-up. In the SC504, the soft-start is implemented by slowly ramping up the reference voltage fed to the error amplifier. This closed loop start-up method allows the output voltage to ramp up without any overshoot. The duration of the soft-start in the SC504 is controlled by an internal timing circuit, which is used during start-up and is based on the boost converter switching frequency. For example, with switching frequency at MHz, it is 8ms typical and becomes 4ms typical when the switching frequency is 2MHz. If the PWM voltage goes low while the SC504 is in soft - start operation, the SC50 4 switches to standby mode, where the external power MOSFET and the LED current sources will be turned off immediately. The internal soft- start timer is turned off and the soft-start value is saved. When the PWM voltage goes hi gh again, the soft-start resumes from the previously saved value. Each LED current source (IO to IO4) tries to regulate the LED current to its set point. The control loop will regulate the output voltage such that all the IO pin voltages are at least 0.9V typical. Shutdown When the EN pin is pulled down below 0.8V, the device enters into shutdown mode. In this mode, all the internal circuitry is turned off and the supply current is less than µA (max). In the scenario where the EN pin voltage is high, but VCC voltage falls below the respective UVLO threshold, the SC504 goes into a suspend mode. In this mode, all the internal circuitry except the reference and the oscillator are turned off. Thermal Shutdown (TSD) If the thermal shutdown temperature of typical 50°C is reached, the boost converter and all IO current sources are turned off. The FLT pin is forced low in this condition. When the temperature falls below the TSD trip point by 0°C, the SC50 4 will restart following the start-up sequence as described before. The FLT pin is latched and will stay low, it is reset by cycling the EN, VCC or UVLO. Applications Information

Applications Information (continued) Boost Converter Operation The SC504 includes a boost controller with programma- ble switching frequency. It applies a current-mode control method with an integrated compensation loop as shown in the diagram below. The clock (see block diagram on page) from the oscillator sets the latch and turns on the external power MOSFET, which serves as the main power switch. The current flowing through this switch is sensed by the current sense resistor in series with the switch. The sensed switch current is summed with the slope-com - pensated ramp and fed into the modulating input of the PWM comparator. When the modulating ramp intersects the error amplifier output (COMP), the latch is reset and the power MOSFET is turned off. The sense resistor also sets the peak current limit of the power MOSFET, IOCP using the following equation: IOCP[A] = 0.4 / RCS [Ω] EA Min. Voltage Detection Boost Oscillator Control Logic COMP OSC + +- PWM COMP Slope Comp DC VIN=4.5 to 27V IO LS CS NDRV RCS The current-mode control system contains two loops. For the inner current loop, the error amplifier (EA) output (COMP) controls the peak inductor current. In the outer loop, the EA regulates the output voltage for driving the LED strings. Boost Converter Switching Frequency Selection The resistor between FSET and GND sets the boost con - verter switching frequency (200kHz to 2.2MHz) using the following equation: fSW [kHz] = 05/ RFSET [kΩ] A higher switching frequency allows the use of low-profile height inductors for space-constrained and cost-sensitive applications. Over-Voltage Protection (OVP) The SC504 features programmable output over-voltage protection to prevent damage to the IC and output capaci- tor in the event of a LED string open-circuit. The boost con- verter output voltage is sensed at the OVP pin through the resistor voltage divider. The OVP trip threshold (refer to detailed application circuit on page 23, Figure 2) can be cal- culated using the following equation: OVP Trip Voltage [V] = .2 X (R + R2) / R2 When the OVP pin voltage exceeds .2V, the boost con - verter turns off and the FLT pin is pulled low. When the OVP pin voltage falls below the OVP threshold (falling), the boost converter restarts and the FLT pin is released. There is 0mV hysteresis between the OVP pin threshold (falling) and the OVP pin threshold (rising). This results in an output voltage hysteresis expressed as: Output OVP Hysteresis [mV] = 0 X (R + R2) / R2 LED Current Sink The SC504 provides 4 current sinks and each can sink up to 20mA current. It incorporates LED string short-circuit protection (trip-level programmable; can be disabled) and LED string open-circuit protection. LED String Peak Current Programming LED string peak current (at 00% dimming) can be set by selecting resistor RISET, connected between ISET and GND. The relationship between R ISET resistance and single LED string peak current is calculated using the following equation: ILED [mA] = 2 X (036 X .23) / RISET [kΩ] The string current can be programmed up to 20mA. Unused Strings The SC504 may be operated with less than 4 strings. In this mode of operation, all unused IO pins should be con- nected to ground. During start-up, these unused strings are detected and disabled while other active strings work normally, and FLT does not get pulled low.

Applications Information (continued) The SC504 has a unique DAC architecture which allows it to have excellent LED current accuracy and string-to-string matching over the entire DAC range. The analog dimming method can be used in conjunction with PWM dimming to increase the dimming resolution. The fast loop response of the SC50 4 allows the LED current to transition to a new value within 60µs or so. Please refer to the graphs in the typical characteristics section. LED PWM Dimming Control The SC50 4 supports three PWM dimming modes for controlling the brightness of the LEDs. The dimming modes are: () PWM direct, (2) PWM indirect and (3) I2C control It provides flexibility in setting the duty cycle and fre - quency of the LED PWM signal. The PWM dimming mode is set through the device control register (register address: 0x0) DCR [:0] bits. Refer to Table for more details. (1) PWM Direct Control The PWM input needs to be held high for normal opera - tion. PWM dimming can be achieved by cycling the PWM input at a given frequency where a “low” on the PWM input turns off all IO current sinks and a “high” turns on all IO current sinks. The PWM pin can be toggled by external circuitry to allow PWM dimming. In a typical application, a microcontroller sets a register or counter that varies the pulse width on a GPIO pin. The SC50 4 allows dimming over a wide frequency range ( 00Hz-30kHz) in order to allow compatibility with a wide range of devices. This includes the newest dimming strategies that avoid the audio band by using high frequency PWM dimming. In this manner, a wide range of illumination can be gener - ated while keeping the instantaneous LED current at its peak value for high efficiency and color temperature. The SC504 provides a 000: dimming range at kHz PWM frequency. The LED current sinks turn on/off very rapidly (<25ns, typical). This allows a wide dimming ratio. An addi- tional advantage of PWM dimming is that it avoids in-rush currents when filling the boost output capacitor. Simply apply the PWM signal to the device at 0% duty for a milli- second or two, and in-rush current is reduced. This dimming time will vary based on the number of LEDs and the size of the output capacitor. This can be easily deter - mined during testing and programmed into the microcon- troller firmware. Table 1 — LED Dimming Control Methods PWM Dim- ming Mode Register Settings DCR[1:0] PWM Input Source LED PWM Output Phase Shift OptionPWM Frequency PWM Duty Cycle PWM Direct Control 00 PWMI Pin Input Same as the PWMI Input (Range 00 Hz to 30kHz) Same as the PWMI Input NO PWM Indirect Control (Default Option)

0 PWMI Pin

(0x05) and FAST_FREQ Bit 0kHz (max): FAST_FREQ=0 20kHz (max): FAST_FREQ= Same as the Duty Cycle of the PWM Input YES I2C Control I2C Control Set via the FREQ Register (0x05) and FAST_FREQ bit 0kHz (max): FAST_FREQ=0 20kHz (max): FAST_FREQ= Set Via the Duty Cycle Control Register (0x03, 0x04) 0-Bits @ 0kHz Output 9-Bits @ 20kHz Output YES

Applications Information (continued) (2) PWM Indirect Control This is the default mode for LED PWM dimming in the SC504. In this mode, the input signal applied on the PWM pin is passed through a duty cycle extractor block after the system has detected two successive duty cycles that are the same. The extractor measures the duty cycle of the PWM input, and, depending on the value of FAST_FREQ, the duty cycle is converted to a 9-bit value (FAST_FREQ = ) or a 0- bit value (FAST_FREQ = 0). This value is then passed to the PWM generator block as shown in Figure . The LED PWM output frequency is set via the FREQ regis - ter (address 0x05) and the FAST_FREQ bit. With FAST_FREQ = 0, low dimming frequency option is selected and the PWM dimming frequency will be accord- ing to the following equation: 10kHz(max) MHz10FrequencyDimmingPWM +×= With FAST_FREQ = , the high dimming frequency option is selected and the PWM dimming frequency is shown by the following equation: 20kHz(max) ] 1] 0:7 [FREQ[512 MHz10FrequencyDimmingPWM +×= The default option is FAST_FREQ = . This gives 9-bit duty cycle resolution and up to 20kHz dimming frequency range. The PWM input is usually generated by the system graphics processor. This mode allows the user to set the PWM output dimming frequency independent of the PWMI input. If the PWM signal has jitter, the SC504 provides an option to filter it out. Hysteresis is also provided by selecting the WND[:0] bits in the DCR register (address 0x0). WND[:0] bits set the window comparator such that if a change in the duty cycle is detected which is smaller than the set window, then it is ignored. (3) I2C Control In I2C dimming mode (refer to Figure , page 4), both the output LED dimming duty cycle and the dimming fre - quency are set via the internal registers. The PWMI pin should be connected to ground. In this mode, the LED dimming duty cycle is set via the duty cycle registers (addresses 0x03, 0x04); and the dimming frequency is set via the FREQ register (address 0x05) and the FAST_FREQ bit. With FAST_FREQ = 0, the LED duty cycle can achieve 0-bit resolution, D[9:0], which is combined by two portions: () MSB portion - register address 0x03 [:0] and (2) LSB portion - register address 0x04 [7:0] as shown below. The dimming duty cycle with FAST_FREQ = 0 can be calcu- lated as: LED Dimming Duty Cycle = {D[9:0]decimal }/20- With FAST_FREQ = , the LED duty cycle can achieve 9-bit resolution, D[9:], which is combined by two portions: () MSB portion - register address 0x03 [:0] and (2) LSB portion - register address 0x04 [7:] as shown below. The dimming duty cycle with FAST_FREQ = can be calcu- lated as: LED Dimming Duty Cycle = {D[9:]decimal }/29- In both cases mentioned above, the duty cycle is fixed to be 0 when D[9:0] is set as 0x00. The PWM dimming frequency is controlled the same way as in “Indirect Control” .

The SC504 provides an option for phase-shifted LED PWM dimming. This option is available in both PWMI indirect control and I2C control. The phase-shift option is set by the PH_SHIFT bit in the Device Control Register (register address 0x0). This option delays the turn-on of the LED strings based on the number of the strings in operation (the number of the strings in operation is determined during the start-up). The delay time can be calculated by the following equation: frequency dimming PWM LEDf operation in strings of number N fT PWM PWM phase φ Phase-shift mode is disabled during the soft-start period. This allows the output to ramp up to the correct voltage in a controlled fashion. Phase-shifting reduces the peak input current, decreases EMI and improves the dimming linearity. The figures in the Typical Characteristics Section on page 6 show the improvement in dimming linearity with phase-shifted versus non-phase-shifted dimming. Backlight Fade-in and Fade-out Options The SC50 4 features an option for fade-in and fade-out brightness control, which allows a smooth transition from one brightness level to another. Registers associated with these fading functions are shown in this section. Fade Option (register address 0x09) — sets fade enable options, fade time, fade type. Fade Rate (register address 0x0A) — sets fade step size option. The fade option register allows the user to select fading, choose between linear or logarithmic fading, and to set the fading time. The default setting is fading enabled with logarithmic mode. The fading time is determined by the LED PWM dimming frequency. The fade setting is shown in Table 2. An example for calculating the fading time is shown in this section. Assuming LED PWM dimming frequency is 0kHz, then 0-bits are assigned for 024 duty cycle settings. Table 2 — Fade Setting Duty Cycle Zone Duty Cycle Range Step Increment Step Interval Total Steps within the Range 0 to 5 2 52 2 52 to 767 256 3 768 to 024 2 256 The time required to go from 0% ( 02/024) to 90% (922/024) duty cycle can be calculated using the follow- ing equation: TPWM = 00 µs (with 0kHz dimming frequency) Cycle in Zone # = (5 - Starting Duty Cycle) x [(Zone # Step Interval) / (Zone # Step Increment)] Cycle in Zone #2 = Total Steps in Zone #2 x [(Zone #2 Step Interval) / (Zone #2 Step Increment)] Cycle in Zone #3 = (End Duty Cycle - 768) x [(Zone #3 Step Interval) / (Zone #3 Step Increment)] In this case, the total cycle will be: Total cycle = 2 x (5-02) + x 256 + 0.5 x (922 - 768) = 5 Total Fading Time = Total Cycle x TPWM = 5 x 00 µs = 5.ms Time required to go from 0% ( 02/ 024) to 90% (922/024) duty cycle can be calculated using the follow- ing equation: ms 115.1T1151 TimeTotal )()( Cycle Total Period) Dimming (PWM μs 100T PWM PWM =×= =−×++−×= 11517689222 12561025112 Applications Information (continued)

Table 3 — Fault Protection Descriptions Type of Fault User Disable? Fault Criteria Action on Fault Recovery Device FL T pin (latching / non-latching Condition(s) FL T pin Input Under-voltage at VIN (UVLO) No VIN < ( + R2/R) x .23 (rising) No Startup Not Active VUVLO > .23V (rising) High No VIN < ( + R2/R) × .23V - IUVLO × R (falling) Shutdown Not Active VUVLO > .23V (rising) High Input Under-volt- age at VCC (UVLO) No VCC < 4.2V (rising) No Startup Not Active VCC > 4.2V (rising) High No VCC < 4.0V (falling) Shutdown Not Active VCC > 4.2V (rising) High Over-voltage Protection (OVP) No VOVP > .23V (rising) Regulate to OVP threshold: IO(n) = “on” Low (non-latching) VOVP < .22V (falling) High on re- moval of fault condition Over-current Protection (OCP) No VCS > 0.4V Limit Q FET drain current < 0.4V/R9 (typ) () High VCS > 0.4V High Shorted LED(s) Yes, tie SCP to VCC VIO(n) > 20 x VSCP Device on: IO(n) = “off” Other IO(All) = “on” Low (latching) Replace Shorted LED(s) and Toggle EN, VCC or UVLO High VIO(All) > 20 x VSCP Device latch-off; IO(All) = “off” Low (latching) Replace Shorted LED(s) and Toggle EN, VCC or UVLO High Open LED(s) No VIO(n) < 0.V and OVP event Device on: IO(n) = “off” Other IO(All) = “on” Low (latching) Replace Open LED(s) and Toggle EN, VCC or UVLO High VIO(All) < 0.V and OVP event Device latch-off; IO(All) = “off” Low (latching) Replace Open LED(s) and Toggle EN, VCC or UVLO High Unused Strings No VIO(All) < 0.V (start up) Device on: IO(n) = “off” Other IO(All) = “on” High Over-Tempera- ture Protection (OTP) No TJ > 50ºC (typ) Device off; IO(All) = “off” Low (latching) Satisfy THYS > 0ºC; Device On; IO(All) = “on”; Toggle EN, VCC or High Note: Refer to the application circuit example for R and R2 on page 23, Figure 2.

Applications Information (continued) Fault Protection The SC50 4 provides fault detection for low supply voltage, LED related faults, boost converter over-voltage and thermal shutdown. The open drain output pin ( FLT) indicates a system fault. The nature of the fault can be read from the fault status resistor (register address: 0x00) via I2C interface. Refer to Table 3 for a description of the Fault Protection Modes. Other Possible Configurations Depending on different application requirements, the SC504 can also be easily configured to other topologies, such as the SEPIC configuration shown in Figure 4, page 24. Li-Ion Powered Display Configuration If a Li-Ion powered display application is required, V CC is needed to power with 5V. However, V IN can be set lower from 3V to 4.2V for example. An advantage of this type of configuration is that it provides higher efficiency. Please use Figure 3 on page 23 for reference. High Output Voltage Configuration If a high output voltage application is required, an addi - tional external cascode MOSFET can be added on each IO pin to meet such requirement, please refer to Figure 5 on page 24 for reference. In this case, the upper limit on the output voltage is mainly determined by the rating of the external MOSFET, heat dissipation, etc. PCB Layout Considerations The placements of the power components outside the SC504 should follow the layout guidelines of a general boost converter. The Detailed Application Circuit is used as an example. Capacitor (C2) should be placed as close as possible to the VCC and AGND to achieve the best performance. Capacitor (C) is the input power filtering capacitor for the boost. It needs to be tied to PGND. The converter power train inductor (L ) is the boost converter input inductor. Use wide and short traces connecting these components. The output rectifying diode (D) uses a Schottky diode for fast reverse recovery. Transistor (Q) is the external switch. Resistor (R9) is the switch current sensing resis- tor. To minimize switching noise for the boost con - verter, the output capacitor (C6) should be placed such that the loop formed by Q , D, C6 and R9, is minimized. The output of the boost converter is used to power up the LEDs. Use wide and short trace con - necting Pin NDRV and the gate of Q. The GNDs for R9 and C6 should be PGND. These components should be close to the SC504. Resistor (R8) is the output current adjusting resistor for IO through IO4 and should return to AGND. Place it next to the IC. Resistor (R6) is the switching frequency adjusting resistor and should return to AGND. Place it next to the IC. The decoupling capacitor (C3) for Pin REF should return to AGND. Place it next to the IC. Resistors (R4, R5) form a divider to set the SCP level, R4 should return to AGND. Place it next to the IC. Resistors (R2, R) form a divider to set the UVLO level for UVLO pin. R should return to AGND. Place it next to the IC. R and R 0 form a divider to set the OVP level for VOUT, R0 should return to AGND. Place it next to the IC. All the traces for components with AGND connection should avoid being routed close to the noisy areas. An exposed pad is located at the bottom of the SC504 for heat dissipation and analog ground. A copper area underneath the pad is used for better heat dissipation. On the bottom layer of the PCB another copper area, connected through vias to the top layer, is used for better thermal performance. The pad at the bottom of the SC50 4 should be connected to AGND. AGND should be connected to PGND at a single point for better noise immunity.

state operation, transient response, and its loop stability. current can be calculated using the following equation. 4 lists some recommended inductors and their vendors. Table 4. Recommended Inductors

V RIPPLE – Peak to peak output ripple. 480mA, and 6x 4.7µF capacitors are recommended. their low forward voltage drop and fast switching speed. current will be sufficient for most designs. Table 5. Recommended Rectifier Diodes are preferred for achieving better efficiency. drive the MOSFET is given by the following equation.

Components Selection (continued) Current Sensing Resistor Selection The switch current is sensed via the current sensing resis- tor, RCS. The sensed voltage at this pin is used to set the peak switch current limit and also used for steady state regulation of the inductor current. The current limit com- parator has a trip voltage of 0.4V (typical). R CS value is chosen to set the peak inductor and switch current using the following equation. I 2 SW(Peak) = 0.4/RCS The power dissipation in RSNS can be calculated using the following equations. PR_CS = IRMS 2 x RCS IRMS = D x [IO/(1-D)]2 I O = Output DC Current, D = Duty Cycle For the typical application circuit shown in the detailed application circuit (page 23, Figure 2), the power dissipa - tion on the sensing resistor is shown by the following equations. Assuming VIN = 6V and VOUT = 3.5V, thus D = 8%, For this example, a 0.08 Ω % thick-film chip resistor rated at W can be used. PLL Filter Component Selection The detailed application circuit on page 23, Figure 2 shows the optimal R/C filter components for the PLL compensa- tion. These are optimized for internal MHz switching fre- quency. Please contact Semtech Power management Application Group if a different switching frequency is selected.

Figure 2— Application Circuit Example, 40 LED @ 100mA 2.7pF VIN (6-27V) SC5014 VCC EN UVLO SCP REF FSET CPLL SCL SDA ISET PWM IO4 IO3 IO2 IO1 OVP CS PGND NDRV R4 C4 100pF C6Q1 C12 SDA R15 SCL PWM R12 VCC (5V) GND R11 Vout

10 WLEDs per channel

2.2µF 10kΩ PGND 10µF/35V x2PCS 4.7µF/50V x6PCS 1µF 24.3kΩ 80mΩ 357kΩ 10kΩ 25.5kΩ R7, 110kΩ 20kΩ 10kΩ R5, 40.2kΩ 100kΩ 10kΩ 4.7µH AON7244 B260 PAD Figure 3— Li-Ion Powered Display Application Circuit Example, 20 LED @ 20mA VIN (3-4.2V) S C 504 VCC EN UVLO SCP REF FSET NC SCL SDA ISET PWM IO4 IO3 IO2 IO1 OVP CS PGND NDRV C6Q1 C12 SDA R15 SCL PWM R12 VCC (5V) GND R11 Vout

5 WLEDs per channel

2.2µF/10V 10kΩ PGND 10µF/6.3V x2PCS 1µF 13kΩ 100mΩ 249kΩ 10kΩ 127kΩ 20kΩ 10kΩ R5, 60.4kΩ 100kΩ 10kΩ Si2318 B140 PAD RCS

2.7pF VIN (6-27V) S C504 VCC EN UVLO SCP REF FSET CPLL SCL SDA ISET PWM IO4 IO3 IO2 IO1 OVP CS PGND NDRV R4 C4 100pF C12 SDA R15 SCL PWM R12 VCC (5V) GND R11 Vout FLTFLT 2.2µF PGND 1µF R7, 110kΩ 20kΩ 10kΩ PAD RCS Figure 4— SEPIC Configuration 2.7pF VIN (12-19V) S C504 VCC EN UVLO SCP REF FSET CPLL SCL SDA ISET PWM IO4 IO3 IO2 IO1 OVP CS PGND NDRV R4 C4 100pF C6Q1 C12 SDA R15 SCL PWM R12 VCC (5V) GND R11 Vout up to 70V

20 WLEDs per channel

2.2µF 10kΩ PGND 10µF/25V x3PCS 2.2µF/100V x6PCS 1µF 75kΩ 50mΩ 787kΩ 10kΩ 25.5kΩ R7, 110kΩ 20kΩ 10kΩ R5, 40.2kΩ 250kΩ 10kΩ AON6482 DFLS1100 PAD VIN 3.3µH RCS Figure 5— Cascode Configuration drives 80 LEDs@100mA

acknowledges and the master terminates the transfer with the stop condition [P]. (2) Combined Format — Read After the start condition [S], the slave address is sent, fol - lowed by an eighth bit indicating a write. The SC504 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the 8-bit data from the previously addressed register; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. (3) Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC50 4 then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC50 4 with a read command. The device acknowledges this request and returns the data from the register location that had previously been set up. Serial Interface The I2C General Specification The SC50 4 is a read-write slave-mode I 2C device and complies with the NXP B.V. I2C standard Version 2., dated January 2000. The SC504 has user-accessible internal 8-bit registers. The I 2C interface has been designed for program flexibility, supporting direct format for write operation. Read operations are supported on both com - bined format and stop separated format. While there is no auto increment/decrement capability in the SC50 4 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. Limitations to the I2C Specifications The SC504 only recognizes 7-bit addressing. This means that 0-bit addressing and CBUS communication are not compatible. The device can operate in either standard mode (00kbit/s) or fast mode (400kbit/s). Slave Address Assignment The 7-bit slave address is 0 0 x. The eighth bit is the data direction bit. 0x5F is used for read operation and 0x5E is used for write operation. Supported Formats The supported formats are described in the following subsections. (1) Direct Format — Write The simplest format for an I2C write is direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC50 4 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again, the slave

Slave Address Register Address DataS W A A A P S – Start Condition W – Write = ‘0’ A – Acknowledge (sent by slave) P – Stop condition Slave Address – 7-bit Register address – 8-bit Data – 8-bit I2C Stop Separated Format Read Slave Address Register Address Slave Address B Data NACKS W A A S/Sr R A PP Slave AddressS Register Address Setup Access Master Addresses other Slaves Register Read Access S – Start Condition W – Write = ‘0’ R – Read = ‘1’ A – Acknowledge (sent by slave) NAK – Non-Acknowledge (sent by master) Sr – Repeated Start condition P – Stop condition Slave Address – 7-bit Register address – 8-bit Data – 8-bit I2C Combined Format Read Slave Address Register Address Slave Address Data NACKS W A A Sr R A P S – Start Condition W – Write = ‘0’ R – Read = ‘1’ A – Acknowledge (sent by slave) NAK – Non-Acknowledge (sent by master) Sr – Repeated Start condition P – Stop condition Slave Address – 7-bit Register address – 8-bit Data – 8-bit

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value Description 0x00 CLF PLL_RDY LED_ SHORT LED_ OPEN OTP OVP FAULT 0x00 Fault Status 0x0 WND WND0 FAST_ FREQ FLT_EN PHASE_ SHIFT INT_ DUTY INT_ PWM 0xB5 Device Control 0x02 IDAC4 IDAC3 IDAC2 IDAC IDAC0 0xF Analog Dimming Control 0x03 D9 D8 0x00 Dimming Duty Cycle Control 0x04 D7 D6 D5 D4 D3 D2 D D0 0x00 Dimming Duty Cycle Control 2 0x05 FREQ7 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ FREQ0 0x00 Dimming Frequency Select 0x06 NPLL7 NPLL6 0x00 PLL Divider MSB 0x07 NPLL5 NPLL4 NPLL3 NPLL2 NPLL NPLL0 NPLL9 NPLL8 0x00 PLL Divider LSB2 0x08 NPLL7 NPLL6 NPLL5 NPLL4 NPLL3 NPLL2 NPLL NPLL0 0x08 PLL Divider LSB 0x09 FADE_EN FADE_ TYPE STEP_ MUL2 STEP_ MUL STEP_ MUL0 0x80 Fade Options 0x0A FADE_ RATE6 FADE_ RATE5 FADE_ RATE4 FADE_ RATE3 FADE_ RATE2 FADE_ RATE FADE_ RATE0 0x00 Fade Rate

Definition of Registers and Bits Fault Status Register Bit Field Definition Read / Write Description 0x00 [7] CLF W Clear latching flags bit. (Set = to clear OTP , LED_OPEN, LED_SHORT and mask OVP for 32 to 64μs) 0x00 [6] PLL_RDY R PLL ready status 0x00 [5] LED_SHORT R One or more LED strings faulted shorted 0x00 [4] LED_OPEN R One or more LED strings faulted open 0x00 [2] OTP R Thermal shutdown ( = thermal OTP fault) 0x00 [] OVP R Output over-voltage fault ( = OVP ) 0x00 [0] FAULT R OR of all fault conditions (0= no fault, = fault condition)

Bit Field Definition Read / Write Description 0x0 [7:6] WIN[:0] R/W A modified duty cycle sent into the PWMI pin replaces the existing saved duty cycle when its deviation from the saved duty is outside the window for two consecutive samples. 00 = 0 bits (no window) 0 = ± bit window 0 = ±2 bit window = ±3 bit window 0x0 [5] FAST_FREQ R/W Determines the LED PWM dimming frequency selection: = High PWM dimming frequency mode assuming 9-bit PWM duty cycle dimming, dividing the system clock 0MHz / (52 x (FREQ+)). 0 = Low PWM dimming frequency mode assuming 0-bit PWM duty cycle dimming, dividing the system clock 0MHz / (024 x (FREQ+)). 0x0 [4] FLT_EN R/W This bit enables fault checking: 0 = LED_OPEN and LED_SHORT faults are not checked. = LED_OPEN and LED_SHORT faults are checked. 0x0 [2] PH_SHIFT R/W Enables String-by-String phase shifting. This is a don’t care if INT_PWM=0. 0 = Phase shifting disabled. = Phase shifting is enabled. 0x0 [] INT_DUTY R/W Determines the duty cycle source. This is a don’t care if INT_PWM = 0. 0 = LED duty cycle is set by the PWMI input. = LED duty cycle is set by the 0-bit duty cycle control registers. 0x0 [0] INT_PWM R/W Sets the LED PWM dimming source. 0 = LED PWM dimming driven directly from the PWMI input source (direct PWM dimming). = LED PWM dimming driven from an internal oscillator (required for phase-shifted PWM dimming); enables the PLL. Analog Dimming Control Register Bit Field Definition Read / Write Description 0x02 [4:0] IDAC [4:0] R / W 5-bit analog dimming register — The LED current can adjusted in 32 steps from 0mA to max value determined by RISET. Definition of Registers and Bits (continued)

Definition of Registers and Bits (continued) Dimming Duty Cycle Control Register Bit Field Definition Read / Write Description 0x03 [:0] 0x04 [7:0] D [9:0] R / W 0-bit PWM brightness setting — This value is spread over registers: 0x03 (MSB) and 0x04 (LSB). Dimming Frequency Select Register Bit Field Definition Read / Write Description 0x05 [7:0] FREQ [7:0] R / W This register sets the LED dimming frequency. FAST_FREQ = , then LED dimming frequency is equal to 0MHz / (52 x (FREQ+)). FAST_FREQ = 0, then LED dimming frequency is equal to 0MHz / (024 x (FREQ+)). PLL Control Registers Bit Field Definition Read / Write Description 0x06 [:0] 0x07 [7:0] 0x08 [7:0] NPLL [7:0] R / W These registers set the PLL divider value — The system clock is intended to run at 0MHz; this value divides the system clock down to a frequency comparable to the SYNC signal’s frequen- cy to allow PLL synchronization. Typical values are shown below. FIN PLL Divider N Register Values FPLL = (N+2) × FIN

60 Hz 69,982 0x02 - 0x97 - 0xFE 0MHz

MHz 8 0x00 - 0x00 - 0x08 0MHz Fade Options Registers Bit Field Definition Read / Write Description 0x09 [7] FADE_EN R/W Enables the fading feature. FADE_EN = 0: No Fading; Jumps directly to new PWM value. FADE_EN = : Enables fading. 0x09 [6] FADE_TYPE R/W Selects the fading type. FADE_TYPE = 0: Logarithmic Fading. FADE_TYPE = : Linear Fading.

Bit Field Definition Read / Write Description 0x09 [2:0] STEP_MUL [2:0] R/W Used to speed up fade time, when selected LED PWM dimming frequency is low. Define a 2N multiplier of the fade amount. STEP_MUL[2:0] = 000, N=0, multiplier = STEP_MUL[2:0] = 00, N=, multiplier = 2 = 2 STEP_MUL[2:0] = 00, N=2, multiplier = 22 = 4 STEP_MUL[2:0] = 0, N=3, multiplier = 23 = 8 STEP_MUL[2:0] = 00, N=4, multiplier = 24 = 6 STEP_MUL[2:0] = 0~, N=5, multiplier = 25 = 32 Fade Rate Register Bit Field Definition Read / Write Description 0x0A [6:0] FADE_RATE [6:0] R / W Defines how often the duty is changed during a fade. Fade rate = PWM Output Rate / ( + FADE_RATE[6:0]) Definition of Registers and Bits (continued)

e D/2 .001 MAX .002 .039 NOM 0.80 0.02 (0.20) 0.90 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. NOTES: N PIN 1 INDICATOR 4.103.90 4.00 4.103.90.157 .154 .161 .154 .161 aaa C A C (LASER MARK) D E B A SEATING PLANE LxN E/2 INCHES .020 BSC b .007 bbb aaa N E L e D .012 .100 DIM A MIN .000 .031 0.50 2.80 0.30 2.55 .004 .004 .016 .157 .106 .020 .110 0.10 0.10 0.40 4.00 2.70

0.50 BSC

0.05 1.00 DIMENSIONS MIN 0.00 NOM (.008) .035 Outline Drawing — MLPQ-20 4x4

Land Pattern — MLPQ-20 4x4 DIMENSIONS K H G Z X P (C) COMPANY'S MANUFACTURING GUIDELINES ARE MET. 4.80.189ZY FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FUNCTIONAL PERFORMANCE OF THE DEVICE. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P C G MILLIMETERSINCHES (3.95) .010 .033 .122 .020 .106 .106 (.156) 0.25 0.85 2.70 0.50 2.70 3.10

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