SC417

SC417 SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Input voltage — 3V to 28V Internal power MOSFETs — 10A Integrated bootstrap switch Smart power-save protection Confi gurable 150mA LDO with bypass capability TC compensated R DS(ON) sensed current limit Pseudo-fi xed frequency adaptive on-time control Designed for use with ceramic capacitors Programmable V IN UVLO threshold Independent enable for switcher and LDO Selectable ultra-sonic power-save (SC417) Selectable power-save (SC427) Internal soft-start and soft-shutdown at output Internal reference — 1% tolerance Over-voltage/under-voltage fault protection Power good output Lead-free 5x5mm, 32 Pin MLPQ package Fully WEEE and RoHS compliant

Applications

Notebook, desktop, tablet, and server computers Networking and telecommunication equipment Printers, DSL, and STB applications Embedded applications Power supply modules Point of load power supplies

Description

The SC417/SC427 is a stand-alone synchronous buck power supply. It features integrated power MOSFETs, a bootstrap switch, and a programmable LDO in a space- saving MLPQ-5x5mm 32-pin package. The device is highly effi cient and uses minimal PCB area. It uses pseudo-fi xed frequency adaptive on-time operation to provide fast transient response. The SC417/SC427 supports using standard capacitor types such as electrolytic or special polymer in addition to ceramic, at switching frequencies up to 1MHz. The pro- grammable frequency, synchronous operation, and select- able power-save provide high effi ciency operation over a wide load range. The LDO output is programmable from 0.75V to 5.25V using external resistors. The bias voltage for the device can be supplied by the on-chip LDO when V IN > 4.5V, or by an external 5V supply. When a separate source is used as the bias supply, the LDO can be programmed to provide a diff erent voltage. Additional features include cycle-by-cycle current limit, soft-start, under and over-voltage protection, program- mable over-current protection, soft shutdown, and select- able power-save. The device also provides separate enable inputs for the PWM controller and LDO as well as a power good output for the PWM controller. The input voltage can range from 3V to 28V. The wide input voltage range, programmable frequency, and pro- grammable LDO make the device extremely fl exible and easy to use in a broad range of applications. Support is provided for single cell or multi-cell battery systems in addition to traditional DC power supply applications. November 11, 2008 POWER MANAGEMENT

154KΩ SC417/SC427 FB1 FBL2 V5V3 AGND4 VOUT5 VIN6 VLDO7 BST8 VIN9 VIN10 VIN11 PGND15 PGND16 PGND 22 LX 23 LX 24 LX 25 PGOOD 26 ILIM 27LX 28EN/PSV 29 AGND 30 TON 31ENL 32 DL14 LX13 DH12 VINPAD 2 AGNDPAD 1 LX PAD 3 RILIM 7.5KΩ RLDO2 10KΩ RLDO1 56.2KΩ CIN 22μF RGND 100nF CBST 0.1μF VIN +12V Note: V5V is tied to VLDO PGND PGND PGND PGND PGND A separate 5V supply for the SC417/SC427 is not required if VLDO is used to power the device. 10nF CFF 100pF RFB1 11KΩ 0.88μH RFB2 10KΩ VOUT 1.05V @ 10A, 250kHz COUT1 220μF 15mΩ ENABLE/ PSAVE ENABLE LDO All other small signal components (resistors and capacitors) are standard SMT devices. Component Value Manufacturer Part Number Web CIN 22 μF/25V Murata GRM32ER61E226KE15L www.murata.com www.panasonic.comCOUT1, COUT2 220 μF/15mΩ/6.3V Panasonic EEFUE0J221R www.vishay.comL1 0.88 μH/20A Vishay IHLP4040DZERR88M11 Key Components +COUT2 15mΩ 220μF PGOOD 1μF Typical Application Circuit

Pin Confi guration Ordering Information Marking Information SC417 yyww. xxxxxx xxxxxx AGND PAD 1 VIN PAD 2 LX PAD 3 ENL TON AGND EN/PSV LX ILIM PGOOD LX 24 LX LX23 PGND22 PGND21 PGND20 PGND19 PGND18 PGND17 PGND PGND DL LX DH VIN VIN VIN BST 8 VOUT 5 VLDO 7 VIN 6 V5V 3 AGND 4 FBL 2 FB 1 Top View Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free packaging only. Device is WEEE and RoHS compliant. yyww. = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number MLPQ-32; 5x5, 32 LEAD SC427 yyww. xxxxxx xxxxxx yyww. = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number Device Package SC417MLTRT(1)(2) MLPQ-32 5X5 SC427MLTRT(1)(2) MLPQ-32 5X5 SC417EVB Evaluation Board SC427EVB Evaluation Board

Absolute Maximum Ratings(1) IN Recommended Operating Conditions Thermal Information Thermal resistance, junction to ambient (2) (°C/W) Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Unless specifi ed: V IN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, V5V = +5V, Typical Application Circuit

Electrical Characteristics

Parameter Conditions Min Typ Max Units Input Supplies Input Supply Voltage 32 8 V V5V Voltage 4.5 5.5 V VIN UVLO Threshold(1) Sensed at ENL pin, rising edge 2.40 2.60 2.95 V Sensed at ENL pin, falling edge 2.235 2.40 2.565 VIN UVLO Hysteresis EN/PSV = High 0.2 V V5V UVLO Threshold Measured at V5V pin, rising edge 3.7 3.9 4.1 V Measured at V5V pin, falling edge 3.5 3.6 3.75 V5V UVLO Hysteresis 0.3 V VIN Supply Current ENL , EN/PSV = 0V, VIN = 28V 8.5 20 μA Standby mode; ENL=V5V, EN/PSV = 0V 130

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) V5V Supply Current ENL , EN/PSV = 0V 3 7 μA SC417, EN/PSV = V5V, no load (fSW = 25kHz), VFB > 500mV(2) 2 mASC427, EN/PSV = V5V, no load, VFB > 500mV(2) 0.7 fSW = 250kHz, EN/PSV = fl oating , no load(2) 10 FB On-Time Threshold static VIN and load, 0 to +85 °C 0.496 0.500 0.504 V static VIN and load, -40 to +85 °C 0.495 0.505 V Frequency Range continuous mode operation 200 1000 kHz minimum fSW, (SC417 only), EN/PSV = V5V, no load 25 Bootstrap Switch Resistance 10 Ω Timing On-Time continuous mode operation, VIN = 15V, VOUT = 5V, fSW= 300kHz, RTON = 133kΩ 999 1110 1220 ns Minimum On-Time (2) 50 ns Minimum Off -Time (2) 250 ns Soft-Start Soft-Start Ramp Time (2) 850 μs Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero-Crossing Detector Threshold LX - PGND -3 0 +3 mV Power Good Power Good Threshold upper limit, V FB > internal 500mV reference +20 % lower limit, VFB < internal 500mV reference -10 % Start-Up Delay Time 2m s Fault (noise immunity) Delay Time(2) 5μ s Leakage 1μ A Power Good On-Resistance 10 Ω

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Fault Protection Valley Current Limit R ILIM = 5.9k Ω 6 8 10 A ILIM Source Current 10 μA ILIM Comparator Off set with respect to AGND -10 0 +10 mV Output Under-Voltage Fault VFB with respect to internal 500mV reference, 8 consecutive clocks -25 % Smart Power-save Protection Threshold (2) VFB with respect to internal 500mV reference +10 % Over-Voltage Protection Threshold V FB with respect to internal 500mV reference +20 % Over-Voltage Fault Delay(2) 5μ s Over-Temperature Shutdown(2) 10°C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage EN/PSV, ENL 2.0 V Logic Input Low Voltage EN/PSV, ENL 0.4 V EN/PSV Input Bias Current EN/PSV= V5V or AGND -10 +10 μA ENL Input Bias Current V IN = 28V 11 18 μA FBL, FB Input Bias Current FBL, FB = V5V or AGND -1 +1 μA Linear Regulator (LDO) FBL Accuracy VLDO load = 10mA 0.735 0.75 0.765 V LDO Current Limit Start-up and foldback, VIN = 12V 85 mA operating current limit, VIN = 12V 135 200 VLDO to VOUT Switch-over Threshold (3) -140 +140 mV VLDO to VOUT Non-switch-over Threshold (3) -450 +450 mV VLDO to VOUT Switch-over Resistance V OUT = +5V 2 Ω LDO Drop Out Voltage (4) from VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA 1.2 V Notes: (1) V IN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. (2) Guaranteed by design. (3) The switch-over threshold is the maximum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. (4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.

Effi ciency vs. Load — Forced Continuous Mode Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V 100 IOUT (A) Efficiency (%) 85% Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417). Effi ciency vs. Load — Powersave Mode 100 0.10 1.00 10.00 I OUT (A) Efficiency (%) Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V 85% VOUT vs. Load — Forced Continuous Mode Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V 1.000 1.025 1.050 1.075 1.100 IOUT (A) VOUT (V) +1% -1% Effi ciency vs. Load — Powersave Mode IOUT (A) Efficiency (%) Externally biased at VIN = 12V, V5V = 5V, VOUT = 1.050V 85% 100 0.10 1.00 10.00 Frequency vs. Load — Forced Continuous Mode Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V 100 150 200 250 300 350 400 IOUT (A) Freq (kHz) +15% -15% VRIPPLE vs. Load — Forced Continuous Mode Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V 0.00 0.05 0.10 0.15 0.20 I OUT (A) VRIPPLE (VP-P) 50mV VOUTP-P

Typical Characteristics (continued) VOUT vs. Load — Powersave Mode 1.000 1.025 1.050 1.075 1.100 0.10 1.00 10.00 Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V IOUT (A) VOUT (V) +1% -1% Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417). VOUT vs. Line — Forced Continuous Mode 1.000 1.025 1.050 1.075 1.100 VIN (V) Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1.050V VOUT (V) +1% -1% Ultrasonic Powersave Mode — No Load Time (10μs/div) (50mV/div) (10V/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V 1.073V Δ V ~ 29mV 1.044V f=26.22kHz Forced Continuous Mode — No Load Time (2μs/div) (50mV/div) (10V/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV= fl oat 1.078V Δ V ~ 30mV 1.048V f=227.4kHz Time (100μs/div) Enabled Loaded Output — Full Scale (50mV/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V 1.05V ΔV/ΔT ~ 1.4V/ms Enabled Loaded Output — Power Good True (500mV/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V Time (400μs/div) 1.05V ~2ms

Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417). Transient Response — Load Rising Time (10μs/div) (50mV/div) (10A/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A to 10A, VLDO = V5V = EN/PSV= ENL = 5V 1.063V 1.025V Output Over-current Response — Normal Operation Time (100μs/div) (500mV/div) (10V/div) (10A/div) (5V/div) VIN = 12V, VOUT = 1.05V, VLDO = V5V = ENL = 5V, EN/PSV= fl oating; IOUT ramped to trip point 1.05V IOUT = 10.37A Output Under-voltage Response — Normal Operation Time (100μs/div) (500mV/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, fl oating EN/PSV V2~710mV Transient Response — Load Falling Time (10μs/div) (50mV/div) (10A/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 10A to 0A, VLDO = V5V = EN/PSV= ENL = 5V 1.101V 1.055V Time (400μs/div) Self-Biased Start-Up — Power Good True (10V/div) (2V/div) (5V/div) VIN = 0V to 12V step, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V 1.05V ΔV/ΔT ~

1.4 V/ms

(500mV/div)

Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2. Shorted Output Response — Normal Operation Time (40μs/div) (500mV/div) (10V/div) (10A/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V 1.05V Shorted Output Response — Power-UP Operation Time (400μs/div) (500mV/div) (10V/div) (10A/div) (5V/div) VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V ~1.7ms

Pin # Pin Name Pin Function 1F B Feedback input for switching regulator used to program the output voltage — connect to an external resis- tor divider from VOUT to AGND. 2 FBL Feedback input for the LDO — connect to an external resistor divider from VLDO to AGND — used to pro- gram the LDO output. 3 V5V 5V power input for internal analog circuits and gate drives — connect to external 5V supply or confi gure the LDO for 5V and connect to VLDO. 4, 30, PAD 1 AGND Analog ground 5 VOUT Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO. 6, 9-11, PAD 2 VIN Input supply voltage

7 VLDO LDO output

8 BST Bootstrap pin — connect a capacitor from BST to LX to develop the fl oating supply for the high-side gate drive.

12 DH High-side gate drive — do not connect this pin

13, 23-25, 28, PAD 3 LX Switching (phase) node

14 DL Low-side gate drive — do not connect this pin

26 PGOOD Open-drain power good indicator — high impedance indicates power is good. An external pull-up resistor is required. 27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX.

29 EN/PSV

Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator. Float to operate in forced continuous mode (power-save disabled). SC417 — connect to V5V to operate with ultra-sonic power-save mode enabled. SC427 — connect to V5V to operate with power-save mode enabled with no minimum frequency.

31 TON On-time programming input — set the on-time by connecting through a resistor to AGND

32 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con- trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.

Control & Status PGOOD Gate Drive Control VIN PGNDTON VOUT Zero Cross Detector Valley Current Limit ILIM ENL FBL VLDO Switchover MUX A Y B LDO VLDO BST FB Comparator V5V LX EN/PSV Bypass ComparatorBypass Comparator DL DH DL A 3 26 29 A = connected to pins 6, 9-11, PAD 2 B = connected to pins 13, 23-25, 28, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 B C D VIN V5V V5V V5V VIN Bootstrap Switch Lo-side MOSFET Hi-side MOSFET

Figure 8 — Valley Current Limit Setting the valley current limit to 10A results in a peak inductor current of 10A plus peak ripple current. In this situation, the average (load) current through the inductor is 10A plus one-half the peak-to-peak ripple current. The internal 10μA current source is temperature compen- sated at 4100ppm in order to provide tracking with the RDS (ON). The RILIM value is calculated by the following equation. R ILIM = 735 x ILIM Note that because the low-side MOSFET with low RDS (ON) is used for current sensing, the PCB layout, solder connec- tions, and PCB connection to the LX node must be done carefully to obtain good results. Refer to the layout guide- lines for information. Soft-Start of PWM Regulator Soft-start is achieved in the PWM regulator by using an internal voltage ramp as the reference for the FB Comparator. The voltage ramp is generated using an internal charge pump which drives the reference from zero to 500mV in ~1.2mV increments, using an internal ~500kHz oscillator. When the ramp voltage reaches 500mV, the ramp is ignored and the FB comparator switches over to a fi xed 500mV threshold. During soft-start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft- start profi le for a wide range of applications. Typical soft- start ramp time is 850μs. During soft-start the regulator turns off the low-side MOSFET on any cycle if the inductor current falls to zero. This prevents negative inductor current, allowing the device to start into a pre-biased output. Power Good Output The power good (PGOOD) output is an open-drain output which requires a pull-up resistor. When the output voltage is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns above -8% of nominal. PGOOD is held low during start-up and will not be allowed to transition high until soft-start is completed (when V FB reaches 500mV) and typically 2ms has passed. PGOOD will transition low if the V FB pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh- old (600mV). PGOOD also pulls low if the EN/PSV pin is low when V5V is present. Output Over-Voltage Protection Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 500mV + 20% (600mV). When V FB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off , until the EN/PSV input is toggled or V5V is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls 25% below its nominal voltage (falls to 375mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tri- state the MOSFETs. The controller stays off until EN/PSV is toggled or V5V is cycled. V5V UVLO, and POR Under-Voltage Lock-Out (UVLO) circuitry inhibits switch- ing and tri-states the DH/DL drivers until V5V rises above 3.9V. An internal Power-On Reset (POR) occurs when V5V exceeds 3.9V, which resets the fault latch and soft-start counter to prepare for soft-start. The SC417/SC427 then begins a soft-start cycle. The PWM will shut off if V5V falls below 3.6V. LDO Regulator The device features an integrated LDO regulator with a programmable output voltage from 0.75V to 5.25V using Applications Information (continued)

Switch-over Limitations on VOUT and VLDO Because the internal switch-over circuit always compares the VOUT and VLDO pins at start-up, there are limitations on permissible combinations of VOUT and VLDO. Consider the case where VOUT is programmed to 1.5V and VLDO is programmed to 1.8V. After start-up, the device would connect VOUT to VLDO and disable the LDO, since the two voltage are within the ±300mV switch-over window. To avoid unwanted switch-over, the minimum difference between the voltages for VOUT and VLDO should be ±500mV. It is not recommended to use the switch-over feature for an output voltage less than 3V since this does not provide suffi cient voltage for the gate-source drive to the internal p-channel switch-over MOSFET. Switch-over MOSFET Parasitic Diodes The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in Figure 11. Switchover MOSFET Parasitic diode Parasitic diode V5V VLDO VOUT Switchover control Figure 11— Switch-over MOSFET Parasitic Diodes There are some important design rules that must be fol- lowed to prevent forward bias of these diodes. The fol- lowing two conditions need to be satisfi ed in order for the parasitic diodes to stay off . V5V ≥ V LDO V5V ≥ VOUT If either VLDO or VOUT is higher than V5V, then the respective diode will turn on and the SC417/SC427 operating current will flow through this diode. This has the potential of damaging the device. ENL pin and VIN UVLO The ENL pin also acts as the switcher under-voltage lockout for the V IN supply. The V IN UVLO voltage is pro- grammable via a resistor divider at the VIN, ENL and AGND pins. ENL is the enable/disable signal for the LDO. In order to implement the VIN UVLO there is also a timing require- ment that needs to be satisfi ed. If the ENL pin transitions low within 2 switching cycles and is < 1V, then the LDO will turn off but the switcher remains on. If ENL goes below the VIN UVLO threshold and stays above 1V, then the switcher will turn off but the LDO remains on. The VIN UVLO function has a typical threshold of 2.6V on the VIN rising edge. The falling edge threshold is 2.4V. Note that it is possible to operate the switcher with the LDO disabled, but the ENL pin must be below the logic low threshold (0.4V maximum). ENL Logic Control of PWM Operation When the ENL input is driven above 2.6V, it is impossible to determine if the LDO output is going to be used to power the device or not. In self-powered operation where the LDO will power the device, it is necessary during the LDO start-up to hold the PWM switching off until the LDO has reached 90% of the fi nal value. This is to prevent over- loading the current-limited LDO output during the LDO start-up. However, if the switcher was previously operat- ing (with EN/PSV high but ENL at ground, and V5V sup- plied externally), then it is undesirable to shut down the switcher. To prevent this, when the ENL input is taken above 2.6V (above the VIN UVLO threshold), the internal logic checks the PGOOD signal. If PGOOD is high, then the switcher is already running and the LDO will run through the start-up cycle without aff ecting the switcher. If PGOOD is low, then the LDO will not allow any PWM switching until the LDO output has reached 90% of it’s fi nal value. Applications Information (continued)

Applications Information (continued) Using the On-chip LDO to Bias the SC417/SC427 The following steps must be followed when using the on- chip LDO to bias the device. Connect V5V to VLDO before enabling the LDO. The LDO has an initial current limit of 40mA at start-up, therefore, do not connect any external load to VLDO during start-up. When VLDO reaches 90% of its fi nal value, the LDO current limit increases to 200mA. At this time the LDO may be used to supply the required bias current to the device. Attempting to operate in self-powered mode in any other confi guration can cause unpredictable results and may damage the device. Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifi ed. The maximum input voltage (V INMAX) is the highest speci- fi ed input voltage. The minimum input voltage ( V INMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters defi ne the design. Nominal output voltage (V OUT) Static or DC output tolerance Transient response Maximum load current (I OUT) There are two values of load current to evaluate — con- tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and fi ltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. V IN = 12V + 10% VOUT = 1.05V + 4% fSW = 250kHz Load = 10A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external fi lter components (inductor and output capacitor) and the power conversion effi ciency. The desired switching frequency is 250kHz which results from using component selected for optimum size and cost . A resistor (R TON) is used to program the on-time (indirectly setting the frequency) using the following equation. OUT INON TON VpF25 V)ns10T(R u u To select RTON, use the maximum value for V IN, and for TON use the value associated with maximum VIN. SWINMAX OUT ON fV VT u T ON = 318 ns at 13.2VIN, 1.05VOUT, 250kHz Substituting for RTON results in the following solution. R TON = 154.9kΩ, use RTON = 154kΩ Inductor Selection In order to determine the inductance, the ripple current must fi rst be defi ned. Low inductor values result in smaller size but create higher ripple current which can reduce effi ciency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more effi cient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and effi ciency are all used in the selection process. The ripple current will also set the boundary for power- save operation. The switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then Power-save operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current.

Applications Information (continued) The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, effi ciency, and transient performance. During the DH on-time, voltage across the inductor is (V IN - VOUT). The equation for determining inductance is shown next. RIPPLE ONOUTIN I T)VV(L u Example In this example, the inductor ripple current is set equal to 50% of the maximum load current. Thus ripple current will be 50% x 10A or 5A. To fi nd the minimum inductance needed, use the V IN and T ON values that correspond to VINMAX. H77.0A5 ns318)05.12.13(L P u A slightly larger value of 0.88μH is selected. This will decrease the maximum I RIPPLE to 4.4A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. ns384ns10V VRpF25T INMIN OUTTON VINMIN_ON uu L T)VV(I ONOUTIN RIPPLE u A25.4H88.0 ns384)05.18.10(I VIN_RIPPLE P u Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is con- trolled by the output ripple requirement and the DC toler- ance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is that the output voltage regulation be ±4% under static conditions. The internal 500mV refer- ence tolerance is 1%. Allowing 1% tolerance from the FB resistor divider, this allows 2% tolerance due to V OUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 42mV for a 1.05V output. The maximum ripple current of 4.4A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. A4.4 mV42 I VESR RIPPLEMAX RIPPLE MAX ESR MAX = 9.5 mΩ The output capacitance is usually chosen to meet tran- sient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1μs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. OUT PEAK RIPPLEMAXOUT MIN VV 1IL COUT § u Assuming a peak voltage VPEAK of 1.150 (100mV rise upon load release), and a 10A load release, the required capaci- tance is shown by the next equation. MIN 05.115.1 4.42 110H88.0 COUT § uP COUT MIN = 595μF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 500mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately OUT. This causes a down-slope or falling di/dt in the

Applications Information (continued) inductor. If the load di/dt is not much faster than the -di/ dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capaci- tance for a given dI LOAD/dt: Peak inductor current is shown by the next equation. I LPK = IMAX + 1/2 x IRIPPLEMAX I LPK = 10 + 1/2 x 4.4 = 12.2A dt dlCurrentLoadofchangeofRate LOAD I MAX = maximum load release = 10A OUTPK LOAD MAX OUT LPK LPKOUT VV2 dtdl I V IL IC uu u Example s A5.2 dt dlLoad LOAD P This would cause the output current to move from 10A to zero in 4μs as shown by the following equation. 05.115.12 s15.2 05.1 2.12H88.0 2.12COUT PuuP u C OUT = 379 μF Note that C OUT is much smaller in this example, 379μF compared to 595μF based on a worst-case load release. To meet the two design criteria of minimum 379μF and maximum 9mΩ ESR, select two capacitors rated at 220μF and 15mΩ ESR. It is recommended that an additional small capacitor be placed in parallel with C OUT in order to fi lter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250ns minimum off -time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not aff ect opera- tion. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also impera- tive to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis- tor, as shown in Figure 13. This capacitor should be left unpopulated until it can be confi rmed that double-pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional con- nection on the PCB should be available for this capacitor. VOUT To FB pin CTOP Figure 13 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking sta- bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased.

Applications Information (continued) One simple way to solve this problem is to add trace resis- tance in the high current output path. A side eff ect of adding trace resistance is output decreased load regulation. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insuffi - cient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis- charging during the switching cycle. For most applica- tions the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre- quency. The formula for minimum ESR is shown by the following equation. swOUT MIN fC2 3SRE uuSu For applications using ceramic output capacitors, the ESR is normally too small to meet the above ESR criteria. In these applications it is necessary to add a small virtual ESR network composed of two capacitors and one resistor, as shown in Figure 14. This network creates a ramp voltage across C L, analogous to the ramp voltage generated across the ESR of a standard capacitor. This ramp is then capaci- tively coupled into the FB pin via capacitor C R2FB pin CC COUT L Low- side High- side CLRL Figure 14 — Virtual ESR Ramp Current Dropout Performance The output voltage adjust range for continuous-conduc- tion operation is limited by the fixed 250ns (typical) minimum off -time of the one-shot. When working with low input voltages, the duty-factor limit must be calcu- lated using worst-case values for on and off times. The duty-factor limitation is shown by the next equation. )MAX(OFF)MIN(ON )MIN(ON TT TDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (VOUT Controller) Three factors aff ect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator off set is trimmed so that under static condi- tions it trips when the feedback pin is 500mV, 1%. The on-time pulse from the SC417/SC427 in the design example is calculated to give a pseudo-fi xed frequency of

Applications Information (continued) 250kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with V IN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with V IN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this eff ect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors contributes up to 1% error. If tighter DC accuracy is required, 0.1% resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor eff ect on the DC output voltage. The output ESR also aff ects the output ripple and thus has a minor eff ect on the DC output voltage. Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fi xed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net eff ect is that frequency tends to falls slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the induc- tor. For a conventional PWM constant-frequency con- verter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V IN as losses increase). The on-time is essen- tially constant for a given V OUT/VIN combination, to off set the losses the off -time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load.

current handling (including the chip power ground con- nections). Power components should be placed to mini- mize current loops and reduce losses. Make all the power connections on one side of the PCB using wide copper areas if possible. Do not use minimum land patterns for power components. Current Limit Obtaining an accurate current limit for the SC417/SC427 requires careful PCB layout. The device uses the RDS (ON) of the low-side MOSFET for current sensing. The ILIM com- parator that performs the current limit function monitors the ILIM pin with respect to AGND, but the low-side MOSFET is internally connected to PGND. The PCB layout needs to following these guidelines. AGND and PGND must be connected together directly at the pins of the IC and not anywhere else. This can be done through PCB copper or a zero ohm resistor. Keep the traces short and direct. The preferred connection for PGND is at pin 19. The preferred connection for AGND is at the PAD1. The PGND path from the device to the input and output capacitors requires a wide copper areas. Use multiple vias and copper areas if available. Do not break up these copper areas with inter- vening components. The goal is to minimize the IR drop between all PGND connections. Provide multiple vias and multiple copper areas between the LX pins and the inductor. The goal is to minimize any IR drop that might contrib- uted to the RDS (ON). This is also good to carry heat away from the device. For the connection from the RLIM resistor to the LX node, use a direct Kelvin connection to pin 28 (LX), as near to the pin as possible. Do not connect to a place further in the copper between the LX pins and the inductor — the intervening copper will appear as increased RDS (ON) and will reduce the operating current limit. The layout can be considered in two parts; the control section referenced to AGND, and the switcher power section referenced to GND. Control Section Locate all components referenced to AGND on the sche- matic and place these components near the device and on the same side if possible. Connect AGND to the AGND pad and pins using a plane or island if possible. The device supply decoupling capacitor (V5V to PGND) should be located as close as possible to the pins. The V5V decoupling capacitor preferred placement is on the oppo- site side of the PCB. It should be routed with traces as short as possible, using at least two vias when connecting through the PCB. There are two sensitive feedback-related pins at the device — VOUT and FB. Proper routing is essential to keep noise away from these signals. All components connected to FB should be located directly at the chip, and the copper area of the FB node must be minimized. The VOUT trace that feeds into the VOUT pin, which also feeds the FB resistor divider, must be kept as far away as possible from noise sources such as all switching signals (LX, DH, DL, BST) and the inductor. Route the VOUT trace in a quiet layer if pos- sible, from the output capacitor back to the chip. Power Section The switcher power section key guidelines are as follows. There should be a very small input loop between the input capacitors, inductor, and output capacitors. Locate the input decoupling capaci- tors directly at the VIN pad on the device. The LX phase node should be a large enough to carry the required current. Careful sizing is required since this is the noisiest node. The PGND connection between the input capaci- tors, low-side MOSFET, and output capacitors should be as small as possible, with wide traces or planes and multiple vias. The impedance of the PGND connection between the low-side MOSFET and the PGND pin should be minimized. This connection must carry the DL drive current, which has high peaks at both rising and falling edges. Use multiple layers and multiple vias to minimize impedance and keep the distance as short as practical. Applications Information (continued)

Applications Information (continued) Connect the control and switcher power sections as follows. Route the V OUT feedback trace in a quiet layer, away from noise sources. BST is a noisy node and should be kept as short as possible. The high-side DH driver uses the boost capacitor to provide the DH drive current. The boost capacitor must be placed near the device and connected to the BST and LX pins using short, wide traces to minimize impedance. Connect the PGND pin on the chip to the V5V decoupling capacitor and then insert vias directly to the ground plane. LDO Section There are three components for the LDO that need to be optimized for this layout, the two feedback resistors and the output capacitor. Use the following guidelines to locate these components. The feedback resistors should be placed as close to the FBL pin as possible. This minimizes the trace length for the FBL pin. For the feedback divider connection, the top resistor must connect directly to the LDO output capacitor. There should be no PCB inductance between the top of the resistor divider and the LDO output capacitor. If VLDO is not used to power the device, then a minimum 1.0 μF capacitor referenced to AGND is required. If VLDO is used to power-up the device by con- necting it to V5V, then the LDO output capacitor also becomes the decoupling capacitor for the V5V input. A minimum 0.1μF capacitor refer- enced to AGND is required along with a minimum 1.0μF capacitor referenced to PGND to filter the gate drive pulses. Each capacitor should be placed near the V5V pin and con- nected with short, direct traces. Each capacitor should connect directly to its respective ground.

Outline Drawing — MLPQ-5x5-32 B aaa C C SEATING PLANE N bbb C A B COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: A PIN 1 INDICATOR (LASER MARK) D E bxN A e LxN 0.76 0.76 3.48 1.05 1.66 1.49 PIN 1 IDENTIFICATION R0.20 3.61 MILLIMETERS

0.50 BSC

.002- 0.00.000A1 .193 .193 .135 .076 .012 .007 aaa bbb N e L D E b .020 BSC .137 .016 .003 .004 .197 (.008) .078 .197 .010 3.43.139 .020 0.30 .201 .201 .080 .012 4.90 4.90 1.92 0.18 .031 MINDIM A MAX DIMENSIONS INCHES NOM .039 0.80 MIN - 0.05 5.10 5.10 3.53 2.02 0.50 0.30 3.48 0.40 0.10 0.08 5.00 (0.20) 1.97 5.00 0.25 1.00 MAX NOM

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Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com Land Pattern — MLPQ-5x5-32 1.74 3.48 K 3.61 Y H(C) G THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P C G MILLIMETERSINCHES (4.95) .012 .030 .165 .020 .078 .137 (.195) 0.30 0.75 3.48 0.50 1.97 4.20 DIMENSIONS COMPANY'S MANUFACTURING GUIDELINES ARE MET. 5.70.224Z FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD3. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. X P Z H1 .059 1.49 H2 .065 1.66 K1 .041 1.05 1.74