SC414 SEMTECH | Alldatasheet
Document overview
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Technical content
Features
Input voltage — 3V to 28V Internal power MOSFETs — 6A Integrated bootstrap switch Smart power-save protection Integrated 5V, 150mA LDO with bypass capability TC compensated R DS(ON) sensed current limit Pseudo-fi xed frequency adaptive on-time control Designed for use with ceramic capacitors Programmable V IN UVLO threshold Independent enable for switcher and LDO Selectable ultrasonic power-save (SC414) Selectable power-save (SC424) Internal soft-start and soft-shutdown at output Internal reference — 1% tolerance Over-voltage and under-voltage fault protection Power good output SmartDrive TM Lead-free 4x4mm, 28 Pin MLPQ package Fully WEEE and RoHS compliant, and halogen free
Applications
Notebook, desktop, tablet, and server computers Networking and telecommunication equipment Printers, DSL, and STB applications Embedded applications Power supply modules Point of load power supplies
Description
The SC414/SC424 is a stand-alone synchronous buck regu- lated power supply. It features integrated power MOSFETs, a bootstrap switch, and a 5V LDO in a space-saving MLPQ- 4x4mm 28-pin package. The device is highly effi cient and uses minimal PCB area. It uses pseudo-fi xed frequency adaptive on-time operation to provide fast transient response. The SC414/SC424 supports using standard capacitor types such as electrolytic or special polymer, in addition to ceramic, at switching frequencies up to 1MHz. The pro- grammable frequency, synchronous operation, and select- able power-save provide high effi ciency operation over a wide load range. Additional features include cycle-by-cycle current limit, soft-start, under and over-voltage protection, program- mable over-current protection, soft shutdown, and select- able power-save. The device also provides separate enable inputs for the PWM controller and LDO as well as a power good output for the PWM controller. The input voltage can range from 3V to 28V. The wide input voltage range, programmable frequency, and 5V LDO make the device extremely fl exible and easy to use in a broad range of applications. It can be used for single cell or multi-cell battery systems in addition to traditional DC power supply applications. The 5V LDO or an external 3.3V to 5V supply can be used to provide the bias voltage for the SC414/SC424. When the SC414/SC424 is used as a 5V output switching regula- tor, the 5V LDO can be used as an initial bias supply for the device. Once the switch regulator output is in the switch over range, the LDO will be bypassed by the switcher output for optimum effi ciency. September 11, 2009 POWER MANAGEMENT
9.09KΩ RFB1 10KΩ 100nF +12V ENABLE LDO RTON 154KΩ +COUT 220μF 10nF RFB2 30KΩ C1 C2 1μF 1V @ 6A, 250kHz VIN VOUT RPGOOD 10KΩ V5V CBST 1μF All other small signal components (resistors and capacitors) are standard SMT devices. Component Value Manufacturer Part Number Web CIN 10 μF/25V Murata GRM32DR71E106KA12L www.murata.com www.panasonic.comCOUT 220 μF/15mΩ/6.3V Panasonic EEFUE0J221R www.vishay.comL1 1.5 μH/9A Vishay IHLP2525CZER1R5M01 Key Components SC414/SC424 VOUT V5V 1.5μH FB FB VOUT 1μF CIN 10μF CIN 10μF Typical Application Circuit
Pin Confi guration Ordering Information Marking Information SC414 yyww xxxxx xxxxx EN/PSV PGOOD AGND PAD 1 LX PAD 3 BST 7 VOUT 4 VLDO 6 VIN 5 V5V 2 AGND 3 FB 1 Top View LX15 PGND18 PGND16 PGND17 LX20 PGND19 LX21 VIN VIN 109 11 12 13 14 VIN VIN LXBST PGND PGND 28 2627 25 24 23 22 ENL TON AGND LXS ILIM VIN PAD 2 Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. yyww = Date Code xxxxx = Semtech Lot Number SC414 and SC424 MLPQ-28; 4x4, 28 LEAD SC424 yyww xxxxx xxxxx yyww = Date Code xxxxx = Semtech Lot Number Device Package SC414MLTRT(1)(2) MLPQ-28 4x4 SC424MLTRT(1)(2) MLPQ-28 4x4 SC414EVB Evaluation Board SC424EVB Evaluation Board
Recommended Operating Conditions Thermal Information Thermal resistance, junction to ambient (2) (°C/W) Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Unless specifi ed: V IN =12V, TA = +25°C for Typical, -40 to +85 °C for Min. and Max., TJ < 125°C, V5V = +5V, Typical Application Circuit
Electrical Characteristics
Parameter Conditions Min Typ Max Units Input Supplies VIN UVLO Threshold(1) (not available for V5V < 4.5V) Sensed at ENL pin, rising edge 2.40 2.60 2.95 V Sensed at ENL pin, falling edge 2.235 2.40 2.565 VIN UVLO Hysteresis EN/PSV = High 0.2 V V5V UVLO Threshold Measured at V5V pin, rising edge 2.50 2.9 3.0 V Measured at V5V pin, falling edge 2.40 2.7 2.90 V5V UVLO Hysteresis 0.2 V VIN Supply Current ENL, EN/PSV = 0V, VIN = 28V 8.5 20 μA Standby mode; ENL=V5V, EN/PSV = 0V 130
Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) V5V Supply Current ENL, EN/PSV = 0V , V5V = 5V 3 7 μA ENL, EN/PSV = 0V , V5V = 3V 2 SC414, EN/PSV = V5V, no load (fSW = 25kHz), VFB > 750mV(2) 1 mASC424, EN/PSV = V5V, no load, VFB > 750mV(2) 0.4 V5V = 5V, fSW = 250kHz, EN/PSV = fl oating, no load(2) 4 V5V = 3V, fSW = 250kHz, EN/PSV = fl oating, no load(2) 2.5 FB Comparator Threshold Static VIN and load, 0 to +85 °C, V5V = 3V or 5V 0.744 0.750 0.756 V Static VIN and load, -40 to +85 °C, V5V = 3V or 5V 0.7425 0.7575 V Frequency Range Continuous mode operation 1000 kHz Minimum fSW , (SC414 only), EN/PSV = V5V, no load 25 Bootstrap Switch Resistance 10 Ω Timing On-Time Continuous mode operation, VIN = 15V, VOUT = 3V, RTON = 300kΩ 1350 1500 1650 ns V5V < 4.5V(3) Minimum On-Time (2) 80 ns Minimum Off -Time (2) V5V = 5V 320 ns V5V = 3V 390 Soft-Start Soft-Start Ramp Time (2) 1.7 ms Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero-Crossing Detector Threshold LX - PGND, V5V = 3V or 5V -3 0 +3 mV
Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Power Good Power Good Threshold Upper limit, VFB > internal 750mV reference +20 % Lower limit, VFB < internal 750mV reference -10 % Start-Up Delay Time (Time between EN going high and PGOOD going high) V5V = 3V 2 ms V5V = 5V 4 Fault (noise immunity) Delay Time(2) 5μ s Leakage 1μ A Power Good On-Resistance 10 Ω Fault Protection Valley Current Limit V5V = 5V, R ILIM = 5k Ω 3 4 5 A Valley Current Limit V5V = 3V, R ILIM = 5k Ω 3.4 A ILIM Source Current 8μ A ILIM Comparator Off set With respect to AGND -8 0 +8 mV Output Under-Voltage Fault VFB with respect to internal 750mV reference, 8 consecutive clock cycles -25 % Smart Power-save Protection Threshold (2) VFB with respect to internal 750mV reference +10 % Over-Voltage Protection Threshold V FB with respect to internal 750mV reference +20 % Over-Voltage Fault Delay(2) 5μ s Over-Temperature Shutdown(2) 10°C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage ENL 1 V Logic Input Low Voltage ENL 0.4 V EN/PSV Input for PSAVE Operation (2) % of V5V 45 100 % EN/PSV Input for Forced Continuous Operation (2) % of V5V 1V 42 % EN/PSV Input for Disabling Switcher (2) 0 0.4 V EN/PSV Input Bias Current EN/PSV= V5V or AGND -10 +10 μA ENL Input Bias Current V IN = 28V 11 18 μA FB Input Bias Current FB = V5V or AGND -1 +1 μA
Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Linear Regulator — LDO (not available for V5V < 5V) VLDO Accuracy VLDO load = 10mA 4.9 5.0 5.1 V LDO Current Limit Start-up and foldback, VIN = 12V 85 mA Operating current limit, VIN = 12V 135 200 VLDO to VOUT Switch-over Threshold (4) -140 +140 mV VLDO to VOUT Non-switch-over Threshold (4) -450 +450 mV VLDO to VOUT Switch-over Resistance V OUT = +5V 2 Ω LDO Drop Out Voltage (5) From VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA 1.2 V Notes: (1) V IN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. (2) Guaranteed by design. (3) For V5V less than 4.5V, the On-Time may be limited by the V5V supply voltage and by V IN. See the TON Limitations and V5V Supply Voltage section in the applications Information. (4) The switch-over threshold is the maximum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. (5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point. Thermal resistance, junction to ambient — guaranteed by design (°C/W)
Effi ciency vs. Load — Forced Continuous Mode IOUT (A) Efficiency (%) 100 0.001 0.01 0.1 1 10 Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Effi ciency vs. Load — Powersave Mode (SC414) IOUT (A) Efficiency (%) 100 0.001 0.01 0.1 1 10 VOUT vs. Load — Forced Continuous Mode IOUT (A) Output Voltage (V) 0.95 0.97 0.99 1.01 1.03 1.05 0.001 0.01 0.1 1 10 Effi ciency vs. Load — Powersave Mode (SC414) IOUT (A) Efficiency (%) 100 0.001 0.01 0.1 11 0 5V Bias 3V Bias Effi ciency vs. Load — Powersave Mode (SC424) Effi ciency vs. Load — Powersave Mode (SC424) IOUT (A) Efficiency (%) 100 0.001 0.01 0.1 11 0 5V Bias 3V Bias IOUT (A) Efficiency (%) 100 0.001 0.01 0.1 1 10 Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Externally biased, VIN = 12V, VOUT = 1V Externally biased, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Typical Characteristics (continued) VOUT vs. Load — Powersave Mode (SC414) IOUT (A) VOUT (V) 0.95 0.97 0.99 1.01 1.03 1.05 0.001 0.01 0.1 1 10 Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Frequency vs. Load — Forced Continuous Mode Frequency (kHz) 100 150 200 250 300 350 400 0.001 0.01 0.1 1 10 I OUT (A) VRIPPLE vs. Load — Forced Continuous Mode IOUT (A) VRIPPLE (mVP_P) 100 0.001 0.01 0.1 1 10 VOUT vs. Load — Powersave Mode (SC424) IOUT (A) VOUT(V) 0.95 0.97 0.99 1.01 1.03 1.05 0.001 0.01 0.1 1 10 Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V VOUT vs. Line — Forced Continuous Mode Input Voltage (V) Output Voltage (V) 0A 1.5A 0.95 0.97 0.99 1.01 1.03 1.05 57 9 11 13 15 17 19 21 Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V VOUT vs. Line — Forced Continuous Mode Input Voltage (V) VRIPPLE (mVP_P) 100 5 7 9 1 11 31 51 71 9 2 1 6A3A 1.5A 0A Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Ultrasonic Powersave Mode — No Load (SC414) Time (10μs/div) (50mV/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V Forced Continuous Mode — No Load Time (2μs/div) (50mV/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV= fl oat Enabled Loaded Output — Power Good True (500mV/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V Time (1ms/div) Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Powersave Mode — No Load (SC424) Time (10ms/div) (50mV/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V Time (10ms/div) Self-Biased Start-Up — Power Good True (500mV/div) (10V/div) (5V/div) VIN = 0V to 12V step, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V (2V/div) Output Over-current Response — Normal Operation Time (100μs/div) (500mV/div) (5V/div) (5V/div) (5A/div) VIN = 12V, VOUT = 1V, VLDO = V5V = ENL = 5V, EN/PSV= fl oating; IOUT ramped to trip point
Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424). Transient Response — Load Rising (SC414) Time (10μs/div) (50mV/div) (5A/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 200mA to 6A, VLDO = V5V = EN/PSV= ENL = 5V Transient Response — Load Falling (SC414) Time (10μs/div) (50mV/div) (5A/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V Transient Response — Load Rising (SC424) Time (10μs/div) (50mV/div) (5A/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A to 6A, VLDO = V5V = EN/PSV= ENL = 5V Transient Response — Load Falling (SC424) Time (10μs/div) (50mV/div) (5A/div) (10V/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V Shorted Output Response — Normal Operation Time (40μs/div) (500mV/div) (10V/div) (5A/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V Shorted Output Response — Power-UP Operation Time (1ms/div) (500mV/div) (10V/div) (5A/div) (5V/div) VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
Pin # Pin Name Pin Function 1F B Feedback input for switching regulator used to program the output voltage — connect to an external resis- tor divider from VOUT to AGND. 2 V5V Bias input for internal analog circuits and gate drives — connect to external 3V or 5V supply or bias connec- tion to VLDO. 3, 26, PAD 1 AGND Analog ground 4 VOUT Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO. 5, 8-11 PAD 2 VIN Input supply voltage
6 VLDO 5V LDO output
7 BST Bootstrap pin — connect a capacitor from BST to LXBST to develop the fl oating supply for the high-side gate drive. 12 LXBST LX Boost — connect to the BST capacitor. 15,20, 21, PAD 3 LX Switching (phase) node 13, 14, 16-19 PGND Power ground 22 PGOOD Open-drain power good indicator — high impedance indicates power is good. An external pull-up resistor is required. 23 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.
24 LXS LX sense — connects to RILIM resistor
25 EN/PSV
Enable/power save input for the switching regulator — connect to AGND to disable the switching regula- tor. Float to operate in forced continuous mode (power save disabled). For SC414, connect to V5V to operate with ultrasonic power save mode enabled. For SC424, connect to V5V to operate with power save mode enabled with no minimum frequency.
27 TON On-time programming input — set the on-time by connecting through a resistor to AGND
28 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con- trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
Control & Status PGOOD Gate Drive Control VIN PGND TON VOUT Zero Cross Detector ILIM ENL VLDO Switchover MUX A Y B LDO VLDO BST FB Comparator V5V EN/PSV Bypass ComparatorBypass Comparator DL A 2 22 25 A = connected to pins 5, 8-11, PAD 2 B = connected to pins 15, 20, 21, PAD 3 C = connected to pins 13, 14, 16-19 D = connect to pins 3, 26, PAD 1 C D VIN V5V V5V V5V VIN Bootstrap Switch Lo-side MOSFET Hi-side MOSFET Valley Current Limit LXB LXBST12 LXS24 DL
This method automatically produces an on-time that is proportional to V OUT and inversely proportional to V IN. Under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. INON OUT SW VT Vf u The SC414/SC424 uses an external resistor to set the on- time which indirectly sets the frequency. The on-time can be programmed to provide an operating frequency from 200kHz to 1MHz using a resistor between the TON pin and ground. The resistor value is selected by the following equation. OUT IN SW TON V V400fpF25 1R u:u The maximum RTON value allowed is shown by the follow- ing equation. A5.110 VR MIN_IN MAX_TON Pu Immediately after the on-time, the DL (drive signal for the low side FET) output drives high to turn on the low-side MOSFET. DL has a minimum high time of ~320ns, after which DL continues to stay high until one of the following occurs: VFB falls below the 750mV reference The Zero Cross Detector senses that the voltage on the LX node is below ground. Power Save is activated when a zero crossing is detected. TON limitations and V5V Supply Voltage For V5V below 4.5V, the TON accuracy may be limited by the input voltage. The original RTON equation is accurate if V IN satisfi es the below relation over the entire VIN range: V IN < (V5V - 1.6V) x 10 If VIN exceeds (V5V - 1.6V) x 10, for all or part of the V IN range, the RTON equation is not accurate. In all cases where VIN > (V5V - 1.6V) x 10, the RTON equation must be modifi ed as follows. OUTSW TON V 101.6V)(V5V400f25pF 1R uu:u Note that when VIN > (V5V - 1.6V) x 10 , the actual on-time is fi xed and does not vary with VIN. When operating in this condition, the switching frequency will vary inversely with V IN rather than approximating a fi xed frequency. VOUT Voltage Selection The switcher output voltage is regulated by comparing VOUT as seen through a resistor divider at the FB pin to the internal 750mV reference voltage (see Figure 3). VOUT To FB pin Figure 3 — Output Voltage Selection Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC output voltage V OUT is off set by the output ripple according to the following equation. §¸¸ § u 2 V R R175.0V RIPPLE OUT When a large capacitor is placed in parallel with R1 (C TOP) VOUT is shown by the following equation. TOP TOP1RIPPLE OUT CRR RR1 )CR(1 V R R175.0V § Z u Zu¸ §¸¸ § u Where ω is the angular switching frequency. Enable and Power-save Inputs The EN/PSV and ENL inputs are used to enable or disable the switching regulator and the LDO. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off , the output of the switching regula- tor soft-discharges the output into a 10Ω internal resistor via the VOUT pin. When EN/PSV is allowed to fl oat, the pin voltage will fl oat to 33% of the voltage at V5V. The switch- ing regulator turns on with power-save disabled and all switching is in forced continuous mode. For V5V < 4.5V, it Applications Information (continued)
The SC414/SC424 includes a switch-over function for the LDO. The switch-over function is designed to increase effi ciency by using the more effi cient DC-DC converter to power the LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function con- nects the VLDO pin directly to the VOUT pin using an internal switch. When the switch-over is complete the LDO is turned off , which results in a power savings and maximizes effi ciency. If the LDO output is used to bias the SC414/SC424, then after switch-over the device is self- powered from the switching regulator with the LDO turned off . The switch-over logic waits for 32 switching cycles before it starts the switch-over. There are two methods that determine the switch-over of V LDO to VOUT. In the fi rst method, the LDO is already in regulation and the DC-DC converter is later enabled. As soon as the PGOOD output goes high, the 32 cycle counter is started. The voltages at the VLDO and VOUT pins are then com- pared; if the two voltages are within ±300mV (typically) of each other, within 32 cylces, the VLDO pin connects to the VOUT pin using an internal switch, and the LDO is turned off . In the second method, the DC-DC converter is already running and the LDO is enabled. In this case the 32 cycles are started as soon as the LDO reaches 90% of its fi nal value. At this time, the VLDO and VOUT pins are compared, and if within ±300mV (typically) the switch-over occurs and the LDO is turned off . Switch-over Limitations on VOUT and VLDO Because the internal switch-over circuit always compares the VOUT and VLDO pins at start-up, there are voltage limitations on permissible combinations of these pins. Consider the situation where V OUT is programmed to 4.7V. After start-up, the device would connect VOUT to VLDO and disable the LDO, since the two voltage are within the ±300mV switch-over window. To avoid unwanted switch- over, the minimum diff erence between the voltages for V OUT and VLDO should be ±500mV. Switch-over MOSFET Parasitic Diodes The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in Figure 11. Switchover MOSFET Parasitic diode Parasitic diode V5V VLDO VOUT Switchover control Figure 11— Switch-over MOSFET Parasitic Diodes There are some important design rules that must be fol- lowed to prevent forward bias of these diodes. The fol- lowing two conditions need to be satisfi ed in order for the parasitic diodes to stay off . V5V ≥ V LDO V5V ≥ VOUT If either VLDO or VOUT is higher than V5V, then the respective diode will turn on and the SC414/SC424 operating current will flow through this diode. This has the potential of damaging the device. ENL pin and VIN UVLO The ENL pin also acts as the switcher under-voltage lockout for the V IN supply. The V IN UVLO voltage is pro- grammable via a resistor divider at the VIN, ENL, and AGND pins. ENL is the enable/disable signal for the LDO. In order to implement the V IN UVLO there is also a timing requirement that needs to be satisfi ed. If the ENL pin transitions low within 2 switching cycles and is < 1V, then the LDO will turn off but the switcher remains on. If ENL goes below the V IN UVLO threshold and stays above 1V, then the switcher will turn off but the LDO remains on. The V IN UVLO function has a typical threshold of 2.6V on the VIN rising edge. The falling edge threshold is 2.4V. Applications Information (continued)
Applications Information (continued) There are two values of load current to evaluate — con- tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and fi ltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. V IN = 12V + 10% VOUT = 1V + 4% fSW = 250kHz Load = 6A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external fi lter components (inductor and output capacitor) and the power conversion effi ciency. The desired switching frequency is 250kHz which results from using components selected for optimum size and cost . A resistor (R TON) is used to program the on-time (indirectly setting the frequency) using the following equation. OUT IN SW TON V V400fpF25 1R u:u To select RTON, use the maximum value for V IN, and for TON use the value associated with maximum VIN. SWINMAX OUT ON fV VT u T ON = 303 ns at 13.2VIN, 1VOUT, 250kHz Substituting for RTON results in the following solution. R TON = 130.9kΩ, use RTON = 130kΩ Inductor Selection In order to determine the inductance, the ripple current must fi rst be defi ned. Low inductor values result in smaller size but create higher ripple current which can reduce effi ciency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more effi cient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and effi ciency are all used in the selection process. The ripple current will also set the boundary for power- save operation. The switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then Power-save operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, effi ciency, and transient performance. During the DH on-time, voltage across the inductor is IN - V OUT ). The equation for determining inductance is shown next. RIPPLE ONOUTIN I T)VV(L u Example In this example, the inductor ripple current is set equal to 50% of the maximum load current. Therefore ripple current will be 50% x 6A or 3A. To find the minimum inductance needed, use the V IN and TON values that corre- spond to VINMAX. H26.1A3 ns318)V1V2.13(L P u A slightly larger value of 1.5μH is selected. This will decrease the maximum I RIPPLE to 2.53A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. ns311ns10V VRpF25T INMIN OUTTON VINMIN_ON uu
Applications Information (continued) L T)VV(I ONOUTIN RIPPLE u A03.2H5.1 ns311)V18.10(I VINMIN_RIPPLE P u Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is con- trolled by the output ripple requirement and the DC toler- ance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 750mV refer- ence tolerance is 1%. Assuming a 1% tolerance from the FB resistor divider, this allows 2% tolerance due to V OUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 40mV for a 1V output. The maximum ripple current of 2.53A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. A53.2 mV40 I VESR RIPPLEMAX RIPPLE MAX ESR MAX = 15.8 mΩ The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capaci- tance. If the load release is instantaneous (load changes from maximum to zero in < 1μs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. OUT PEAK RIPPLEMAXOUT MIN VV 1IL COUT § u Assuming a peak voltage VPEAK of 1.150 (100mV rise upon load release), and a 6A load release, the required capaci- tance is shown by the next equation. MIN V1V05.1 A53.22 1A6H5.1 COUT § uP COUT MIN = 772μF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately OUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capaci- tance for a given dI LOAD/dt. Peak inductor current is shown by the next equation. I LPK = IMAX + 1/2 x IRIPPLEMAX I LPK = 6A + 1/2 x 2.53A = 7.26A dt dlCurrentLoadofchangeofRate LOAD I MAX = maximum load release = 6A OUTPK LOAD MAX OUT LPK LPKOUT VV2 dtdl I V IL IC uu u Example A25.1 dt dlLOAD P
Applications Information (continued) This causes the output current to move from 6A to 0A in 4.8μs, giving the minimum output capacitance require- ment shown in the following equation. V1V05.12 s1A25.1 A26.7H5.1 A26.7COUT PuuP u F443COUT P Note that C OUT is much smaller in this example, 443μF compared to 772μF based on a worst-case load release. To meet the two design criteria of minimum 443μF and maximum 15mΩ ESR, select two capacitors rated at 220μF and 15mΩ ESR or less. It is recommended that an additional small capacitor be placed in parallel with C OUT in order to fi lter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the minimum off -time has expired. In extreme cases the noise can cause three or more successive on-times. Double- pulsing will result in higher ripple voltage at the output, but in most applications it will not aff ect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis- tor, as shown in Figure 13. This capacitor should be left unpopulated unless it can be confirmed that double- pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. VOUT To FB pin CTOP Figure 13 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking sta- bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. One simple way to solve this problem is to add trace resis- tance in the high current output path. A side eff ect of adding trace resistance is a decrease in load regulation. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insuffi - cient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis- charging during the switching cycle. For most applica- tions, the total output ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre- quency. The formula for minimum ESR is shown by the following equation. swOUT MIN fC2 3SRE uuSu
Applications Information (continued) Using Ceramic Output Capacitors When applications use ceramic output capacitors, the ESR is normally too small to meet the previously stated ESR criteria. In these applications it is necessary to add a small virtual ESR network composed of two capacitors and one resistor, as shown in Figure 14. This network creates a ramp voltage across C L, analogous to the ramp voltage generated across the ESR of a standard capacitor. This ramp is then capacitively coupled into the FB pin via capacitor C R2FB pin CC COUT L Low- side High- side CLRL Figure 14 — Virtual ESR Ramp Current Output Voltage Dropout The output voltage adjustable range for continuous-con- duction operation is limited by the fi xed 320ns (typical) minimum off -time. When working with low input volt- ages, the duty-factor limit must be calculated using worst- case values for on and off times. The duty-factor limitation is shown by the next equation. )MIN(OFF)MIN(ON )MIN(ON TT TDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy — VOUT Controller Three factors aff ect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator off set is trimmed so that under static condi- tions it trips when the feedback pin is 750mV, 1%. The on-time pulse from the SC414/SC424 in the design example is calculated to give a pseudo-fi xed frequency of 250kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with V IN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with V IN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this eff ect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors may result in up to an additional 1% error. If tighter DC accuracy is required, resistors with lower tolerances should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor eff ect on the DC output voltage. The output ESR also aff ects the output ripple and thus has a minor eff ect on the DC output voltage. Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fi xed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net eff ect is that frequency tends to falls slightly with increasing input voltage.
Applications Information (continued) All other decoupling capacitors must be located as close as possible to the IC. PGND Plane PGND requires its own copper plane with no other signal traces routed on it. Copper planes, multiple vias, and wide traces are needed to connect PGND to input capacitors, output capacitors, and the PGND pins on the IC. The PGND copper area between the input capacitors, output capacitors, and PGND pins must be as small as and as compact as possible to reduce the area of the PCB that is exposed to noise due to current fl ow on this node. Connect PGND to AGND with a short trace or resistor. This connection should be as close to the IC as possible. AGND Island AGND should have its own island of copper with no other signal traces routed on this layer that connects the AGND pins and pad of the IC to the analog control components. All of the components for the analog control cir- cuitry should be located so that the connections to AGND are done by wide copper traces or vias down to AGND. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the IC as possible. FB, VOUT, and Other Analog Control Signals The connection from the V OUT power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. The traces between VOUT and the analog control circuitry (VOUT, and FB pins) must be short and routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. ILIM and TON nodes must be as short as possible to ensure the best accuracy in current limit and on time. RILIM should be close to the IC and connected to LXS with a Kelvin trace to pin 24 on the IC. This will be a suffi cient connection and will prevent the need to connect the resistor further into the LX plane. The feedback components for the switcher need to be as close to the FB pin of the IC as possible to reduce the possibility of noise corrupting these analog signals. BST, ILIM and LX LX and BST are very noisy nodes and must be carefully routed to minimized the PCB area that is exposed to these signals. The connections for the boost capacitor between the IC and LX must be short and directly connected to the LXBST (pin 12). The connections for the current limit resistor between the ILIM pin and LX must be as short as possible and directly connected to pin 24 (LXS). The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos- sibility of LX noise corrupting other signals. Multiple vias should be used to provide a good connection to LX between the IC and the inductor. Capacitors and Current Loops The current loops between the input capacitors, the IC, the inductor, and the output capacitors must be as close as possible to each other to reduce IR drop across the copper. All bypass and output capacitors must be con- nected as close as possible to the respective pin on the IC.
Outline Drawing — MLPQ-4x4-28 LxN bxN 1.29 D/2 COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: E AD B PIN 1 INDICATOR (LASER MARK) aaa C C SEATING PLANE N R 0.20 PIN 1 IDENTIFICATION e bbb C A B E/2 1.45±0.10 0.73±0.10 2.58 1.29 A MILLIMETERS
0.45 BSC
0.00 2.48 0.30 3.90 3.90 0.96 0.17 DIMENSIONS 0.80 MIN - 0.05 4.10 4.10 2.68 1.16 0.50 0.29 2.58 0.40 0.10 0.08 4.00 (0.20) 1.06 4.00 0.23 1.00 MAX NOM aaa bbb N e L D E b DIM A
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Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com Land Pattern — MLPQ-4x4-28 2.58 X K P 1.29 K G H2 1.29 H Y (C) Z NOTES: 3. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 0.73 1.45 MILLIMETERS (3.95) 0.30 0.75 2.58 0.45 1.06 3.20 DIMENSIONS 4.70 DIM X Y H K P C G Z