SC412A

SC412A SEMTECH | Alldatasheet

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Features

25°C -40° to 85°C Units Min Typ Max Min Max Input Supplies VBAT Input Voltage 3.0 25 V VCC Shutdown Current EN = 0V 1 5 μA VCC Operating Current FB > REF 500 1000 μA Controller FB On-Time Threshold 0.75 0.7425 0.7575 V Regulation Line Regulation Error Typical Application Circuit 0.04 %/V Load Regulation Error Typical Application Circuit 0.3 % 2© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Parameter Symbol Min Max Units DH, BST to GND (DC) DH, BST to GND (transient - 100nsec max) -0.3 -2.0 +30 +33 V D L to GND (DC) DL to GND (transient - 100nsec max) -0.3 -2.0 +6.0 +6.0 V L X to GND (DC) LX to GND (transient - 100nsec max) -0.3 -2.0 +25 +28 V B ST to LX -0.3 +6.0 V RTN to GND -0.3 +0.3 V VCC to RTN -0.3 +6.0 V EN, FB, ILIM, PGOOD, VCC, VOUT to RTN -0.3 V CC + 0.3 V Operating Junction Temperature Range T J -40 +125 oC Storage Temperature Range T STG -60 +150 oC Thermal Resistance, Junction to Ambient(1) θJA 45 oC/Watt Peak IR Refl ow Temperature, 10-40 Second T PKG +260 oC ESD Rating (Human Body Model) 2k V Test Conditions: VBAT = 15V, VOUT = 1.5V, TA = 25 oC, 0.1% resistor dividers; VCC = 5.0V, unless otherwise noted. Exceeding the specifi cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Note: (1) Calculated from package in still air, mounted 3” to 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Absolute Maximum Ratings

Electrical Characteristics

25°C -40° to 85°C Units Min Typ Max Min Max Timing On-Time Continuous Mode Operation VOUT = 1.1V 250 225 275 ns Minimum On-Time 100 ns Minimum Off-Time 350 Maximum Duty Cycle V BAT < VOUT +0.2 VOUT < On-Time Threshold 85 80 % Soft-Start Soft-Start Time I OUT = ILIM/2 1000 μs Analog Inputs/Outputs VOUT Input Resistance 500 k Ω Current Sense Zero-Crossing Detector Threshold LX - GND 0 -7 +7 mV Power Good Power Good Threshold 1% HysteresisTypical -12% -9% -15% % Threshold Delay Time(1) 5 μs Leakage 1 μA Fault Protection ILIM Source Current 10 9 11 μA ILIM Comparator Offset 0 -10 +10 mV Current Limit (Negative) LX - GND 80 60 100 mV Output Under-Voltage Fault FB with Respect to REF -30 -35 -25 % Steady-State Over-Voltage Fault FB with Respect to REF 20 +17 +23 % Over-Voltage Fault Delay(1) FB Forced 50mV Above Over-Voltage Fault Threshold 5 μs VCCA Under-Voltage (UVLO) Conditions = Falling Edge (Hysteresis 100mV) 4 3.7 4.35 V Over-Temperature Shutdown (1) 160 °C Logic Inputs/Outputs Logic Input Hgh Voltage EN 1.2 V Logic Input Low Voltage EN 0.4 V 3© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Electrical Characteristics (continued)

25°C -40° to 85°C Units Min Typ Max Min Max Logic Inputs/Outputs (continued) EN Input Bias Current EN = V CC or RTN -1 +1 μA FB Input Bias Current FB = V CC or RTN -1 +1 μA Power Good Output Low Voltage RPWRGD = 10kΩ to VCC 0.4 V Gate Drivers Shoot-Through Protection Delay(1) DH or DL Rising 30 ns DL Pull-Down Resistance DL Low 0.8 1.6 Ω DL Sink Current V DL = 2.5V 3.1 A DL Pull-Up Resistance DL High 2 4 Ω DL Source Current V DL = 2.5V 1.3 A DH Pull-Down Resistance DH Low, B ST - LX = 5V 2 4 Ω DH Pull-Up Resistance(2) DH High, BST - LX = 5V 2 4 Ω DH Sink/Source Current V DH = 2.5V 1.3 A Notes: (1) Guaranteed by design. (2) Semtech’s SmartDriver™ FET drive fi rst pulls DH high with a pull-up resistance of 10Ω (typical) until LX = 1.5V (typical). At this point, an additional pull-up device is activated, reducing the resistance to 2Ω (typical). This negates the need for an external gate or boost resistor. 4© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Electrical Characteristics (continued)

5© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Notes: 1) Available in tape and reel packaging only. A reel contains 3000 devices. 2) Available in lead-free packaging only. This product is fully WEEE, RoHS and J-TD-020B compliant. This component and all homog- enous sub-components are RoHS compliant. Device Package (2) SC412AMLTRT(1) MLPQ-16 3X3 SC412AEVB Evaluation Board TOP VIEW 16 15 14 13 5678 MLPQ16: 3X3 16 LEAD T EN NC NC BST DH LX VCC DL VOUT ILIM PGOOD FB NC NC RTN GND Pin Confi guration Ordering Information Marking Information 412A yyww xxxx Marking for the 3 x 3mm MLPQ 16 Lead Package nnnn = Part Number (example: 412A) yyww = Date Code (example: 0652) xxxx = Semtech Lot No. (example: E901)

6© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Pin # Pin Name Pin Function

1 LX Switching (phase) node

2 BST Boost capacitor connection for high-side gate drive

3 VCC 5V power input for internal analog circuits and gate drive outputs

4 DL Gate drive output for the low-side external MOSFET

5 GND Power ground — the return point for the DL driver output and the reference point

for the ILIM and Zero Cross circuits

6 RTN Return or analog ground for VOUT sense — connect to GND at the chip

7 NC Not connected internally — leave unconnected or connect to GND

8 NC Not connected internally — leave unconnected or connect to GND

9F B Feedback input — connect to an external resistor divider from VOUT to program the output voltage

10 VOUT Output voltage sense point for determining the on-time

11 PGOOD Open-drain Power Good indicator — high impedance indicates power is good —

an external pull-up resistor is required.

12 EN Enable input — connect EN to RTN to disable the SC412A

13 ILIM Current limit sense point — to program the current limit connect a resistor from ILIM to

LX or to a current sense resistor

14 NC Not connected internally — leave unconnected or connect to GND

15 NC Not connected internally — leave unconnected or connect to GND

16 DH Gate drive output for the high-side external FET

TP A D Thermal pad for heatsinking purposes — not connected internally — connect to system ground through preferably one large via or multiple smaller vias Pin Descriptions

7© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Block Diagram Block Diagram VCC Reference FB PGOODEN VOUT DL LX DH DRV DRV BST VOUT ILIM VBAT RTN +5V PAD GND Power Good TON Generator +5V Valley I-Limit Gate Drive Control Control and Status Enable Zero Cross/Negative I-limit Detect FB VOUT Startup FB Comparator

9© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Applications Information (continued) Enable Input The EN is used to disable or enable the SC412A. When EN is low (grounded), the SC412A is off and in its lowest- power state. When EN is high the controller is enabled and switching will begin. PSAVE Operation The SC412A provides automatic power save operation at light loads. The internal Zero-Cross comparator looks for inductor current (via the voltage across the lower MOSFET) to fall to zero on 8 consecutive cycles. Once observed, the controller then enters power save and turns off the low-side MOSFET on each cycle when the current crosses zero. To add hysteresis, the on-time is increased by 25% in power- save. The effi ciency improvement at light loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller immediately exits power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps. Smart Power Save Protection In some applications, active loads can leak current from a higher voltage and thereby cause VOUT to slowly rise and reach the OVP threshold, leading to a hard shutdown. The SC412A uses Smart Power Save to prevent this. When the feedback signal exceeds 8% above nominal (810mV), the IC exits power save operation (if already active) and DL drives high to turn on the low-side MOSFET, which draws current from VOUT via the inductor. When FB drops back to the 0.75V trip point, a normal TON switching cycle begins. This method cycles energy from VOUT back to VBAT and prevents a hard OVP shutdown, and also minimizes operating power by avoiding continuous conduction-mode operation. Current Limit Circuit Current limiting can be accomplished in two ways. The RD- SON of the lower MOSFET can be used as a current sensing element, or a sense resistor at the lower MOSFET source can be used if greater accuracy is needed. RDSON sensing is more effi cient and less expensive. In both cases, the R ILIM resistor sets the over-current threshold. The RILIM connects from the ILIM pin to either the lower MOSFET drain (for RD- SON sensing) or the high side of the current-sense resistor. R ILIM connects to a 10μA current source from the ILIM pin which turns on when the low-side MOSFET turns on, after the on-time DH pulse has completed. If the voltage drop across the sense resistor or low-side MOSFET exceeds the voltage across the R ILIM resistor, current limit will activate. The high-side MOSFET will then not turn on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the R ILIM resistor. This current sensing scheme actually regulates the inductor valley current, see Figure 3. This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. I LIMIT ILOAD IPEAK INDUCTOR CURRENT TIME Valley Current Limit Figure 3.

11© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Applications Information (continued) Soft-Start The soft-start is accomplished by ramping the FB com- parator’s internal reference from zero to 0.75V in 30mV increments. Each 30mV step typically lasts for eight clock cycles. During the soft-start period, the Zero Cross Detector is active to monitor the voltage across the lower MOSFET while DL is high. If the inductor current reaches zero, the FB comparator’s internal ramp reference is immediately overridden to match the voltage at the FB pin. This soon causes the FB comparator to trip which forces DL to turn off and a DH on-time will begin. This prevents the inductor current from going too negative which would cause droop in the VOUT start-up waveform. The next 30mV step on the internal reference ramp occurs from the new point at the FB pin. Since any of the internal 30mV steps can be over- ridden by the FB waveform, the start-up time is therefore dependent upon operating conditions. This override feature will stop when the FB pin reaches approximately 660mV. At start-up, during the fi rst 32 switching cycles, the over- current threshold is reduced by 50%, to reduce overshoot caused by the fi rst set of switching pulses. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate high-side and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off, and conversely, monitors the DH output and prevents the low- side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. The SC412A utilizes SmartDrive TM to achieve fast switching with reduced noise. At the start of the DH on-time when LX is typically below GND, the DH output drives the high- side MOSFET through a pull-up resistance of 10 ohms, which results in a soft reverse-recovery of the low-side diode. The high-side MOSFET conducts and causes LX to rise; when LX reaches 1.5volts, the DH drive resistance is reduced to 2 ohms to provide fast switching and reduce switching loss. Design Procedure Prior to designing a switch mode supply, the input voltage, load current, switching frequency and inductor ripple cur- rent must be specifi ed. For notebook systems the maximum input voltage (VIN MAX) is determined by the highest AC adaptor voltage, and the minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. In general, four parameters are needed to de fi ne the design: 1) Nominal output voltage (VOUT) 2) Static or DC output tolerance 3) Transient response 4) Maximum load current (IOUT) There are two values of load current to consider: continu- ous load current and peak load current. Continuous load current is concerned with thermal stresses which drive the selection of input capacitors, MOSFETs and commuta- tion diodes. Peak load current determines instantaneous component stresses and fi ltering requirements such as inductor saturation, output capacitors and design of the current limit circuit. Design example: VBAT = 10V min, 20V max VOUT = 1.15V +/- 4% Load = 20A maximum Inductor Selection Low inductor values result in smaller size, but create high- er ripple current and are less effi cient because of the high AC current fl owing in the inductor. Higher inductor values will reduce the ripple current and are more ef fi cient, but are larger and more costly. The inductor selection is gen- erally based on the ripple current which is typically set between 20% to 50% of the maximum load current. Cost, size, output ripple and effi ciency all play a part in the se- lection process.

12© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Applications Information (continued) The switching frequency is optimized for 325kHz. The equation for on-time is: TON (nsec) = 2560 • (V OUT/VBAT) + 35 During the DH on-time, voltage across the inductor is (VBAT - VOUT). To determine the inductance, the ripple current must be defi ned. Smaller ripple current will give smaller output ripple and but will lead to larger inductors. The ripple current will also set the boundary for PSAVE operation: the switching will typically enter PSAVE operation when the load current decreases to 1/2 of the ripple current; (i.e. if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then PSAVE will commence for loads less than 20% of maximum current). The equation for determining inductance is: L = (V BAT - VOUT) • T ON / IRIPPLE Use the maximum value for VBAT, and for TON use the value associated with maximum VBAT. T ON = 182 nsec at 20VBAT, 1.1VOUT L = (20 - 1.15) • 182 nsec / 5A = 0.69 μH We will select a slightly larger value of 0.7 μH, which will decrease the maximum IRIPPLE to 4.91A. Note: the inductor must be rated for the maximum DC load cur- rent plus 1/2 of the ripple current. The ripple current under minimum VBAT conditions is also checked. TON VBATMIN = 2560 • (1.15/10) + 35 = 329 nsec I RIPPLE = (VBAT - VOUT) • T ON / L I RIPPLE_VBATMIN = (10 - 1.15) • 329 nsec / 0.7 μH = 4.16A Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The ESR requirement is driven by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple, plus 1/2 of the peak-to-peak ripple. Change in the ripple voltage will lead to a change in DC voltage at the output. The design goal is +/-4% output regulation. The internal 0.75V reference tolerance is 1%, assuming 1% tolerance for the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 46mV for a 1.15V output. The maximum ripple current of 4.05A creates a ripple voltage across the ESR. The maximum ESR value allowed would be 44mV: ESR MAX = VRIPPLE/IRIPPLEMAX = 46mV / 4.91A ESR MAX = 9.4 mΩ The output capacitance is typically chosen based on tran- sient requirements. A worst-case load release, from maxi- mum load to no load at the exact moment when inductor current is at the peak, de fi nes the required capacitance. If the load release is instantaneous (load changes from maximum to zero in a very small time), the output capaci- tor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the equation: COUT MIN = L • (I OUT + 1/2 • I RIPPLEMAX)2 / (VPEAK 2 - VOUT2) Assuming a peak voltage VPEAK of 1.230 (80mV rise upon load release), and a 10 amp load release, the required capacitance is: COUTMIN = 570μF

13© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Layout Guidelines These requirements (650μF, 10.8mΩ) can be met using two capacitors, 330μF 20mΩ. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 0.75V reference, the DL output is high and the low-side mosfet is on. During this time, the voltage across the inductor is approximately - VOUT. This causes a downslope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt in the inductor, then the inductor current can track change in load current, and there will be relatively less overshoot from a load release. The following can used to calculate the needed capacitance for a given dILOAD/dt: Peak inductor current, ILPEAK = I LOADMAX + 1/2 • I RIPPLEMAX ILPEAK = 10 + 1/2 • 4.05 = 12.02A Rate of change of Load current = dILOAD/dt I MAX = maximum load release = 10A COUT = ILPEAK • (L •ILPEAK / VOUT - IMAX/dILOAD/dt) 2 • (VPEAK - VOUT) Example: Load dI/dt = 2.5A/usec This would cause the output current to move from 10A to zero in 4μsec. C 2 •(1.23 - 1.15) C OUT = 278 μF Stability Considerations Unstable operation shows up in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. double-pulsing occurs due to switching noise seen at the FB input or because the ESR is too low, caus- ing insuffi cient voltage ramp in the FB signal. This causes the error amplifi er to trigger prematurely after the 350ns minimum off-time has expired. double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. In some cases, however, double-pulsing can indicate the presence of loop instability, which is caused by insuffi cient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a small (e.g. 10pF) capacitor across the upper feedback resistor divider net- work, (this capacitor is shown in Figure 6). This capacitance should be left out until con fi rmation that double-pulsing exists. Adding this capacitance will add a zero in the trans- fer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed. To FB pinVOUT C Figure 6. Loop instability can cause oscillations at the output as a response to line or load transients. These oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero-to- full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ring- ing after the initial step is a sign that the ESR should be increased.

14© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Layout Guidelines (continued) SC412A ESR Requirements The constant on-time control used in the SC412A regulates the valley of the output ripple voltage. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors, the absolute minimum ESR must be considered. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. To prevent double pulsing, the ripple voltage present at the FB pin should be 10-15mV minimum over the on-time interval. Dropout Performance The output voltage adjust range for continuous-conduction operation is limited by the fi xed 350nS (typical) Minimum Off-time One-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by: T ON(MIN) T ON(MIN) + TOFF(MAX) Be sure to include inductor resistance and MOSFET on- state voltage drops when performing worst-case dropout duty-factor calculations. SC412A System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the switching frequency variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that it trips when the feedback pin is 0.75V, 1%. The on-time pulse in the SC412A is calculated to give a pseudo-fi xed frequency of 325kHz. Nevertheless, some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because con- stant on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, If the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25 volts, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is often desirable to use passive droop. Take the feedback directly from the output side of the inductor, placing a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. The use of 1% feedback resistors contributes up to 1% er- ror. If tighter DC accuracy is required use 0.1% resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output volt- age. The output ESR also affects the ripple and thus the DC output voltage. Switching Frequency Variations The switching frequency will vary somewhat due to line and load conditions. The line variations are a result of a fi xed offset in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As VBAT increases, these factors make the actual DH on-time slightly longer than the idealized on-time. The net effect is that frequency tends to falls slightly as with increasing input voltage. The load variations are due to losses in the power train due to IR drop and switching losses. For a conventional PWM constant-frequency topology, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time topology must also overcome the same losses

16© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Layout Guidelines Layout Guidelines One or more ground planes are recommended to minimize the effect of switching noise and copper losses and to maximize heat removal. The analog ground reference, RTN, should connect directly to the thermal pad, which in turn connects to the ground plane through preferably one large via. There should be a RTN plane or copper are near the chip; all components that are referenced to RTN should connect to this plane directly, not through the ground plane, and located on the chip side of the PCB if possible. GND should be a separate plane which is not used for routing analog traces. The VCC input provides power to the internal analog circuits and the upper and lower gate drivers. The VCC supply decoupling capacitor should be tied be- tween VCC and GND with short traces. All power GND connections should connect directly to this plane with special attention given to avoiding indirect connections between RTN and GND which will create ground loops. As mentioned above, the RTN plane must be connected to the GND plane at the chip near the RTN/GND pins. The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the power connections on one side of the PCB using wide copper fi lled areas if possible. Do not use “minimum” land patterns for power components. Minimize trace lengths and maximize trace widths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses); the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitic) if routed on more than one layer. For an accurate ILIM current sense connection, connect the ILIM trace to the current sense element (MOSFET or resistor) directly at the pin of the element, and route that trace over to the ILIM resistor on another layer if needed. The layout can be generally considered in two parts; the control section referenced to RTN, and the switcher power section referenced to GND. Looking at the control section fi rst, locate all components referenced to RTN on the schematic and place these components near the chip and on the same side if possible. Connect RTN using a wide trace. Very little current fl ows in the RTN path and therefore large areas of copper are not needed. Connect the RTN pin directly to the thermal pad under the device as the only connection between RTN and GND. The chip supply decoupling capacitor (VCC/GND) should be located near to the pins. Since the DL pin is directly between VCC and GND, and the DL trace must be a wide, direct trace, the VCC decoupling capacitor is best placed on the opposite side of the PCB, routed with traces as short as possible and using at least two vias when connecting through the PCB. There are two sensitive, feedback-related pins at the chip: VOUT and FB. Proper routing is needed to keep noise away from these signals. All components connected to FB should be located directly at the chip, and the copper area of the FB node minimized. The VOUT trace that feeds into the VOUT pin, which also feeds the FB resistor divider, must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the VOUT trace in a quiet layer if possible, from the output capacitor back to the chip. For the switcher power section, there are a few key guidelines to follow:

17© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Layout Guidelines (continued) 1) There should be a very small input loop between the input capacitors, MOSFETs, inductor, and output capacitors. Locate the input decoupling capacitors directly at the MOSFETs. 2) The phase node should be a large copper pour, but still compact since this is the noisiest node. 3) The power GND connection between the input capacitors, low-side MOSFET, and output capacitors should be as small as is practical, with wide traces or planes. 4) The impedance of the power GND connection between the low-side MOSFET and the GND pin should be minimized. This connection must carry the DL drive current, which has high peaks at both rising and falling edges. Use multiple layers and multiple vias to minimize impedance, and keep the distance as short as practical. Finally, connecting the control and switcher power sections should be accomplished as follows: 1) Route the VOUT feedback trace in a “quiet” layer, away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to the chip using wide traces, with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power GND as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. DL, DH, LX, and BST are high-noise signals and should be kept well away from sensitive signals, particularly FB and VOUT. 3) BST is also a noisy node and should be kept as short as possible. The high-side DH driver is relies on the boost capacitor to provide the DH drive current, so the boost capacitor must be placed near the IC and connect to the BST and LX pins using short, wide traces to minimize impedance. 4) Connect the GND pin on the chip to the VCC decoupling capacitor and then drop vias directly to the ground plane. Locate the current limit resistor RLIM at the chip with a kelvin connection to the drain of the lower MOSFET at the phase node, and minimize the copper area of the ILIM trace.

18© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Typical Characteristics TON vs. VBAT - VOUT > 2.5V Note: See Reference schematic on Page 20. TON vs. VBAT - VOUT < 1.8V Frequency vs. VBAT Ef fi ciency vs. Load - 1.15V Output Load Regulation Line Regulation 1.07 1.08 1.09 1.10 1.11 1.12 1.13 0 2 4 6 8 1 01 21 41 61 82 0 Load (A) VOUT (V) 10V 19V 15V 1.07 1.08 1.09 1.10 1.11 1.12 1.13 10 12 14 16 18 VBAT (V) VOUT (V) No Load 10A 15A 100 200 300 400 500 600 700 800 900 1000 51 0 1 5 2 0 VBAT (V) TON (nsec) 0.75V 1.1V 1.5V 1.8V 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 51 0 1 5 2 0 VBAT (V) TON (nsec) 2.5V 3.3V 5V 75% 80% 85% 90% 95% 02468 1 0 1 2 1 4 1 6 1 8 2 0 Load (A) Efficiency (%) 10V 15V 19V 300 310 320 330 340 350 360 370 380 390 400 5 7 9 1 11 31 51 71 92 12 3 VBAT (V) Frequency (kHz) 0.75V 0.9V 1.0V 1.1V 1.25V 1.5V1.8V

19© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Typical Characteristics (continued) Startup 1.15V 19VBAT No load Note: See Reference schematic on Page 20 Startup 1.15V 19VBAT 20A load Load Transient Response 0A to 20A Load Transient Response 20A to 0A

20© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Reference Design Reference Design 1.15V 20A D RJK0305DP BAT54A 10UF EN PGD +C5* *330uF/6mohm 18.7K VCC VOUT LX1 BST2 VCC3 DL4 GND5 RTN6 NC7 NC8 FB 9 VOUT 10 PGD 11 EN 12 ILIM 13 NC 14 NC 15 DH 16

17 PAD

0.7uH 1UF VCC 10K 10NF C10 NO_POP +C6* R4 10K VOUT D RJK0302DP Component Value Manufacturer Part Number Web C1, C2, C3 10uF, 25V Murata GRM32DR71E106KA12L www.murata.com C5, C5 330uF/6mohm/2V Panasonic EEFSX0D331XR www.panasonic.com L1 0.7uH, 24A NEC Tokin C-PI-1350-0R7S http://www.nec-tokin.com Q1 10mohm/30V Renesas RJK0305DBP www.renesas.com Q2 3.5mohm/30V Renesas RJK0302 www.renesas.com D1 200mA/30V OnSemi BAT54C www.onsemi.com D2 1A/40V OnSemi MBSR140LT3 www.onsemi.com Bill of Materials

21© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT NOTES: bbb C A B aaa C .003 .061 .067 .000 .031 (.008) 0.08 .071 1.55 .040 .002 0.00 0.80 1.801.70 0.05 1.00 (0.20) .004 0.10 1.55 2.90 1.70 1.80 3.00 3.10 0.50 BSC.020 BSC .122.118.114 .071.067.061 A COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. INCHES DIMENSIONS NOM e bbb aaa DIM N L E MIN D A MILLIMETERS MAXMINMAX NOM E BD e/2 e bxN N PIN 1 INDICATOR (LASER MARK) A C SEATING PLANE LxN E/2 D/2 3. DAP IS 1.90 x 1.90mm. Outline Drawing - MLPQ-16 3x3

22© 2006 Semtech Corp. www.semtech.com SC412A POWER MANAGEMENT Y G Z C Z P Y X G H .146 .020 .012 .031 .083 .067 3.70 0.30 0.80 0.50 1.70 2.10 DIM (2.90) MILLIMETERS DIMENSIONS (.114) INCHES K .067 1.70 FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD2. P X H K(C) R R .006 0.15 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: Land Pattern - MLPQ-16 3x3 Semtech Corporation Power Management Products Division

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