SC410

SC410 SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Input voltage — 5.5V to 24V Output voltage — 0.75V to 7.5V Output current — Up to 3A Internal reference — + 1% Small ceramic capacitors Power good pin (open-drain) Patented adaptive on-time control: Excellent transient response Programmable pseudo-fixed frequency during CCM Fault protection features: Cycle-by-cycle current limit Short circuit protection Over and under output voltage protection Over-temperature Internal soft-start Ultrasonic power save and smart PSAVE Internal LDO for bias voltage Ultra-small lead-free 3 x 3mm, 10-Pin MLPD package WEEE and RoHS compliant

Applications

Networking Equipment, Embedded Systems Medical Equipment, Offi ce Automation Instrumentation, Portable Systems Consumer Devices such as DTV and Set-top Boxes POL Converters

Description

The SC410 is an integrated, synchronous 3A EcoSpeed TM step-down regulator. It incorporates Semtech’s advanced, patented adaptive on-time architecture to achieve best- in-class dynamic performance using point-of-load appli- cations. The input voltage range is 5.5V to 24V with a programmable output voltage from 0.75V up to 7.5V. The device features an internal LDO and ultrasonic PSAVE mode for high effi ciency across the output load range. Adaptive on-time control provides programmable pseudo-fi xed frequency operation in continuous conduc- tion and excellent transient performance. The switching frequency can be set from 200kHz to 1MHz, allowing the designer to reduce external LC fi ltering and minimize light load (standby) losses. Additional features include cycle-by-cycle current limit, soft start, input UVLO and output OV protection, and over temperature protection. The open-drain PGOOD pin pro- vides output status. Standby current is less than 10μA when disabled. The device is available in a low profi le, thermally enhanced MLPD 3 x 3mm 10-pin package. SC410 EN VIN TON LDO LX BST VOUT Enable VIN FB PGOOD CIN CLDO2 RTON CBST COUT RTOP RBOT PGOOD CLDO1 PGNDAGND

Pin Confi guration Ordering Information Marking Information Device Package SC410MLTRT(1)(2) MLPD-10 3 x 3 SC410EVB Evaluation Board TOP VIEW BST VIN LX PGND EN LDO AGND TON PGOOD FB 410 yyww xxxx MLPD; 3 x 3, 10 LEAD θJA = 40°C/W yyww = Date code xxxx = Lot number Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free.

Peak IR Refl ow Temperature (°C Recommended Operating Conditions Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W ) . . . . 40 Exceeding the above specifi cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

Electrical Characteristics

Unless specifi ed: VIN =12V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C, per detailed application circuit Parameter Conditions Min Typ Max Units Input Supplies VIN UVLO Threshold Programmable with EN pin after 2 switching cycles 1.5 V VIN UVLO Hysteresis 50 mV Internal Bias UVLO Threshold Rising UVLO V TH 4V Internal Bias UVLO Hysteresis 0.3 V VIN Supply Current VEN = 0V 9 μA IOUT= 0A, fSW=25kHz(1) 2.5 mA Controller FB On-Time Threshold 0.7425 0.75 0.7575 V Frequency Programming Range See R TON Calculation 200 1000 kHz Minimum Frequency Range during Ultrasonic PSAVE 22 kHz FB Input Bias Current FB=5V or 0V -1 +1 μA

Parameter Conditions Min Typ Max Units Timing On-Time Continuous Mode V IN=15V, VOUT=3V, RTON= 200kΩ 0.9 1 1.1 μs Minimum On-Time(1) 100 ns Minimum Off -Time(1) 320 ns Soft start Soft start Time(1) Delay from PWM Switching to Output Regulation 850 μs Current Sense Zero-Crossing Detector Threshold LX - PGND -10 0 +10 mV Power Good Power Good Threshold Upper Limit, VFB > internal 750mV reference 120 %VREF Lower Limit, VFB < internal 750mV reference 90 PGOOD Delay Time(1) Between VOUT at 90% of its regulation value and the PGOOD signal transitioning to high 1m s Noise Immunity Delay Time (1) 5μ s Leakage 1μ A Power Good On-Resistance 10 Ω Fault Protection Output Under-Voltage Fault FB with Respect to REF,

8 Consecutive Switching Cycles 75 %V REF

Output Over-Voltage Fault FB with Respect to REF 120 %V REF Smart PowerSave Protection Threshold FB with Respect to REF 110 %V REF OV, UV Fault Noise Immunity Delay (1) 5μ s Over-Temperature Shutdown (1) OT Latched 145 °C Enable Logic PWM Output Enabled(1) 1.5 V LDO Output Enabled 0.8 V EN Input Bias Current V EN = 5V -10 10 μA Electrical Characteristics (continued)

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Gate Drivers BST Switch On resistance 25 Ω Internal Power MOSFETs Current Limit(2) Inductor Valley Current Limit, VLDO=5V 2.4 3.2 A LX Leakage Current VIN=24V, LX=0V, High Side 1 10 μA Switch Resistance High Side 215 mΩ Low Side 110 Non-overlap time (1) 15 ns Linear Regulator (The LDO is shorted to the bias node, internally) LDO Accuracy -4 4 %V LDO LDO Current Limit Short circuit protection, VIN = 12V, VLDO <80% of fi nal VLDO value 35 mA Operating current limit, VIN = 12V, VLDO > 80% of fi nal VLDO value 100 LDO Drop Out Voltage From V IN to VLDO, ILDO = 100mA 1.2 V Note: (1) Typical value from EVB, not ATE tested. (2) The minimum inductor valley current limit of 2.4V gives an average output current limit of 3A assuming 1.2A inductor ripple current.

Detailed Application Circuit-1 S C410 BST VIN2 LX3 PGND4 EN 7 TON 8 AGND 9 LDO 10 FB 6PGOOD5 CBST CTOP NP RTON RTOP RL NP 10nF CC 47pF COUT2 (1) COUT3 (1)COUT1 (1) 3A max. CL 10nF VIN CLDO2 0.1μF 12.4kΩ 2.2μH 34kΩ RBOT 10kΩ CLDO1 +5 to +24VDC CIN (1 ) Note: (1) Ceramic capacitors VLDO 10µF 22µF 22µF 22µF 90.9kΩ 0.1μF 1μF VOUT VIN RPGOOD REN CC_1 Position as close to IC as possible

Detailed Application Circuit-2 S C410 BST VIN2 LX PGND4 EN 7 TON 8 AGND 9 LDO 10 FB 6PGOOD5 CBST CTOP NP RTON RTOP 10nF COUT2 (2) 3A max. VIN CLDO2 0.1μF 2.2μH 34kΩ RBOT 10kΩ CLDO1 +5 to +24VDC CIN (1 ) VLDO 10µF 90.9kΩ 0.1μF1 μF VOUT VIN RPGOOD REN Notes: (1) Ceramic capacitor ( 2) Capacitor must provide ESR for user application Position as close to IC as possible

Characteristics are based on a circuit with VIN = 12V, L = 2.2μH (DCR = 35mΩ), COUT = 66μF, VOUT = 3.3V, VLDO = 5V, RTON = 90.9kΩ. IOUT (ADC) Efficiency (%) PLOSS (W) 0.0 0.1 1.0 10.0 0.0 1.0 2.0 3.0 4.0 Efficiency PLOSS VIN = 8V VIN = 24V VIN = 12V VIN = 18V VIN = 24V VIN = 8V VIN = 18V VIN = 12V Effi ciency — Power Loss IOUT (ADC) -2.4 -1.8 -1.2 -0.6 0.6 1.2 1.8 0 0.1 1.0 10.0 VIN = 24V VIN = 8V VIN = 18V VIN = 12V VOUT (%) Load Regulation IOUT (ADC) 100 200 300 400 500 600 700 Frequency (kHz) VIN = 24VVIN = 8V VIN = 12V VIN = 18V Switching Frequency IOUT (ADC) 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 VOUT Ripple (V) VIN = 24V VIN = 8V VIN = 18V VIN = 12V Switching Ripple -2.4 -1.8 -1.2 -0.6 0.6 1.2 1.8 6 9 12 15 18 21 24 Input Voltage (V) VOUT (%) Line Regulation IOUT = 1.5A 0.2 0.4 0.6 0.8 1.2 1.4 6 9 12 15 18 21 24 Input Voltage (V) On-Time (ms) On-Time vs. VIN IOUT = 1.5A

Typical Characteristics (continued) Time (100μs/div) (50mV/div) (10V/div) IOUT = 3A to 0A Transient Response Time (2μs/div) (20mV/div) (10V/div) IOUT = 1.5A CCM Time (400μs/div) (5V/div) (1V/div) (5V/div) (10V/div) IOUT = 0A Start-up Time (10μs/div) (20mV/div) (10V/div) IOUT = 0A Power Save Time (40μs/div) (5V/div) (1V/div) (5V/div) (10V/div) IOUT = 1.5A Shutdown Time (400μs/div) (5V/div) (200mV/div) (2V/div) (10V/div) IOUT = 1.5A Start-up Characteristics are based on a circuit with VIN = 12V, L = 2.2μH (DCR = 35mΩ), COUT = 66μF, VOUT = 3.3V, VLDO = 5V, RTON = 90.9kΩ.

Pin # Pin Name Pin Function 1 BST Bootstrap pin — A capacitor is connected between BST to LX to develop the fl oating voltage for the high-side gate drive.

2 VIN Power input supply voltage

3 LX Switching (phase) node

4 PGND Power ground

5 PGOOD Open-drain power good indicator — High impedance indicates power is good. An external pull-up resistor is required. 6F B Feedback input for switching regulator — Connect to an external resistor divider from the output to pro- gram the output voltage. 7E N Enable input for switching regulator —Pull EN high to enable the part with ultrasonic power save mode en- abled. Connect to AGND to disable the switching regulator. A voltage divider can be added between VIN and AGND pins for input UVLO functionality. 8 TON On-time set input — Set the on-time by connecting a series resistor to AGND. 9 AGND Analog Ground. 10 LDO Output for the internal LDO and internal connection to the bias node — Decoupling capacitors are required to AGND and PGND regardless of the use of the LDO for external loads. PAD Thermal pad for heatsinking purposes. (Not connected internally) Connect to AGND plane using multiple vias.

Synchronous Buck Converter The SC410 is a step down synchronous buck DC-DC regu- lator. The device is capable of 3A operation at very high effi ciency in a tiny 3 x 3-10 pin package. The programma- ble operating frequency range of 200kHz – 1MHz enables the user to optimize the design for minimum board space and optimum effi ciency. The buck regulator employs pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response thereby lowering the size of the power components used in the system. Input Voltage Range The SC410 can operate with a wide input voltage ranging from 5.5V to 24V. The internal LDO generates a fixed 5V output that provides power for the bias of the SC410. The LDO can also provide additional power to an external load. Psuedo-fi xed Frequency Adaptive On-time Control The PWM control method used by the SC410 is pseudo- fi xed frequency, adaptive on-time, as shown in Figure 1. The ripple voltage generated at the output capacitor ESR is divided down by the feedback resistor network and used as a PWM ramp signal. The ripple seen at the FB pin is used to trigger the on-time of the controller. L COUT ESR CIN VOUT FB Threshold VFB VLX VLX TON FB VIN Figure 1 — PWM Control Method, VOUT Ripple The adaptive on-time is determined by an internal one- shot timer. When the one-shot is triggered by the feed- back ripple, the device sends a single on-time pulse to the high-side MOSFET. The pulse period is determined by the output voltage value and VIN. The period is proportional to output voltage and inversely proportional to input voltage. The value of the output voltage is obtained by fi ltering the voltage seen on the LX pin. With this adaptive on-time design, the device automati- cally anticipates the on-time needed to regulate V OUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: Predictable operating frequency during CCM compared to other variable frequency methods. Reduced component count by eliminating the error amplifier and compensation components. Reduced component count by removing the need to sense and control inductor current. Fast transient response — the response time is controlled by a fast comparator instead of a typically slow error amplifi er. Reduced output capacitance due to fast tran- sient response One-Shot Timer and Operating Frequency The one-shot timer operates as shown in Figure 2. The feedback comparator output goes high when V FB is less than the internal 750mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator, timing capacitor, and a low pass fi lter (LPF) which regenerates V OUT from LX. One compara- tor input is connected to the fi ltered LX voltage, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to V IN. When the capacitor voltage reaches VOUT, the on-time is completed and the high-side MOSFET turns off . Applications Information

Applications Information (continued) PGOOD will transition low if the V FB pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh- old (900mV). Output Over-Voltage Protection OVP (Over-Voltage Protection) becomes active as soon as the device is enabled. The threshold is set at 750mV + 20% (900mV). When V FB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off , until the EN input is toggled or V IN is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls to 75% of its nominal voltage (falls to 562.5mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to turn off the MOSFETs. The controller stays off until EN is toggled or V IN is cycled. Over-Temperature Protection If the temperature rises to 145°C the device will latch off . The device can be activated after the temperature is reduced below 145°C by cycling the EN pin. VLDO UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switch- ing and tri-states the power FETs until V LDO rises above 4.0V. An internal POR (Power-On Reset) occurs when V LDO exceeds 4.0V, which resets the fault latch and soft start counter to begin the soft start cycle. The SC410 then begins a soft start cycle. The PWM will shut off if V LDO falls below 3.7V. Internal LDO Regulator The SC410 has an internal regulator that supplies the bias voltage for the PWM controller. This LDO can also supply an additional external current for an external load through the LDO pin. When activated, the LDO checks the status of the following signals to ensure proper operation can be maintained. EN pin VLDO output voltage VIN input voltage While the EN pin is above 0.5V, the LDO will be activated. While the V LDO output voltage remains below 4V (80% of the fi nal LDO voltage), the LDO short-cicuit protection is enabled and limits the current to about 35mA. After the V LDO exceeds 4.0V, then the LDO operates in its normal regulation mode where the current is limited to about 100mA. 80% of VLDO Final VLDO Final Sort-circuit Protection @ ~35mA Voltage regulating with ~100mA current limit Figure 8 — LDO Start-Up Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifi ed. The maximum input voltage (V INMAX) is the highest speci- fi ed input voltage. The minimum input voltage ( V INMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters defi ne the design. Nominal output voltage (V OUT) Static or DC output tolerance Transient response Maximum load current (I OUT) The two values of load current to evaluate are continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selec- tion of the inductor and input capacitors. Peak load current determines instantaneous component stresses and fi lter- ing requirements such as inductor saturation, output capacitors, and design of the current limit circuit.

Applications Information (continued) The following values are used in this design example. VIN = 12V + 10% VOUT = 3.3V + 4% fSW = 500kHz Load = 3A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external fi lter components (inductor and output capacitor) and the power conversion effi ciency. The desired switching frequency is 500kHz which results from using components selected for optimum size and cost. A resistor (R TON) is used to program the on-time (indirectly setting the frequency) using the following equation. OUT IN SW TON V V400fpF25 1R u:u To select RTON, use the maximum value for V IN, and for TON use the value associated with maximum VIN. SWINMAX OUT ON fV Vt u t ON = 500 ns at 13.2VIN, 3.3VOUT, 500kHz Substituting for RTON results in the following solution. R TON = 78.5kΩ, use RTON = 78.7kΩ Now, tON = 501ns given that RTON = 78.7kΩ. Inductor Selection In order to determine the inductance, the ripple current must fi rst be defi ned. Low inductor values result in smaller size but create higher ripple current which can reduce effi ciency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more effi cient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and effi ciency are all used in the selection process. The ripple current will also set the boundary for power- save operation. The switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 2A then power-save operation will typically start for loads less than 1A. If ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. During the DH on-time, voltage across the inductor is IN - V OUT ). The equation for determining inductance is shown next. RIPPLE ONOUTIN I t)VV(L u Example In this example, the inductor ripple current is set equal to 75% of the maximum load current. Therefore ripple current will be 75% x 3A or 2.25A. To fi nd the minimum inductance needed, use the V IN and TON values that corre- spond to VINMAX. H204.2A25.2 ns501)V3.3V2.13(L P u A standard value of 2.2μH is selected. This gives a maximum I RIPPLE of 2.53A. The peak ripple can be calculated by the equation, below where L TOL is assumed to be an inductor tolerance of 20%. I RIPPLE_PEAK = IRIPPLE_MAX x (1 + LTOL) = 2.705 Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. I LSAT_MIN = IRIPPLE_PEAK X 0.5 + IOUT = 4.353 The ripple current under minimum V IN conditions is also checked using the following equations. ns611ns10V VRpF25t INMIN OUTTON VINMIN_ON uu L t)VV(I ONOUTIN RIPPLE u A08.2H2.2 ns612)V3.3V8.10(I VINMIN_RIPPLE P u

Applications Information (continued) Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is con- trolled by the output ripple requirement and the DC toler- ance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 750mV reference tolerance is 1%. Assuming a 1% tolerance from the FB resis- tor divider, this allows 2% tolerance due to V OUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 132mV for a 3.3V output. The maximum ripple current of 2.7A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. A705.2 mV132 I V2ESR RIPPLEMAX RIPPLE MAX u ESR MAX = 48.8 mΩ The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capaci- tance. If the load release is instantaneous (load changes from maximum to zero in < 1μs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. OUT PEAK PEAK_RIPPLEOUTTOL MIN VV 1IL1L COUT § uu Assuming a peak voltage VPEAK of 1.150 (132mV rise upon load release), and a 6A load release, the required capaci- tance is shown by the next equation. MIN V3.3V432.3 A705.22 1A3%201H2.2 COUT § uP COUT MIN = 56μF If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately V OUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capaci- tance for a given dI LOAD/dt. Peak inductor current is shown by the next equation. I LPK = IMAX + 1/2 x IRIPPLEMAX I LPK = 3A + 1/2 x 2.7A = 4.353A dt dlCurrentLoadofchangeofRate LOAD I MAX = maximum load release = 3A OUTPK LOAD MAX OUT LPK TOL LPKOUT VV2 dtld I V IL1L IC uuu u Example dt dlLOAD P This causes the output current to move from 3A to 0A in 4.8μs, giving the minimum output capacitance require- ment shown in the following equation. V3.3V432.32 s1A2 V3.3 A353.4%201H2.2 A353.4COUT PuuP u Note that COUT is much smaller in this example, 33μF com- pared to 56μF based on a worst-case load release. To meet the two design criteria of minimum 56μF, select three capacitors rated at 22μF and 15mΩ ESR.

Applications Information (continued) Stability Considerations Unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the minimum off -time has expired. In extreme cases the noise can cause three or more successive on-times. Double- pulsing will result in higher ripple voltage at the output, but in most applications it will not aff ect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout. An alternate method to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 9. This capacitor should be left unpopulated unless it can be confirmed that double- pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be provided for this capacitor. VOUT To FB pin CTOP Figure 9 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking sta- bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. One simple method of solving this problem is to add trace resistance in the high current output path. A side eff ect of adding trace resistance is a decrease in load regulation. ESR Requirements A minimum ESR is required for two reasons. The first reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insuffi - cient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis- charging during the switching cycle. For most applica- tions, the total output ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre- quency. The formula for minimum ESR is shown by the following equation. swOUT MIN fC2 3SRE uuSu Using Ceramic Output Capacitors When applications use ceramic output capacitors, the ESR is normally too small to meet the previously stated ESR criteria. In these applications it is necessary to add a small signal injection network as shown in Figure 10. In this network R L and C L filter the LX switching waveform to generate an in-phase ripple voltage comparable to the ripple seen on higher ESR capacitors. C C is a coupling capacitor used to AC couple the generated ripple onto the FB pin.

Applications Information (continued) R2FB pin CC COUT L Low- side High- side CLRL Figure 10 — Signal Injection Circuit The values of R L, CL, and CC are dependent on the condi- tions of the specifi c application such as V IN, VOUT, fSW and IOUT. Select a value for C L, like 10nF. Using C L, calculate R L as shown in the following equation: DCRC LR L L u Where L is the inductor value and DCR is the resistance of the inductor. The value for C C can be between C C_MIN and C C_MAX. EQ ON MIN_C R tC EQ MAX_C R TC Where T = 1/f SW and R EQ is represented by the following equation. TOPBOTTOM TOP BOTTOMEQ RR RRR u It is benefi cial to use the smallest value of CC that provides stability and enough voltage ripple at feedback. Larger values of C C may negatively affect the load regulation performance. Output Voltage Dropout The output voltage adjustable range for continuous-con- duction operation is limited by the fi xed 320ns (typical) minimum off -time. When working with low input volt- ages, the duty-factor limit must be calculated using worst- case values for on and off times. The duty-factor limitation is shown by the next equation. )MAX(OFF)MIN(ON )MIN(ON tt tDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy — VOUT Controller Three factors aff ect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator off set is trimmed so that under static condi- tions it trips when the feedback pin is 750mV, +1%. The on-time pulse from the SC410 in the design example is calculated to give a pseudo-fi xed frequency of 500kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regu- lation error. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1% feedback resistors may result in up to an additional 1% error. If tighter DC accuracy is required, resistors with lower tolerances should be used.

The output inductor value may change with current. This will change the output ripple and therefore will have a minor eff ect on the DC output voltage. The output ESR also aff ects the output ripple and thus has a minor eff ect on the DC output voltage. Switching Frequency Variation The switching frequency will vary depending on line and load conditions. The line variations are a result of fi xed propagation delays in the on-time one-shot, as well as unavoidable delays in the power FET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net eff ect is that frequency tends to fall slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the induc- tor. For a conventional PWM constant-frequency con- verter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V IN as losses increase). The on-time is essen- tially constant for a given V OUT and V IN combination, to off set the losses the off -time will tend to reduce slightly as load increases. The net eff ect is that switching frequency increases slightly with increasing load. Applications Information (continued)

Applications Information (continued) Figure 11 — PCB Layout SC410 LX connection using a Via FB node PGND VESR node PCB Layout Guidelines The optimum layout for the SC410 is shown in Figure 11. This layout shows an integrated FET buck regulator with a maximum current of 3A. The total PCB area is approxi- mately 19.1mm x 11.3mm. Critical Layout Guidelines The following critical layout guidelines must be followed to ensure proper performance of the device. IC Decoupling capacitors PGND plane AGND island FB and other analog control signals BST and LX Capacitors and Current Loops IC Decoupling Capacitors A 0.1 μF capacitor must be located as close as possible to the IC and directly connected to pins 10 (LDO) and 9 (AGND). All other decoupling capacitors must be located as close as possible to the IC. PGND Plane PGND requires its own copper plane with no other signal traces routed on it. Copper planes, multiple vias, and wide traces are needed to connect PGND to input capacitors, output capacitors, and the PGND pins on the IC. The PGND copper area between the input capacitors, output capacitors, and PGND pins must be as small as and as compact as possible to reduce the area of the PCB that is exposed to noise due to current fl ow on this node. Connect PGND to AGND with a short trace or resistor. This connection should be as close to the IC as possible. AGND Island AGND should have its own island of copper with no other signal traces routed on this layer that connects the AGND pins and pad of the IC to the analog control components. All of the components for the analog control cir- cuitry should be located so that the connections

Applications Information (continued) to AGND are done by wide copper traces or vias down to AGND. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the IC as possible. FB and Other Analog Control Signals The connection from the V OUT power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. The traces between V OUT and the analog control circuitry (AGND, and FB pins) must be as short as possible. The traces must also be routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. The TON node must be as short as possible to ensure the best accuracy for the on time. The feedback components for the switcher need to be as close to the FB pin of the IC as possible to reduce the possibility of noise corrupting these analog signals. BST and LX LX and BST are very noisy nodes and must be carefully routed to minimized the PCB area that is exposed to these signals. The connections for the boost capacitor between the IC and LX must be short and directly connected to the LX (pin 3). The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos- sibility of LX noise corrupting other signals. Capacitors and Current Loops The current loops between the input capacitors, the IC, the inductor, and the output capacitors must be as close as possible to each other to reduce IR drop across copper planes and traces. All bypass and output capacitors must be con- nected as close as possible to their respective pin on the IC.

Outline Drawing — MLPD-10 3x3 NOTES: CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.2. .003 .007 .009 .000 .031 (.008) 0.08 0.23 .011 0.18 .039 .002 0.00 0.80 0.30 0.05 1.00 (0.20) .004 0.10 0.50 BSC.020 BSC aaa C SEATING PLANE A bbb C A B B e C (LASER MARK) INDICATOR PIN 1 N MIN aaa bbb b e L N D A DIM MILLIMETERS NOM DIMENSIONS MAXNOM INCHES MIN MAX D E A LxN E/2 bxN D/2

Land Pattern — MLPD-10 3x3 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DIMENSIONS INCHES H K (C) Z C (.114) P FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. X NOTES: Y G X Z Y K P H G .012 .031 .146 .083 .020 .055 .087 DIM (2.90) 0.30 0.80 3.70 2.10 0.50 1.40 2.20 MILLIMETERS

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