SC402B

SC402B SEMTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Features

Input voltage — 3V to 28V Bias voltage — 3V to 5.5V LDO or external Up to 96% peak efficiency Integrated bootstrap switch Programmable LDO output — 200mA Reference tolerance — 1% TJ= -40 to +125 °C Programmable soft start time Logic Input/Output Control Independent EN controls for LDO and switcher Programmable VIN UVLO threshold Power good output Selectable PSAVE or FCM mode Protection Over-voltage and under-voltage TC compensated RDS(ON) sensed current limit Thermal Shutdown Output Capacitor Types High ESR — SP , POSCAP , OSCON Ceramic capacitors Package Lead-free package — 5x5mm, 32-Pin MLPQ RoHS/WEEE compliant and Halogen free

Applications

Networking and telecommunication equipment Printers, DSL, and STB applications Embedded systems and power supply modules Point of load power supplies

• •••
• ••

Description

The SC402B is a stand-alone synchronous EcoSpeed® buck power supply which incorporates Semtech’s advanced patented adaptive on-time control architecture. This pro- vides excellent light-load efficiency and fast transient response. It features integrated power MOSFETs, a boot - strap switch, and a programmable LDO in a 5x5mm package. The device is highly efficient and uses minimal PCB area. The SC402B has the same package and pin con- figuration as the entire SC40x series for compatibility. The SC402B supports using standard capacitor types such as electrolytic or specialty polymer, in addition to ceramic, at switching frequencies up to 1MHz. The programmable frequency, synchronous operation, and selectable power- save provide high efficiency operation over a wide load range. Additional features include a programmable soft-start, programmable cycle-by-cycle over-current limit protec - tion, under-voltage and over-voltage protection, soft shutdown, and selectable power-save operation. The device also provides separate enable inputs for the PWM controller and LDO as well as a power good output for the PWM controller. The wide input and programmable frequency make the device extremely flexible and easy to use in a broad range of applications. Rev. 2.1 POWER MANAGEMENT RTON SC402B FB VOUT VDD VIN SS BST PGND LX PGOOD ILIM LXS EN/PSV ENL LXBST RILIM CBST ENABLE/PSAVE ENABLE LDO VEXT/LDO AGND +RFB1 RFB2 VOUT COUT CIN VIN PGOODTON 1µF CSOFT 10Ω Typical Application Circuit SC402B 10A EcoSpeed® Integrated FET Regulator with Programmable LDO

Pin Configuration Ordering Information Marking Information SC402B yyww xxxxxx xxxxxx AGND PAD 1 VIN PAD 2 LX PAD 3 ENL TON AGND EN/PSV LXS ILIM PGOOD LX 24 LX LX23 PGND22 PGND21 PGND20 PGND19 PGND18 PGND17 PGND PGND DL LXBST DH VIN VIN VIN BST 8 FBL 5 SS 7 VIN 6 VDD 3 AGND 4 FB 1 Top View VOUT 2 Notes: 1) Available in tape and reel only. A reel contains 3000 devices. 2) Lead-free, Halogen free, and RoHS/WEEE compliant yyww = Date Code xxxxxx = Semtech Lot Number xxxxxx = Semtech Lot Number SC402B MLPQ-32; 5x5, 32 LEAD Device Package SC402BMLTRT(1)(2) MLPQ-32 5X5 SC402BEVB Evaluation Board

Recommended Operating Conditions Thermal Information Thermal resistance, junction to ambient (2) (°C/W) Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Unless specified: VIN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, VDD = +5V, Typical Application Circuit

Electrical Characteristics

Parameter Conditions Min Typ Max Units Input Supplies Input Supply Voltage VIN > VDD 3 28 V VDD Voltage 3 5.5 V VIN UVLO Threshold(1) Sensed at ENL pin, rising edge 2.40 2.60 2.95 V Sensed at ENL pin, falling edge 2.23 2.40 2.57 VIN UVLO Hysteresis EN/PSV = High 0.25 V VDD UVLO Threshold Measured at VDD pin, rising edge 2.5 3.0 V Measured at VDD pin, falling edge 2.4 2.9 VDD UVLO Hysteresis 0.2 V VIN Supply Current ENL , EN/PSV = 0V, VIN = 28V 10 20 μA Standby mode; ENL=VDD, EN/PSV = 0V 130

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Input Supplies (continued) VDD Supply Current ENL , EN/PSV = 0V, no external 5V VDD 3 7 μA ENL , EN/PSV = 0V, external 5V VDD supply 190 300 EN/PSV = VDD (PSAVE), No load, VFB > 600mV 0.7 mAVDD = 5V, fSW = 250kHz, EN/PSV = floating , no load(2) 8 VDD = 3V, fSW = 250kHz, EN/PSV = floating , no load(2) 5 FB On-Time Threshold Static VIN and load, TJ = 0 to +125 °C 0.595 0.6 0.605 V Static VIN and load, TJ = 40 to +125 °C 0.594 0.6 0.606 V Frequency Range Continuous mode operation (FCM) 1000 kHz Bootstrap Switch Resistance 10 Ω Timing On-Time Continuous mode operation, VIN = 12V, VOUT = 5V, fSW= 300kHz, RTON = 133kΩ 999 1110 1220 ns Minimum On-Time (2) 80 ns Minimum Off-Time (2) VDD = 5V 250 ns VDD = 3V 370 Soft-Start Soft-Start Current 3.0 µA Soft-Start Voltage(2) When VOUT reaches regulation 1.5 V Analog Inputs/Outputs VOUT Input Resistance 500 kΩ Current Sense Zero-Crossing Detector Threshold LX - PGND -3 0 +3 mV Power Good Power Good Threshold Upper limit, VFB > internal 600mV reference +20 % Lower limit, VFB < internal 600mV reference -10 % Start-Up Delay Time (between PWM enable and PGOOD high) VDD = 5V, CSS = 10nF 12 ms VDD = 3V, CSS = 10nF 7

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Power Good (continued) Power Good start-up Delay Threshold on SS pin SS voltage when PGOOD goes high 64 %VDD Fault (noise immunity) Delay Time(2) 5 µs Leakage 1 µA Power Good On-Resistance 10 Ω Fault Protection Valley Current Limit (3) VDD = 5V, RILIM = 6810, TJ = 0 to +125 °C 8.5 10 11.5 A VDD = 3V, RILIM = 6810 9 ILIM Source Current 10 μA ILIM Comparator Offset With respect to AGND -10 0 +10 mV Output Under-Voltage Fault VFB with respect to internal 600mV reference, 8 consecutive clocks -25 % Smart Power-save Protection Threshold (2) VFB with respect to internal 600mV reference +10 % Over-Voltage Protection Threshold VFB with respect to internal 600mV reference +20 % Over-Voltage Fault Delay(2) 5 μs Over-Temperature Shutdown(2) 10°C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage ENL 1.0 V Logic Input Low Voltage ENL 0.4 V EN/PSV Input for PSAVE Operation (2) VDD = 5V 2.2 5 V EN/PSV Input for Forced Continuous Operation (2) 1 2 V EN/PSV Input for Disabling Switcher 0 0.4 V EN/PSV Input Bias Current EN/PSV= VDD or AGND -10 +10 μA ENL Input Bias Current ENL = VIN = 28V 10 18 μA FBL, FB Input Bias Current FBL, FB = VDD or AGND -1 +1 μA

Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Linear Regulator (LDO) FBL Accuracy VLDO load = 5mA 0.728 0.75 0.773 V LDO Current Limit Short-circuit protection, VIN = 12V, VDD < 0.75V 65 mA Start-up and foldback, VIN = 12V, 0.75 < VDD < 90% of final VDD value 115 Operating current limit, VIN = 12V, VDD > 90% of final VDD value 135 200 VLDO to VOUT Switch-over Threshold (4) -130 +130 mV VLDO to VOUT Non-switch-over Threshold (4) -500 +500 mV VLDO to VOUT Switch-over Resistance VOUT = +5V 2 Ω LDO Drop Out Voltage (5) From VIN to VDD, VDD = +5V, IVLDO = 100mA 1.2 V Notes: (1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. (2) Typical value measured on standard evaluation board. (3) SC402B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout. (4) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. (5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.

130KΩ SC402B FB1 VOUT2 VDD3 AGND4 FBL5 VIN6 SS7 BST8 VIN9 VIN10 VIN11 PGND15 PGND16 PGND 22 LX 23 LX 24 LX 25 PGOOD 26 ILIM 27LXS 28EN/PSV 29 AGND 30 TON 31ENL 32 DL14 LXBST13 DH12 VINPAD 2 AGNDPAD 1 LX PAD 3 RILIM 7.68KΩ RLDO2 75KΩ RLDO1 422KΩ CIN 2 x 10µF (see note ) RGND CBST 1µF VIN +12V PGND PGND PGND PGND PGND CFF 100pF RFB1 10KΩ 1µH RFB2 6.65KΩ VOUT 1.5V @ 10A, 300kHz ENABLE/PSAVE ENABLE LDO +COUT 9mΩ 330µF PGOOD 1µF Component Value Manufacturer Part Number Web CIN (see note) 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com www.panasonic.com Key Components NOTE: The quantity of 10µF input capacitors required varies with the application requirements. www.cyntec.com Internal LDO Used as Bias 3.3nF 22µF 1µF COUT 330µF/9mΩ Panasonic EEF-SX0E331ER PIMB104T-1R0MS1.0µH/3mΩ CyntecL1 RBST Detailed Application Circuit — 1

130KΩ SC402B FB1 VOUT2 VDD3 AGND4 FBL5 VIN6 SS7 BST8 VIN9 VIN10 VIN11 PGND15 PGND16 PGND 22 LX 23 LX 24 LX 25 PGOOD 26 ILIM 27LXS 28EN/PSV 29 AGND 30 TON 31ENL 32 DL14 LXBST13 DH12 VINPAD 2 AGNDPAD 1 LX PAD 3 RILIM 7.68KΩ 10Ω CIN 2 x 10µF (see note ) RGND 0CBST 1µF VIN +12V PGND PGND PGND PGND PGND CFF 100pF RFB1 10KΩ 1µH RFB2 6.65KΩ VOUT 1.5V @ 10A, 300kHz ENABLE/PSAVE +COUT 9mΩ 330µF PGOOD 1µF Component Value Manufacturer Part Number Web CIN (see note) 2 x 10µF/25V Murata GRM32DR71E106KA12L www.murata.com www.panasonic.com Key Components NOTE: The quantity of 10µF input capacitors required varies with the application requirements. www.cyntec.com External 3.3V - 5V Used as Bias 3.3nF 22µF 1µF COUT 330µF/9mΩ Panasonic EEF-SX0E331ER PIMB104T-1R0MS1.0µH/3mΩ CyntecL1 RBST Detailed Application Circuit — 2

Efficiency/Power Loss vs. Load — PSAVE Mode 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 PLoss (W) PLOSS Efficiency VIN = 12V VIN = 12V VIN = 5V VIN = 5V Characteristics in this section are based on using the Typical Application Circuit on page 8. 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) -0.0250 0.0075 0.0400 0.0725 0.1050 0.1375 0.1700 0.2025 0.2350 0.2675 0.3000 PLOSS (W) PSAVE FCM FCM minus PSM 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) -0.0250 0.0075 0.0400 0.0725 0.1050 0.1375 0.1700 0.2025 0.2350 0.2675 0.3000 PLOSS (W) PSAVE FCM FCM minus PSM 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 Power Loss (W) PLOSS Efficiency VIN = 18V VIN = 12V VIN = 18V VIN = 12V VIN = 5V VIN = 5V 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 PLOSS (W) PLOSS Efficiency VIN = 18V VIN = 12V VIN = 18V VIN = 12V VIN = 5V VIN = 5V 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 PLOSS (W) 3.3V Bias 3.3V minus 5V 5V Bias Efficiency/Power Loss vs. Load — PSAVE Mode Efficiency/Power Loss vs. Load — FCM Efficiency/Power Loss — PSAVE vs. FCM Efficiency/Power Loss — PSAVE vs. FCM Efficiency/Power Loss — PSAVE VDD = 3.3V, VOUT = 1.5V VDD = 5V, VOUT = 1.5V VDD = 5V, VOUT = 1.5V VDD = 3.3V, VOUT = 1.5V, VIN = 12V VDD = 5V, VOUT = 1.5V, VIN = 12V VOUT = 1.5V, VIN = 12V

Typical Characteristics (continued) Load Regulation — FCM 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) VIN = 18V VIN = 12V VIN = 5V Characteristics in this section are based on using the Typical Application Circuit on page 8. 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) VIN = 18V VIN = 12V VIN = 5V 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Switching Frequency (kHz) PSAVE FCM Load Regulation — FCM Load Regulation — PSAVE Mode Switching Frequency — PSAVE Mode vs. FCM Switching Frequency — PSAVE Mode vs. FCM VDD = 5V, VOUT = 1.5V VDD = 5V, VOUT = 1.5V VDD = 5V, VOUT = 1.5V, VIN = 12V 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) VIN = 12V VIN = 5V 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) VIN = 12V VIN = 5V VDD = 3.3V, VOUT = 1.5V 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Switching Frequency (kHz) PSAVE FCM VDD = 3.3V, VOUT = 1.5V Load Regulation — PSAVE VDD = 3.3V, VOUT = 1.5V

Typical Characteristics (continued) Load Regulation vs. Temperature — FCM Characteristics in this section are based on using the Typical Application Circuit on page 8. 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) TA = -40°CVIN = 12V TA = 25°CVIN = 5V TA = 25°CVIN = 12V TA = 25°CVIN = 18V TA = -40°CVIN = 5V TA = -40°CVIN = 18V TA = 85°CVIN = 12V TA = 85°CVIN = 18V TA = 85°CVIN = 5V Load Regulation vs. Temperature — FCM Load Regulation vs. Temperature — PSAVE VDD = 5V, VOUT = 1.5V 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) TA = -40°CVIN = 12V TA = 25°CVIN = 5V TA = 25°CVIN = 12V TA = -40°CVIN = 5V TA = 85°CVIN = 12V TA = 85°CVIN = 5V VDD = 3.3V, VOUT = 1.5V 100 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Efficiency (%) VOUT = 1V VOUT = 5V VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V Efficiency Variation with VOUT— PSAVE VDD = 5V, VIN = 12V, L = 2.2uH (4.6m Ω) for VOUT = 2.5V, 3.3V and 5V VDD = 5V, VOUT = 1.5V 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) TA = -40°CVIN = 12V TA = 25°CVIN = 5V TA = 25°CVIN = 12V TA = -40°CVIN = 5V TA = 85°CVIN = 12V TA = 85°CVIN = 5V Load Regulation vs. Temperature — PSAVE VDD = 5V, VOUT = 1.5V Efficiency/Power Loss vs. Load — PSAVE Mode 100 IOUT (A) Efficiency (%) 0.000 0.035 0.070 0.105 0.140 0.175 0.210 0.245 0.280 0.315 0.350 PLOSS (W) LDO minus External External Bias LDO Bias VDD = 5V, VIN = 12V, VOUT = 1.5V 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 1 2 3 4 5 6 7 8 9 10 IOUT (A) Vout (V) TA = -40°CVIN = 12V TA = 25°CVIN = 5V TA = 25°CVIN = 12V TA = 25°CVIN = 18V TA = -40°CVIN = 5V TA = 85°CVIN = 12V TA = 85°CVIN = 18V TA = 85°CVIN = 5V TA = -40°CVIN = 18V

Start-up — EN/PSV Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Shutdown — EN/PSV Time (2ms/div)s/div)/div) (5V/div) (1V/div) (500mV/div) (5V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A Power Save Mode Time (5ms/div)s/div)/div) (50mV/div) (5V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A Forced Continuous Mode Time (2μs/div)s/div)/div) (50mV/div) (5V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A Over Current Protection — Under-Voltage Protection Time (100μs/div)s/div)/div) (5V/div) (500mV/div) (5A/div) (10V/div) VIN = 12V, VOUT = 1.5V, IOUT = OC regulated at 10.15A Start-up (Pre-Bias) — EN/PSV Time (1ms/div)s/div)/div) (5V/div) (1V/div) (500mV/div) (5V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A 2.2ms Time (2 ms/div)s/div)/div) (5V/div) (1V/div) (500mV/div) (5V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A 27ms 15.10A 10.15A

Typical Characteristics (continued) Characteristics in this section are based on using the Typical Application Circuit on page 8. Rising Edge Dead-time — LX Time (10ns/div)s/div)/div) (1V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A Transient Response — PSAVE Load Rising Time (10μs/div)s/div)/div) (5A/div) (50mV/div) (10V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0.5A to 8.5A, di/dt = 1A/μss Falling Edge Dead-time — LX Time (10ns/div)s/div)/div) (1V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A Transient Response — FCM Time (20μs/div)s/div)/div) (5A/div) (50mV/div) (10V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 2.5A to 10A, di/dt = 1A/μss Transient Response — PSAVE Load Falling Time (10μs/div)s/div)/div) (5A/div) (50mV/div) (10V/div) VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 8.5A to 0.5A, di/dt = 1A/μss Over Temperature Shutdown — 159ºC Time (500μs/div)s/div)/div) (10V/div) (2V/div) VIN = 12V, VOUT = 1.5V, IOUT = 0A, LDO mode 16ns 12ns 811kHz 74mV (1V/div) (1V/div) 74mV

Pin # Pin Name Pin Function 1 FB Feedback input for switching regulator used to program the output voltage — connect to an external resis- tor divider from VOUT to AGND. 2 VOUT Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin. 3 VDD Bias supply for the IC — when using the internal LDO as a bias power supply, VDD is the LDO output. When using an external power supply as the bias for the IC, the LDO output should be disabled. 4, 30, PAD 1 AGND Analog ground 5 FBL Feedback input for the internal LDO — used to program the LDO output. Connect to an external resistor divider from VDD to AGND. 6, 9-11, PAD 2 VIN Input supply voltage 7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin. 8 BST Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the high-side gate drive.

12 DH High-side gate drive

13 LXBST LX Boost — connect to the BST capacitor. 23-25, PAD 3 LX Switching (phase) node

14 DL Low-side gate drive

26 PGOOD Open-drain power good indicator — high impedance indicates power is good. An external pull-up resistor is required. 27 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.

28 LXS LX sense — connects to RILIM

29 EN/PSV Enable/power save input for the switching regulator — connect to AGND to disable the switching regulator, connect to VDD to operate with power save mode and float to operate in forced continuous mode.

31 TON On-time programming input — set the on-time by connecting through a resistor to AGND

32 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic con- trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.

Control & Status PGOOD Gate Drive Control VIN PGND TON VOUT Zero Cross Detector Valley Current Limit ILIM ENL FBL VLDO Switchover MUX A Y B LDO VDD BST FB Comparator LX EN/PSV Bypass ComparatorBypass Comparator DH DL A 26 29 A = connected to pins 6, 9-11, PAD 2 B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 B C D VIN VDD VDD VIN Bootstrap Switch Lo-side MOSFET Hi-side MOSFET LXBST13 LXS28 DL DL VDD VDD VDD SS 7

Synchronous Buck Converter The SC402B is a step down synchronous DC-DC buck converter with integrated power MOSFETs and a 200mA capable programmable LDO. The device is capable of 10A operation at very high efficiency. A space saving 5x5 (mm) 32-pin package is used. The programmable operating frequency of up to 1MHz enables optimizing the configu- ration for PCB area and efficiency. The buck controller uses a pseudo-fixed frequency adap- tive on-time control. This control method allows fast tran- sient response which permits the use of smaller output capacitors. In addition to the following information, the user can click on the applicable link to go to the SC402B online C-SIM design and simulation tool, which will lead the user through the design process. Input Voltage Requirements The SC402B requires two input supplies for normal opera- tion: VIN and VDD. VIN operates over a wide range from 3V to 28V. VDD requires a 3V to 5.5V supply input that can be an external source or the internal LDO configured to supply 3V to 5.5V from VIN. Power Up Sequence When the SC402B uses an external power source at the VDD pin, the switching regulator initiates the start up when V IN, VDD and EN/PSV are above their respective thresholds. When EN/PSV is at a logic high, VDD needs to be applied after V IN rises. It is also recommended to use a10Ω resistor between an external power source and the VDD pin. To start up by using the EN/PSV pin when both VDD and VIN are above their respective thresholds, apply EN/PSV to enable the start-up process. For SC402B in self- biased mode, refer to the LDO section for a full description. Shutdown The SC402B can be shutdown by pulling either VDD or EN/PSV below its threshold. When using an external power source, it is recommended that the VDD voltage ramps down before the V IN voltage. When VDD is active and EN/PSV at low logic, the output voltage discharges into the VOUT pin through an internal FET. Psuedo-fixed Frequency Adaptive On-time Control The PWM control method used by the SC402B is pseudo- fixed frequency, adaptive on-time, as shown in Figure 1. The ripple voltage generated at the output capacitor ESR is used as a PWM ramp signal. This ripple is used to trigger the on-time of the controller. L COUT ESR CIN VOUT FB Threshold VFB VLX VLX TON FB VIN Figure 1 — PWM Control Method, VOUT Ripple The adaptive on-time is determined by an internal one- shot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- side MOSFET. The pulse period is determined by VOUT and VIN; the period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time arrangement, the device automatically antici - pates the on-time needed to regulate VOUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: Predictable operating frequency compared to other variable frequency methods Reduced component count by eliminating the error amplifier and compensation components Reduced component count by removing the need to sense and control inductor current Fast transient response — the response time is controlled by a fast comparator instead of a typi- cally slow error amplifier. Reduced output capacitance due to fast tran - sient response Applications Information

through the SS pin to charge the capacitor. During the start up process (Figure 8), 50% of the voltage at the SS pin is used as the reference for the FB comparator. The PWM comparator issues an on-time pulse when the voltage at the FB pin is less than 40% of the SS pin. As a result, the output voltage follows the SS voltage. The output voltage reaches and maintains regulation when the soft start voltage is > 1.5V. The time between the first LX pulse and VOUT reaching regulation is the soft-start time (tSS). The calculation for the soft-start time is shown by the following equation. V5.1Ct SSSS Pu The voltage at the SS pin continues to ramp up and eventu- ally equals 64% of VDD. After the soft start completes, the FB pin voltage is compared to an internal reference of 0.6V. The delay time between the VOUT regulation point and PGOOD going high is shown by the following equation. )V5.1V64.0(Ct DDSS DELAY-PGOOD P uu Figure 8 — Soft-start Timing Diagram Pre-Bias Startup The SC402B can start up normally even when there is an existing output voltage present. The soft start time is still the same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up when 40% of the voltage at SS pin meets the existing FB voltage level. Pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. This method prevents the output voltage from discharging. Power Good Output The PGOOD (power good) output is an open-drain output which requires a pull-up resistor. When the voltage at the FB pin is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns above -8% of nominal. PGOOD will transition low if the V FB pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh- old. PGOOD also pulls low if the EN/PSV pin is low when VDD is present. Output Over-Voltage Protection Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 600mV + 20% (720mV). When VFB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls 25% below its nominal voltage (falls to 450mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tri- state the MOSFETs. The controller stays off until EN/PSV is toggled or VDD is cycled. VDD UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the DH/DL drivers until VDD rises above 3.0V. An internal POR (Power-On Reset) occurs when VDD exceeds 3.0V, which resets the fault latch and a soft-start counter cycle begins which prepares for soft-start. The SC402B then begins a soft-start cycle. The PWM will shut off if VDD falls below 2.4V. Applications Information (continued)

Applications Information (continued) There are two values of load current to evaluate — con - tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. VIN = 12V + 10% VOUT = 1.5V + 4% fSW = 300kHz Load = 10A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 300kHz which results from using components selected for optimum size and cost. A resistor (RTON) is used to program the on-time (indirectly setting the frequency) using the following equation. SW TON fpF25 kR u To select RTON, use the maximum value for V IN, and for TON use the value associated with maximum VIN. SWINMAX OUT ON fV VT u TON = 379 ns at 13.2VIN, 1.5VOUT, 300kHz Substituting for RTON results in the following solution. RTON = 133.3kΩ, use RTON = 130kΩ Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple

• ••• current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for PSAVE operation. The switching will typically enter PSAVE mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then PSAVE will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the on-time, voltage across the inductor is (VIN - V OUT ). The equation for determining inductance is shown next. RIPPLE ONOUTIN I T)VV(L u Example In this example, the inductor ripple current is set equal to 45% of the maximum load current. Therefore ripple current will be 45% x 10A or 4.5A. To find the minimum inductance needed, use the VIN and TON values that corre- spond to VINMAX. H99.0A5.4 ns379)5.12.13(L P u A slightly larger value of 1µH is selected. This will decrease the maximum IRIPPLE to 4.43A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current.

Applications Information (continued) The ripple current under minimum V IN conditions is also checked using the following equations. ns451V VRpF25T INMIN OUTTON VINMIN_ON uu L T)VV(I ONOUTIN RIPPLE u A19.4H1 ns451)5.18.10(I VINMIN_RIPPLE P u Capacitor Selection The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to- peak ripple. A change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal for output voltage ripple is 3% of 1.5V or 45mV. The maximum ESR value allowed is shown by the following equations. A43.4 mV45 I VESR RIPPLEMAX RIPPLE MAX ESRMAX = 10.2 mΩ The output capacitance is usually chosen to meet tran - sient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. OUT PEAK RIPPLEMAXOUT MIN VV 1IL COUT § u Assuming a peak voltage VPEAK of 1.65V (150mV rise upon load release), and a 10A load release, the required capaci- tance is shown by the next equation. MIN 5.165.1 43.42 110H1 COUT § uP COUTMIN = 316µF During the load release time, the voltage cross the induc- tor is approximately -V OUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt of the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capaci- tance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 10 + 1/2 x 4.43 = 12.215A dt dlCurrentLoadofchangeofRate LOAD IMAX = maximum load release = 10A OUTPK LOAD MAX OUT LPK LPKOUT VV2 dtdl I V IL IC uu u Example A5.2 dt dlLOAD P This would cause the output current to move from 10A to 0A in 4µs, giving the minimum output capacitance requirement shown in the following equation. 5.165.12 s15.2 5.1 215.12H1 215.12COUT PuuP u COUT = 169 µF

Applications Information (continued) Note that C OUT is much smaller in this example, 169µF compared to 316µF based on a worst-case load release. To meet the two design criteria of minimum 316µF and maximum 10.2mΩ ESR, select one capacitor of 330µF and 9mΩ ESR. It is recommended that an additional small capacitor be placed in parallel with COUT in order to filter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect opera - tion. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also impera- tive to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis - tor, as shown in Figure 12. This capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional con - nection on the PCB should be available for this capacitor. VOUT To FB pin CTOP Figure 12 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking sta- bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insuffi - cient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and dis - charging during the switching cycle. For most applica - tions the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre - quency. The formula for minimum ESR is shown by the following equation. swOUT MIN fC2 3SRE uuSu Using Ceramic Output Capacitors When the system is using high ESR value capacitors, the feedback voltage ripple lags the phase node voltage by 90 degrees. Therefore, the converter is easily stabilized. When the system is using ceramic output capacitors, the ESR value is normally too small to meet the above ESR cri- teria. As a result, the feedback voltage ripple is 180 degrees from the phase node and behaves in an unstable manner. In this application it is necessary to add a small

Applications Information (continued) SC402B regulates to the valley of the ripple voltage at the FB pin, a high ripple magnitude is undesirable as it signifi- cantly impacts the output voltage regulation. As a result, it is desirable to select a corner frequency for (R1// R2) x CC to achieve enough, but not excessive, ripple magnitude and phase margin. The component values for R 1, R2, and CC should be calculated using the following procedure. Select C L (typical 10nF) and R L to match with L and DCR time constant using the following equation. L L CDCR LR u Select CC by using the following equation. sw21 C R//R 1C uSuu| The resistor values (R1 and R2) in the voltage divider circuit set the V OUT for the switcher. The typical value for C C is from 10pF to 1nF. Dropout Performance The output voltage adjustment range for continuous con- duction operation is limited by the fixed 250ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calcu - lated using worst-case values for on and off times. The duty-factor limitation is shown by the next equation. )MAX(OFF)MIN(ON )MIN(ON TT TDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static condi - tions it trips when the feedback pin is 750mV, 1%. The on-time pulse from the SC402B in the design example is calculated to give a pseudo-fixed frequency of 300kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regu- lation error. For example, if the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25V, then the measured DC output will be 40mV above the comparator trip. The best way to mini - mize this effect is to minimize the output ripple. The use of 1% feedback resistors may result in up to 1% error. If tighter DC accuracy is required, 0.1% resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency varies with load current as a result of the power losses in the MOSFETs and DCR of the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. An adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essen - tially constant for a given V OUT/VIN combination, to offset the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load.

Applications Information (continued) PCB Layout Guidelines The optimum layout for the SC402B is shown in Figure 17. This layout shows an integrated FET buck regulator with a maximum current of 10A. The total PCB area is approxi - mately 25 x 29 mm with single side components. Critical Layout Guidelines The following critical layout guidelines must be followed to ensure proper performance of the device. IC Decoupling capacitors PGND plane AGND island FB, VOUT, and other analog control signals CSS BST, ILIM, and LX CIN and COUT placement and Current Loops IC Decoupling Capacitors A 1 μF capacitor must be located as close as pos- sible to the IC and directly connected to pins 3 (VDD) and 4 (AGND). Another 1 μF capacitor must be located as close as possible to the IC and directly connected to pins 3 (VDD) and PGND plane. PGND Plane PGND requires its own copper plane with no other signal traces routed on it. Copper planes, multiple vias and wide traces are needed to connect PGND to input capacitors, output capacitors, and the PGND pins on the IC. The PGND copper area between the input capacitors, output capacitors and PGND pins must be as tight and compact as possible to reduce the area of the PCB that is exposed to noise due to current flow on this node. VOUT Plane on top and bottom layer L CIN Css RFB2 RFB1 RILIM CBST LX plane on top and bottom layer All components shown Top Side AGND plane on inner layer VIN plane on top and/or bottom layer RGND — AGND connects to PGND close to IC Pin 1 marking IC with vias for LX, AGND, VIN COUT PGND on inner or bottom layer Vout sense trace on inner layer VDD Decoupling Capacitor VDD Cer. CIN SP or POSCAP RTON CTOP PGND on top layer RGND Figure 17 — PCB Layout

AGND should have its own island of copper with no other signal traces routed on this layer that connects the AGND pins and pad of the IC to the analog control components. All of the components for the analog control cir- cuitry should be located so that the connections to AGND are done by wide copper traces or vias down to AGND. Connect PGND to AGND with a short trace or 0Ω resistor. This connection should be as close to the IC as possible. FB, VOUT, and Other Analog Control Signals The connection from the V OUT power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. The traces between Vout and the analog control circuitry (VOUT, and FB pins) must be wide, short and routed away from noise sources, such as BST, LX, VIN, and PGND between the input capacitors, output capacitors, and the IC. The feedback components for the switcher and the LDO need to be as close to the FB and FBL pins of the IC as possible to reduce the possibil - ity of noise corrupting these analog signals. BST, ILIM,TON,SS and LX The connections for the boost capacitor between the BST and LXBST must be short, wide and directly connected. ILIM and TON nodes must be as short as possible to ensure the best accuracy in current limit and on time. RILIM should be close to the IC and connected between LXS (pin 28) and ILIM (pin 27) only. RTON should be close to the IC and connected between TON (pin 31) and AGND (pin 30). CSOFT should be close to the IC and kept away from the boost capacitor. Connect the AGND end of CSOFT to the AGND plane at pin 4. The LX node between the IC and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos - sibility of LX noise corrupting other signals. Multiple vias should be used on the LX PAD to provide good thermals and connection to an internal or bottom layer LX plane. Capacitors and Current Loops Figure 17 shows the placement of input/output capacitors and inductor. This placement shows the smallest current loops between the input/ output capacitors, the SC402B and the inductor to reduce the IR drop across the copper. Applications Information (continued)

Outline Drawing — MLPQ-5x5-32 B aaa C C SEATING PLANE N bbb C A B COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). NOTES: A PIN 1 INDICATOR (LASER MARK) D E bxN A e LxN 0.76 0.76 3.48 1.05 1.66 1.49 PIN 1 IDENTIFICATION R0.20 3.61 MILLIMETERS

0.50 BSC

.002- 0.00.000A1 .193 .193 .135 .076 .012 .007 aaa bbb N e L D E b .020 BSC .137 .016 .003 .004 .197 (.008) .078 .197 .010 3.43.139 .020 0.30 .201 .201 .080 .012 4.90 4.90 1.92 0.18 .031 MINDIM A MAX DIMENSIONS INCHES NOM .039 0.80 MIN - 0.05 5.10 5.10 3.53 2.02 0.50 0.30 3.48 0.40 0.10 0.08 5.00 (0.20) 1.97 5.00 0.25 1.00 MAX NOM

1.74 3.48 K 3.61 Y H(C) G THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P C G MILLIMETERSINCHES (4.95) .012 .030 .165 .020 .078 .137 (.195) 0.30 0.75 3.48 0.50 1.97 4.20 DIMENSIONS COMPANY'S MANUFACTURING GUIDELINES ARE MET. 5.70.224Z FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD3. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. X P Z H1 .059 1.49 H2 .065 1.66 K1 .041 1.05 1.74 Land Pattern — MLPQ-5x5-32

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse - quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.