SC3017B MURATA | Alldatasheet
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Technical content
www.RFM.com E-mail: info@rfm.com Page 1 of 2 ©2008 by RF Monolithics, Inc. SC3017B - 3/27/08
Electrical Characteristics
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. NOTES: Characteristic Sym Notes Minimum Typical Maximu Units Output Frequency Absolute Frequency f O 1, 2 399.920 400.080 MHz Tolerance from 400.000 MHz ΔfO ±200 ppm Q and Q Output Voltage into 50Ω (VSWR ≤ 1.2) V O 1, 3 0.60 1.1 VP-POperating Load VSWR 2:1 Symmetry 3, 4, 5 49 51 % Harmonic Spurious 3, 4, 6 -25 -20 dBc Nonharmonic Spurious -60 dBc Q and Q Period Jitter No Noise on VCC 3, 4, 6, 7 15 30 ps P-P 200 mVP-P from 1 MHz to ½ fO on 3, 4, 7, 8 35 ps P-P Output (Disabled) Amplitude into 50 Ω 3, 9 75 mV P-P Output DC Resistance (between Q & Q ) 3 50 K Ω ENABLE (Terminal 14) Input HIGH Voltage V IH 3, 9 VCC-0.1 V CC VCC+0.1 V Input LOW Voltage V IL 0.0 0.20 V Input HIGH Current I IH 35 m A Input LOW Current I IL -1 mA Propagation Delay t PD 1 ms DC Power Supply Operating Voltage V CC 1, 3 Operating Current I CC 20 40 mA Operating Ambient Temperature T A 1, 3 0 +70 °C Lid Symbolization (YY = Year, WW = Week) RFM SC3017B 400.00 MHz YYWW
- Quartz SAW Frequency Stability Fundamental Fixed Frequency Very Low Jitter and Power Consumption Rugged, Miniature, Surface-Mount Case Low-Voltage Power Supply (3.3 VDC) This digital clock is designed for use with high-speed CP Us and digitizers. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology . The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving 50 Ω loads. Absolute Maximum Ratings Rating Value Units Power Supply Voltage (VCC at Terminal 1) 0 to +4.0 VDC Input Voltage (ENABLE at Terminal 8) 0 to +4.0 VDC Case Temperature (Powered or Storage) -40 to +85 °C
400.0 MHz
- Unless otherwise noted, all specifications include any combination of load VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to ground. (See: Typical Test Circuit.) 2. One or more of the following United States patents apply: 4,616,197; 3. The design, manufacturing process, and specifications of this device are subject to change without notice. 4. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and nominal power supply voltage. 5. Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q . (See: Timing Definitions.) 6. Jitter and other spurious output s induced by externally generated electrical noise on VCC or mechanical vibration are not included. Dedicated external voltage regulation and careful PCB layout are recommended for optimum performance. 7. Applies to period jitter of Q and Q . Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples. 8. Period jitter measured with a 200 mV P-P sine wave swept from 1 MHz to one-half of fO at the VCC power supply terminal. 9. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is defined as the time from the 50% point on the rising edge of ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point. (SEE: Timing Definitions.)
www.RFM.com E-mail: info@rfm.com Page 2 of 2 ©2008 by RF Monolithics, Inc. SC3017B - 3/27/08 Electrical Connections Case Design All pads consist of 30 microinches (min) electroless gold on 50 microinches (min) electroless nickel over base metal. The metallic center pad was designed for mechanical support. Grounding of this pad is optional. Lid symbolization, including terminal 1 locator dot, are in contrasting ink. Symbolization varies by model number. For purposes of illustration, only terminal 1 dot is shown. Footprint Actual size footprint: Typical Printed Circuit Board Land Pattern A typical land pattern for a circuit board is shown below. Grounding of the metallic center pad is optional. Typical Test Circuit Timing Definitions TOP VIEW A B N J L (X2) D (X8) K (X8) C H G M (X3) E F Typically 0.01" to 0.05" or 0.25 mm to 1.25 mm (8 Places) (The optimum value of this dimension is dependent on the PCB assembly process employed.) Clock Under Test Q Tektronix CSA 803 Digitizing Oscilloscope Ch 2 ENABLE Vcc Q Ch 150 Ω Trigger *Power Splitter, Mini-Circuits ZFSC2-4 0.1 μF Sine-Wave Signal Generator4.7 μH 50 Ω 50 Ω Vcc t PD Propagation Delay: 50% ENABLE Q or Q Output Amplitude Envelope 50% 90% 10% Symmetry: 50% 50% Q or Q Output 50% Symmetry as % of Period Period Symmetry as % of Period t PD Terminal Number Connection 1V CC
2 Ground
3 NC or Ground
4 Q Output
6 Ground7
Dimensions Millimeters Inches Min Max Min Max A 13.46 13.97 0.530 0.550 B 9.14 9.66 0.360 0.380 C 2.05 Nominal 0.081 Nominal D 3.56 Nominal 0.141 Nominal E 2.24 Nominal 0.088 Nominal F 1.27 Nominal 0.050 Nominal G 2.54 Nominal 0.100 Nominal H 3.05 Nominal 0.120 Nominal J 1.93 Nominal 0.076 Nominal K 5.54 Nominal 0.218 Nominal L 4.32 Nominal 0.170 Nominal M 4.83 Nominal 0.190 Nominal N 0.50 Nominal 0.020 Nominal