SC28C198A1A

SC28L198 PHILIPS | Alldatasheet

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Technical content

Octal UART for 3.3V and 5V supply voltage Product specification Supersedes data of 1998 Nov 04 IC19 Data Handbook

1999 Jan 14

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

21999 Jan 14 853–2047 20654

BRG Counters (Used for random baud rate generation) 8 Device Configuration after Hardware Reset or CRa cmd=x1F 41

DESCRIPTION

The Philips 28L198 Octal UART is a single chip CMOS–LSI communications device that provides 8 full-duplex asynchronous channels with significantly deeper 16 byte FIFOs, Automatic in–band flow control using Xon/Xoff characters defined by the user and address recognition in the wake up mode. Synchronous bus interface is used for all communication between host and OCTART. It is fabricated using Philips 1.0 micron CMOS technology that combines the benefits of low cost, high density and low power consumption. The operating speed of each receiver and transmitter can be selected independently from one of 22 fixed baud rates, a 16X clock derived from one of two programmable baud rate counters or one of three external 16X clocks (1 available at 1x clock rate). The baud rate generator and counter can operate directly from a crystal or from seven other external or internal clock inputs. The ability to independently program the operating speed of the receiver and transmitter makes the Octal UART particularly attractive for dual speed full duplex channel applications such as clustered terminal systems. The receivers and transmitters are buffered with FIFOs of 16 characters to minimize the potential for receiver overrun and to reduce interrupt overhead. In addition, a handshaking capability and in–band flow control are provided to disable a remote UART transmitter when the receiver buffer is full or nearly so. To minimize interrupt overhead an interrupt arbitration system is included which reports the context of the interrupting UART via direct access or through the modification of the interrupt vector. The context of the interrupt is reported as channel number, type of device interrupting ( receiver COS etc.) and, for transmitters or receivers, the fill level of the FIFO. The Octal UART provides a power down mode in which the oscillator is stopped but the register contents are maintained. This results in reduced power consumption of several orders of magnitudes. The Octal UART is fully TTL compatible when operating from a single +5V power supply. Operation at 3.3 volts is maintained with CMOS interface levels. The device also offered in a version which maintains TTL input and output levels while operating with a 3.3 volt power supply.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 3

Packet–switching networks Process Control Building or Plant Control Laboratory data gathering ISDN front ends Computer Networks Point–of–Sale terminals Automotive, cab and engine controls Entertainment systems MIDDI keyboard control music systems Theater lighting control Terminal Servers Computer–Printer/Plotter links

FEATURES

• Single 3.3V and 5V power supply
• Eight Philips industry standard full duplex UART channels
• Sixteen byte receiver FIFOs for each UART
• Sixteen byte transmit FIFOs for each UART
• In band flow control using programmable Xon/Xoff characters
• Flow control using CTSN RTSN hardware handshaking
• Automatic address detection in multi-drop mode
• Three byte general purpose character recognition
• Fast data bus, 30 ns data bus release time, 125 ns bus cycle time
• Programmable interrupt priorities
• Automatic identification of highest priority interrupt pending
• Global interrupt and control registers ease setup and interrupt handling
• Vectored interrupts with programmable interrupt vector formats – Interrupt vector modified with channel number – Interrupt vector modified with channel number and channel type – Interrupt vector not modified
• IACKN and DACKN signal pins
• Watch dog timer for each receiver (64 receive clock counts)
• Programmable Data Formats: – 5 to 8 data bits plus parity – Odd, even force or no parity – 1, 1.5 or 2 stop bits
• Flexible baud rate selection for receivers and transmitters: – 22 fixed rates; 50 – 230.4K baud or 100 to 460.8K baud – Additional non–standard rates to 500K baud with internal generators – Two reload–counters provide additional programmable baud rate generation – External 1x or 16x clock inputs – Simplified baud rate selection
• 1 MHz 1x and 16x data rates full duplex all channels.
• Parity, framing and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode – Normal(full duplex) – Diagnostic modes automatic echo local loop back emote loop back
• Four I/O ports per UART for modem controls, clocks, RTSN, I/O etc. – All I/O ports equipped with ”Change of State Detectors”
• Two global inputs and two global outputs for general purpose I/O
• Power down mode
• On chip crystal oscillator, 2–8 MHz
• TTL input levels. Outputs switch between full VCC and VSS
• High speed CMOS technology
• 84 pin PLCC
• 100 pin LQFP ORDERING CODE VCC = 5V ±10% PACKAGES Industrial1 DWG #Industrial -40°C to +85°C 84-Pin Plastic Leaded Chip Carrier (PLCC) SC28L198A1A SOT189-3 100-Pin Plastic Low–Profile Quad Flat Pack (LQFP) SC28L198A1BE SOT407–1 VCC = 3.3V ±10% Industrial1 -40°C to +85°C 84-Pin Plastic Leaded Chip Carrier (PLCC) SC28L198A1A SOT189-3 100-Pin Plastic Low–Profile Quad Flat Pack (LQFP) SC28L198A1BE SOT407–1 NOTES: 1. For availability, please contact factory.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 4

ÁÁÁÁÁÁ ÁÁÁÁÁÁ Pin ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Function ÁÁÁÁÁÁ ÁÁÁÁÁÁ Pin ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Function ÁÁÁÁÁÁ ÁÁÁÁÁÁ Pin ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Function ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VSS ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1d ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2g ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VCC ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2d ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1g ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ CEN ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3d ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0g ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ W_RN ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDd ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDg ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Vss ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDg ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDd ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VSS ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RESETN ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ DACKN ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Gin0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0a ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Gout0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDf ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1a ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3f ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDa ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2f ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDb ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1f ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2a ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0f ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3a ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VSS ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDe ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDa ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VCC ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3e ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0b ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2e ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1b ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1e ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2b ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDf ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3b ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDe ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDb ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Gin1 ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0e ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0c ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ IRQN ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Vss ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1c ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O1h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O2c ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3c ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Vss ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDc ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDh ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ RxDc ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TxDh ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ IACKN ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O0d ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I/O3g ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ SCLK

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 5

100–PIN LQFP TOP VIEW PINOUT ÁÁÁÁÁ ÁÁÁÁÁ Pin ÁÁÁÁÁ ÁÁÁÁÁ Function ÁÁÁÁÁ ÁÁÁÁÁ Pin ÁÁÁÁÁ ÁÁÁÁÁ Function ÁÁÁÁÁ ÁÁÁÁÁ Pin ÁÁÁÁÁÁ ÁÁÁÁÁÁ Function ÁÁÁÁÁ ÁÁÁÁÁ Pin ÁÁÁÁÁ ÁÁÁÁÁ Function ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxDb ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ TxDd ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxDe ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/02a ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RESETN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ RxDh ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0e ÁÁÁÁÁ ÁÁÁÁÁ I/03a ÁÁÁÁÁ ÁÁÁÁÁ G IN0 ÁÁÁÁÁ ÁÁÁÁÁÁ TxDh ÁÁÁÁÁ ÁÁÁÁÁ IRQN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ TxDa ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ G OUT 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O3g ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0b ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O2g ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O1b ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O1g ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O2b ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O0g ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O3b ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ RxDg ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ TxDb ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁÁ TxDg ÁÁÁÁÁ ÁÁÁÁÁ IACKN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0c ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Sclk ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O1c ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ I/O2c ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ TxDf ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O3c ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O3f ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CEN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ TxDc ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O2f ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ W_RN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxDc ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ G IN1 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O1f ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0d ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ G OUT 1 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O0f ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O1d ÁÁÁÁÁ ÁÁÁÁÁ I/O3h ÁÁÁÁÁ ÁÁÁÁÁÁ TxDe ÁÁÁÁÁ ÁÁÁÁÁ JA0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O2d ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O2h ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O3e ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DACKN ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O3d ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O1h ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O2e ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0a ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxDd ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O0h ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ I/O1e ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ I/O1a ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ RxDf ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxDa ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ N/C ÁÁÁÁÁ ÁÁÁÁÁ 100 ÁÁÁÁÁ ÁÁÁÁÁ N/C

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 6

ÁÁÁÁÁ ÁÁÁÁÁ MNEMONIC ÁÁÁ ÁÁÁ TYPE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ SClk ÁÁÁ ÁÁ Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency. ÁÁÁÁÁ ÁÁÁÁÁ CEN ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal indicates direction. (Must not be active in IACKN cycle) ÁÁÁÁÁ ÁÁÁÁÁ A(7:0) ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address lines (A[6] is NOT used. See ”Host Interface” ) ÁÁÁÁÁ ÁÁÁÁÁ D(7:0) ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 8–bit bi–directional data bus. Carries command and status information between 28L198 and the host CPU. Used to convey parallel data for serial I/O between the host CPU and the 28L198 ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ W_RN ÁÁÁ ÁÁ Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write Read not control: When high indicates that the host CPU will write to a 28L198 register or transmit FIFO. When low, indicates a read cycle. 0 = Read; 1 = Write ÁÁÁÁÁ ÁÁÁÁÁ DACKN ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete. Open drain. ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ IRQN ÁÁÁ ÁÁ Á ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Request: Active low. When asserted, indicates that the 28L198 requires service for pending inter- rupt(s). Open drain. ÁÁÁÁÁ ÁÁÁÁÁ IACKN ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt ac- knowledge cycle. (Do not use CEN in an IACKN cycle) ÁÁÁÁÁ ÁÁÁÁÁ TD(a–h) ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmit Data: Serial outputs from the 8 UARTs. ÁÁÁÁÁ ÁÁÁÁÁ RD(a–h) ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receive Data: Serial inputs to the 8 UARTs ÁÁÁÁÁ ÁÁÁÁÁ I/O0(a–h) ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input/Output 0: Multi–use input or output pin for the UART. ÁÁÁÁÁ I/O1(a–h) ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input/Output 1: Multi–use input or output pin for the UART. ÁÁÁÁÁ ÁÁÁÁÁ I/O2(a–h) ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input/Output 2: Multi–use input or output pin for the UART. ÁÁÁÁÁ ÁÁÁÁÁ I/O3(a–h) ÁÁÁ ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input/Output 3: Multi–use input or output pin for the UART. ÁÁÁÁÁ ÁÁÁÁÁ G IN(1:0) ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Global general purpose inputs, available to any/all channels. ÁÁÁÁÁ ÁÁÁÁÁ G OUT 0 ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Global general purpose outputs, available from any channel. ÁÁÁÁÁ ÁÁÁÁÁ RESETN ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and re- start the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK. ÁÁÁÁÁ ÁÁÁÁÁ X1/CCLK ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may alter- natively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁ Á ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin must be left unconnected. ÁÁÁÁÁ ÁÁÁÁÁ Power Supplies ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 8 pins total 6 pins for Vss, 2 pins for Vcc NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See previous note on Sclk noise under pin assignments. ABSOLUTE MAXIMUM RATINGS 1 ÁÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁÁ RATING ÁÁÁÁÁÁ UNIT ÁÁÁÁÁÁ ÁÁÁÁÁÁ TA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating ambient temperature range2 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ See Note 3 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ºC ÁÁÁÁÁÁ ÁÁÁÁÁÁ TSTG ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Storage temperature range ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ –65 to +150 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ºC ÁÁÁÁÁÁ ÁÁÁÁÁÁ Vcc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage from VCC to Vss4 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ –0.5 to +7.0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ V ÁÁÁÁÁÁ ÁÁÁÁÁÁ Vss ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Voltage from any pin to Vss ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ –0.5 to Vcc + 0.5 ÁÁÁÁÁÁ ÁÁÁÁÁÁ V ÁÁÁÁÁÁ ÁÁÁÁÁÁ PD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Package Power Dissipation (PLCC) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 3.78 ÁÁÁÁÁÁ ÁÁÁÁÁÁ W ÁÁÁÁÁÁ PD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Package Power Dissipation (LQFP) ÁÁÁÁÁÁÁÁÁ 2.08 ÁÁÁÁÁÁ W ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Derate above 25 ºC (PLCC pkg.) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ mW/ºC ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Derate above 25ºC (LQFP pkg.) ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ mW/ºC NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature. 3. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply range. 4. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 7

Block Diagram SC28C/28L198 HOST INTERFACE TIMING AND BAUD RATE GENERATOR INTERRUPT ARBITRATION I/O PORT TIMING AND INTERFACE FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL INPUT BUFFERS AND OUTPUT DRIVERS DATA DRIVERS AND MODEM INTERFACE SD00193 As shown in the block diagram, the Octal UART consists of: an interrupt arbiter, host interface, timing blocks and eight UART channel blocks. The eight channels blocks operate independently, interacting only with the timing, host I/F and interrupt blocks. FUNCTIONAL DESCRIPTION The SC28L198 is composed of several functional blocks:

• Synchronous host interface block
• A timing block consisting of a common baud rate generator making 22 industry standard baud rates and 2 16–bit counters used for non–standard baud rate generation
• 4 identical independent full duplex UART channel blocks
• Interrupt arbitration system evaluating 24 contenders
• I/O port control section and change of state detectors. CONCEPTUAL OVERVIEW Host Interface The Host interface is comprised of the signal pins CEN, W/RN, IACKN, DACKN, IRQN Sclk and provides all the control for data transfer between the external and internal data buses of the host and the OCTART. The host interface operates in a synchronous mode with the system (Sclk) which has been designed for a nominal operating frequency of 33 MHz. The interface operates in either of two modes; synchronous or asynchronous to the Sclk However the bus cycle within the OCTART always takes place in four Sclk cycles after CEN is recognized. These four cycles are the C1, C2, C3, C4 periods shown in the timing diagrams. DACKN always occurs in the C4 time and occurs approximately 18 ns after the rising edge of C4. Addressing of the various functions of the OCTART is through the address bus A(7:0). The 28L198 is compatible with the SC28L198 OCTAL UART in software and function. A[7], in a general sense, is used to separate the data portion of the circuit from the control portion. Asynchronous bus cycle The asynchronous mode requires one bus cycle of the chip select (CEN) for each read or write to the chip. No more action will occur on the bus after the C4 time until CEN is returned high. Synchronous bus cycle In the synchronous mode a read or write will be done every four cycles of the Sclk. CEN does not require cycling but must remain low to keep the synchronous accesses active. This provides a burst mode of access to the chip. In both cases each read or write operation(s) will be completed in four (4) Sclk cycles. The difference in the two modes is only that the asynchronous mode will not begin another bus cycle if the CEN remains active after the four internal Sclk have completed. Internally the asynchronous cycle will terminate after the four periods of Sclk regardless of how long CEN is held active In all cases the internal action will terminate at the withdrawal of CEN. Synchronous CEN cycles shorter than multiples of four Sclk cycles minus 1 Sclk and asynchronous CEN cycles shorter than four Sclk cycles may cause short read or write cycles and produce corrupted data transfers. Timing Circuits The timing block consists of a crystal oscillator, a fixed baud rate generator (BRG), a pair of programmable 16 bit register based

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 8

counters. A buffer for the System Clock generates internal timing for processes not directly concerned with serial data flow. Crystal Oscillator The crystal oscillator operates directly from a crystal, tuned between 1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with a minimum of external components. BRG values listed for the clock select registers correspond to a 3.6864 MHz crystal frequency. Use of a 7.3728 MHz crystal will double the Communication Clock frequencies. An external clock in the 100 KHz to 10 MHz frequency range may be connected to X1/CCLK. If an external clock is used instead of a crystal, X1/CCLK must be driven and X2 left floating. The X1 clock serves as the basic timing reference for the baud rate generator (BRG) and is available to the BRG timers . The X1 oscillator input may be left unused if the internal BRG is not used and the X1 signal is not selected for any counter input. Sclk – System Clock A clock frequency, within the limits specified in the electrical specifications, must be supplied for the system clock Sclk. To ensure the proper operation of internal controllers, the Sclk frequency provided, must be strictly greater than twice the frequency of X1 crystal clock, or any external 1x data clock input. The system clock serves as the basic timing reference for the host interface and other internal circuits. Baud Rate Generator BRG The baud rate generator operates from the oscillator or external X1/CCLK clock input and is capable of generating 22 commonly used data communications baud rates ranging from 50 to 230.4K baud. These common rates may be doubled (up to 460.8 and 500K baud) when faster clocks are used on the X1/X2 clock inputs. (See Receiver and Transmitter Clock Select Register descriptions.) All of these are available simultaneously for use by any receiver or transmitter. The clock outputs from the BRG are at 16X the actual baud rate. BRG Counters (Used for random baud rate generation) The two BRG Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks. These clocks may be used by any or all of the receivers and transmitters in the Octart or output on the general purpose output pin GPO. Each timer unit has eight different clock sources available to it as described in the BRG Timer Control Register. (BRGTCR). Note that the timer run and stop controls are also contained in this register. The BRG Timers generate a symmetrical square wave whose half period is equal in time to the division of the selected BRG Timer clock source by the number loaded to the BRG Timer Reload Registers ( BRGTRU and BRGTRL). Thus, the output frequency will be the clock source frequency divided by twice the value loaded to the BRGTRU and BRGTRL registers. This is the result of counting down once for the high portion of the output wave and once for the low portion. Whenever the these timers are selected via the receiver or transmitter Clock Select register their output will be configured as a 16x clock for the respective receiver or transmitter. Therefore one needs to program the timers to generate a clock 16 times faster than the data rate. The formula for calculating ’n’, the number loaded to the BRGTRU and BRGTRL registers, is shown below. n BRG Timer Input frequency 2 16 desired baud rate –1 Note: ’n’ may assume values of 0 and 1. In previous Philips data communications controllers these values were not allowed. The BRG timer input frequency is controlled by the BRG Timer control register (BRGTCR) The frequency generated from the above formula will be at a rate 16 times faster than the desired baud rate. The transmitter and receiver state machines include divide by 16 circuits which provide the final frequency and provide various timing edges used in the qualifying the serial data bit stream. Often this division will result in a non–integer value; 26.3 for example. One may only program integer numbers to a digital divider. There for 26 would be chosen. If 26.7 was the result of the division then 27 would be chosen. This percentage error of 1.14% or 1.12% respectively; well within the ability of the asynchronous mode of operation. One should be cautious about the assumed benign effects of small errors since the other receiver or transmitter with which one is communicating may also have a small error in the precise baud rate. In a ”clean” communications environment using one start bit, eight data bits and one stop bit the total difference allowed between the transmitter and receiver frequency is approximately 4.6%. Less than eight data bits will increase this percentage. Channel Blocks There are eight channel blocks, each containing an I/O port control, a data format control, and a single full duplex UART channel consisting of a receiver and a transmitter with their associated 16 byte FIFOs. Each block has its own status register, interrupt status and interrupt mask registers and their interface to the interrupt arbitration system. A highly programmable character recognition system is also included in each block. This system is used for the Xon/Xoff flow control and the multi-drop (”9 bit mode”) address character recognition. It may also be used for general purpose character recognition. Four I/O pins are provided for each channel. These pins are configured individually to be inputs or outputs. As inputs they may be used to bring external data to the bus, as clocks for internal functions or external control signals. Each I/O pin has a ”Change of State” detector. The change detectors are used to signal a change in the signal level at the pin (Either 0 to 1 or 1 to 0). The level change on these pins must be stable for 25 to 50 Us (two edges of the 38.4 KHz baud rate clock) before the detectors will signal a valid change. These are typically used for interface signals from modems to the OCTART and from there to the host. See the description of the ”UART channel” under detailed descriptions below. Character Recognition Character recognition is specific to each of the eight UARTs. Three programmable characters are provided for the character recognition for each channel. The three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to ”Multi-drop” address recognition or in–band Xon/Xoff flow control. Character recognition is accomplished via CAM memory. The Content Addressable Memory continually examines the incoming data stream. Upon the recognition of a control character appropriate bits are set in the Xon/Xoff Interrupt Status Register (XISR) and Interrupt Status Register (ISR). The setting of these bit(s) will initiate any of the automatic sequences or and/or an interrupt that may have enabled via the MR0 register. The characters of the recognition system are not controlled by the software or hardware reset. They do not have a pre-defined “reset

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 9

value”. They may, however, be loaded by a “Gang White” or “Gang Load” command as described in the “Xon Xoff Characters” paragraph. Note: Character recognition is further described in the Minor Modes of Operation. Interrupt Control The interrupt system determines when an interrupt should be asserted thorough an arbitration (or bidding) system. This arbitration is exercised over the several systems within the OCTART that may generate an interrupt. These will be referred to as ”interrupt sources”. There are 64 in all. In general the arbitration is based on the fill level of the receiver FIFO or the empty level of the transmitter FIFO. The FIFO levels are encoded into a four bit number which is concatenated to the channel number and source identification code. All of this is compared (via the bidding or arbitration process) to a user defined ”threshold”. When ever a source exceeds the numerical value of the threshold the interrupt will be generated. At the time of interrupt acknowledge (IACKN) the source which has the highest bid (not necessarily the source that caused the interrupt to be generated) will be captured in a ”Current Interrupt Register” (CIR). This register will contain the complete definition of the interrupting source: channel, type of interrupt (receiver, transmitter, change of state, etc.), and FIFO fill level. The value of the bits in the CIR are used to drive the interrupt vector and global registers such that controlling processor may be steered directly to the proper service routine. A single read operation to the CIR provides all the information needed to qualify and quantify the most common interrupt sources. The interrupt sources for each channel are listed below.

• Transmit FIFO empty level for each channel
• Receive FIFO Fill level for each channel
• Change in break received status for each channel
• Receiver with error for each channel
• Change of state on channel input pins
• Receiver Watch-dog Time out Event
• Xon/Xoff character recognition
• Address character recognition Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR) resident in each UART. Programming of the IMR selects which of the above sources may enter the arbitration process. Only the bidders in the ISR whose associated bit in the IMR is set to one (1) will be permitted to enter the arbitration process. The ISR can be read by the host CPU to determine all currently active interrupting conditions. For convenience the bits of the ISR may be masked by the bits of the IMR. Whether the ISR is read unmasked or masked is controlled by the setting of bit 6 in MR1. Global Registers The ”Global Registers”, 19 in all, are driven by the interrupt system. These are not real hardware devices. They are defined by the content of the CIR (Current Interrupt Register) as a result of an interrupt arbitration. In other words they are indirect registers contained in the Current Interrupt Register (CIR) which the CIR uses to point to the source and context of the OCTART sub circuit presently causing an interrupt. The principle purpose of these ”registers” is improving the efficiency of the interrupt service. The global registers and the CIR update procedure are further described in the Interrupt Arbitration system I/O Ports Each of the eight UART blocks contains an I/O section of four ports. These ports function as a general purpose post section which services the particular UART they are associated with. External clocks are input and internal clocks are output through these ports. Each of the four pins has a change of state detector which will signal a change (0 to 1 or 1 to 0) at the pin. The change of state detectors are individually enabled and may be set to cause and interrupt. These pins will normally be used for flow control hand–shaking and the interface to a modem. Their control is further described in I/O Ports section and the I/OPCR register. DETAILED DESCRIPTIONS RECEIVER AND TRANSMITTER The Octal UART has eight full-duplex asynchronous receiver/transmitters. The operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter , or from an external input. Registers that are central to basic full-duplex operation are the mode registers (MR0, MR1 and MR2), the clock select registers (RxCSR and TxCSR), the command register (CR), the status register (SR), the transmit holding register (TxFIFO), and the receive holding register (RxFIFO). Transmitter The transmitter accepts parallel data from the CPU and converts it to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Each character is always ”framed” by a single start bit and a stop bit that is 9/16 bit time or longer. If a new character is not available in the TxFIFO, the TxD output remains high, the ”marking” position, and the TxEMT bit in the SR is set to 1. Transmitter Status Bits The SR (Status Register, one per UART) contains two bits that show the condition of the transmitter FIFO. These bits are TxRDY and TxEMT. TxRDY means the TxFIFO has space available for one or more bytes; TxEMT means The TxFIFO is completely empty and the last stop bit has been completed. TxEMT can not be active without TxRDY also being active. These two bits will go active upon initial enabling of the transmitter. They will extinguish on the disable or reset of the transmitter. Transmission resumes and the TxEMT bit is cleared when the CPU loads at least one new character into the TxFIFO. The TxRDY will not extinguish until the TxFIFO is completely full. The TxRDY bit will always be active when the transmitter is enabled and there is at lease one open position in the TxFIFO. The transmitter is disabled by reset or by a bit in the command register (CR). The transmitter must be explicitly enabled via the CR before transmission can begin. Note that characters cannot be loaded into the TxFIFO while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the TxFIFO. It is not possible to load the TxFIFO and then enable the transmission. Note the difference between transmitter disable and transmitter reset. The transmitter may by reset by a hardware or software. The

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 10

software reset is issued through command 3x of the Command register (CR). The disable is done by setting the transmitter disable bit also in the command register. If the transmitter is disabled, it continues operating until the character currently being transmitted, if any, is completely sent, including the stop bit. When reset the transmitter stops immediately, drives the transmitter serial data out put to a high level and discards any data in the TxFIFO. Transmission of ”break”s Transmission of a break character is often needed as a synchronizing condition in a data stream. The ”break” is defined as a start bit followed by all zero data bits by a zero parity bit (if parity is enabled) and a zero in the stop bit position. The forgoing is the minimum time to define a break. The transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the CR. This command does not have any timing associated with it. Once issued the TxD output will be driven low (the spacing condition) and remain there until the host issues a command to ”stop break” via the CR or the transmitter is issued a software or hardware reset. In normal operation the break is usually much longer than one character time. 1x and 16x modes, Transmitter The transmitter clocking has two modes: 16x and 1x. Data is always sent at the 1x rate. However the logic of the transmitter may be operated with a clock that is 16 times faster than the data rate or at the same rate as the data i.e. 1x. All clocks selected internally for the transmitter (and the receiver) will be 16x clocks. Only when an external clock is selected may the transmitter logic and state machine operate in the 1x mode. The 1x or 16x clocking makes little difference in transmitter operation. (this is not true in the receiver) In the 16X clock mode the transmitter will recognize a byte in the TxFIFO within 1/16 to 2/16 bit time and thus begin transmission of the start bit; in the 1x mode this delay may be up to 2 bit times. Transmitter FIFO The transmitter buffer memory is a 16 byte by 8 bit ripple FIFO. The host writes characters to this buffer. This buffer accepts data only when the transmitter is enabled. The transmitter state machine reads them out in the order they were received and presents them to the transmitter shift register for serialization. The transmitter adds the required start, parity and stop bits as required the MR2 register programming. The start bit (always one bit time in length) is sent first followed by the least significant bit (LSB) to the most significant bit (MSB) of the character, the parity bit (if used) and the required stop bit(s). Logic associated with the FIFO encodes the number of empty positions available in a four bit value. This value is concatenated with the channel number and type interrupt type identifier and presented to the interrupt arbitration system. The encoding of the ”positions empty” value is always 1 less than the number of available positions. Thus, an empty TxFIFO will bid with the value or 15; when full it will not bid at all; one position empty bids with the value 0. A full FIFO will not bid since a character written to it will be lost Normally a TxFIFO will present a bid to the arbitration system when ever it has one or more empty positions. The MR0[5:4] allow the user to modify this characteristic so that bidding will not start until one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. A similar system exists in the receiver. Receiver The receiver accepts serial data on the RxD pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any),framing error or break condition, and presents the assembled character and its status condition to the CPU via the RxFIFO. Three status bits are FIFOed with each character received. The RxFIFO is really 11 bits wide; eight data and 3 status. Unused FIFO bits for character lengths less than 8 bits are set to zero. It is important to note that receiver logic considers the entire message to be contained within the start bit to the stop bit. It is not aware that a message may contain many characters. The receiver returns to its idle mode at the end of each stop bit! As described below it immediately begins to search for another start bit which is normally, of course, immediately forth coming. 1x and 16x mode, Receiver The receiver operates in one of two modes; 1x and 16x. Of the two, the 16x is more robust and the preferred mode. Although the 1x mode may allow a faster data rate is does not provide for the alignment of the receiver 1x data clock to that of the transmitter. This strongly implies that the 1x clock of the remote transmitter is available to the receiver; the two devices are physically close to each other. The 16x mode operates the receiver logic at a rate 16 times faster than the 1x data rate. This allows for validation of the start bit, validation of level changes at the receiver serial data input (RxD), and a stop bit length as short as 9/16 bit time. Of most importance in the 16x mode is the ability of the receiver logic to align the phase of the receiver 1x data clock to that of the transmitter with an accuracy of less than 1/16 bit time. When the receiver is enabled ( via the CR register) it begins looking for a high to low (mark to space) transition on the RxD input pin. If a transition is detected, an internal counter running at 16 times the data rate is reset to zero. If the RxD remains low and is still low when the counter reaches a count of 7 the receiver will consider this a valid start bit and begin assembling the character. If the RxD input returns to a high state the receiver will reject the previous high to low (mark to space) transition on the RxD input pin. This action is the ”validation” of the start bit and also establishes the phase of the receiver 1x clock to that of the transmitter The counter operating at 16x the data rate is the generator for the 1x data rate clock. With the phase of the receiver 1x clock aligned to the falling of the start bit (and thus aligned to the transmitter clock) AND with a valid start bit having been verified the receiver will continue receiving bits by sampling the RxD input on the rising edge of the 1x clock that is being generated by the above mentioned counter running 16 times the data rate. Since the falling edge of the 1x clock was aligned to falling edge of the start bit then the rising of the clock will be in the ”center” of the bit cell. This action will continue until a full character has been assembled. Parity , framing, and stop bit , and break status is then assembled and the character and its status bits are loaded to the RxFIFO At this point the receiver has finished its task for that character and will immediately begin the search for another start bit. Receiver Status Bits There are five (5) status bits that are evaluated with each byte (or character) received: received break, framing error, parity error, overrun error, and change of break. The first three are appended to each byte and stored in the RxFIFO. The last two are not necessarily related to the a byte being received or a byte that is in the RxFIFO. They are however developed by the receiver state machine

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 11

. The ”received break” will always be associated with a zero byte in the RxFIFO. It means that zero character was a break character and not a zero data byte. The reception of a break condition will always set the ”change of break” (see below) status bit in the Interrupt Status Register(ISR). A framing error occurs when a non zero character was seen and that character has a zero in the stop bit position. The parity error indicates that the receiver generated parity was not the same as that sent by the transmitter. The overrun error occurs when the RxFIFO is full, the receiver shift register is full and another start bit is detected. At this moment the receiver has 17 valid characters and the start bit of the 18th has been seen. At this point the host has approximately 7/16 bit time to read a byte from the RxFIFO or the overrun condition will be set and the 18th character will overrun the 17th and the 19th the 18th and so on until an open position in the RxFIFO is seen. The meaning of the overrun is that data has been lost. Data in the RxFIFO remains valid. The receiver will begin placing characters in the RxFIFO as soon as a position becomes vacant. Note: Precaution must be taken when reading an overrun FIFO. There will be 16 valid characters. Data will begin loading as soon as the first character is read. The 17 th. character will have been received as valid but it will not be known how many characters were lost between the two characters of the 16th. and 17th. reads of the RxFIFO The ”Change of break” means that either a break has been detected or that the break condition has been cleared. This bit is available in the ISR. The beginning of a break will be signaled by the break change bit being set in the ISR AND the received break bit being set in the SR. At the termination of the break condition only the change of break in the ISR will be set. After the break condition is detected the termination of the break will only be recognized when the RxD input has returned to the high state for two successive edges of the 1x clock; 1/2 to 1 bit time. The receiver is disabled by reset or via CR commands. A disabled receiver will not interrupt the host CPU under any circumstance in the normal mode of operation. If the receiver is in the multi-drop or special mode, it will be partially enabled and thus may cause an interrupt. Refer to section on Wake–Up and minor modes and the register description for MR1 for more information. Receiver FIFO The receiver buffer memory is a 16 byte ripple FIFO with three status bits appended to each data byte. (The FIFO is then 16 11 bit ”words”). The receiver state machine gathers the bits from the receiver shift register and the status bits from the receiver logic and writes the assembled byte and status bits to the RxFIFO. Logic associated with the FIFO encodes the number of filled positions for presentation to the interrupt arbitration system. The encoding is always 1 less than the number of filled positions. Thus, a full RxFIFO will bid with the value or 15; when empty it will not bit at all; one position occupied bids with the value 0. An empty FIFO will not bid since no character is available. Normally RxFIFO will present a bid to the arbitration system when ever it has one or more filled positions. The MR2[3:2 bits allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 1/2 filled, 3/4 filled, full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. A similar system exists in the transmitter. RxFIFO Status: Status reporting modes The description below applies to the upper three bits in the ”Status Register” These three bits are not ”in the status register”; They are part of the RxFIFO. The three status bits at the top of the RxFIFO are presented as the upper three bits of the status register included in each UART. The error status of a character , as reported by a read of the SR (status register upper three bits) can be provided in two ways, as programmed by the error mode control bit in the mode register: ”Character mode ” or the ”Block Mode”. The block mode may be further modified (via a CR command) to set the status bits as the characters enter the FIFO or as they are read from the FIFO. In the ’character’ mode, status is provided on a character by character basis as the characters are read from the RxFIFO: the ”status” applies only to the character at the top of the RxFIFO – The next character to be read In the ’block’ mode, the status provided in the SR for these three bits is the logical OR of the status for all characters coming to the top of the RxFIFO, since the last reset error command was issued. In this mode each of the status bits stored in the RxFIFO are passed through a latch as they are sequentially read. If any of the characters has an error bit set then that latch will set and remain set until reset with an ”Reset Error” command from the command register or a receiver reset. The purpose of this mode is indicating an error in the data block as opposed to an error in a character The latch used in the block mode to indicate ”problem data” is usually set as the characters are read out of the RxFIFO. Via a command in the CR the latch may be configured to set the latch as the characters are pushed (loaded to) the RxFIFO. This gives the advantage of indicating ”problem data” 16 characters earlier . In either mode, reading the SR does not affect the RxFIFO. The RxFIFO is ’popped’ only when the RxFIFO is read. Therefore, the SR should be read prior to reading the corresponding data character. If the RxFIFO is full when a new character is received, that character is held in the receive shift register until a RxFIFO position is available. At this time there are 17 valid characters in the RxFIFO. If an additional character is received while this state exists, the contents of the RxFIFO are not affected: the character previously in the shift register is lost and the overrun error status bit, SR[4], will be set upon receipt of the start bit of the new (overrunning) character. I/O ports Each of the eight UARTs includes four I/O ports equipped with ”change of state” detectors. The pins are individually programmable for an input only function or one of three output functions. These functions are controlled by the ”I/O Port Configuration Register (I/OPCR)) They will normally be used for the RTSN–CTSN, DTR hardware signals, RxD or TxD input or output clocks or switch inputs as well as data out put from the I/OPIOR register. It is important to note that the input circuits are always active. That is the signal on a port, whether it is derived from an internal or external source is always available to the internal circuits associated with an input on that port. The ”Change of State” (COS) detectors are sensitive to both a 1 to 0 or a 0 to 1 transition. The detectors are controlled by the internal

38.4 KHz baud rate and will signal a change when a transition has

been stable for two rising edges of this clock. Thus a level on the I/O ports must be stable for 26 s to 52 s. Defining a port as an output will disable the COS detector at that port. The condition of

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 12

the four I/O pins and their COS detectors is available at any time in the IPR (Input Port Register) The control of data and COS enable for these ports is through the I/OPIOR register. This is a read/write register and gives individual control to the enabling of the change of state detectors and also to the level driven by I/O pins when programmed to drive the logic level written to the four lower bits of the I/OPIOR. A read of this register will indicate the data on the pin at the time of the read and the state of the enabled COS detectors. General Purpose Pins In addition to the I/O ports for each UART four other ports are provided which service the entire chip. Two are dedicated as inputs and one as an output. The G IN1 and GIN0 are the input pins; GOUT 0 the output. These ports are multiplexed to nearly every functional unit in the chip. See the registers which describe the multitude of connections available for these pins. The G OUT 0 pin is highly multiplexed output and is controlled by four (4) registers: GPOSR, GPOR, GPOC and GPOD. The G IN0 and GIN1 pins are available to the receivers and transmitters, BRG counters and the GOUT 0 pin. Global Registers The ”Global Registers”, 19 in all, are driven by the interrupt system. These are not real hardware devices. They are defined by the content of the CIR (Current Interrupt Register) as a result of an interrupt arbitration. In other words they are indirect registers pointed to by the content of the CIR. The list of global register follows: GIBCR The byte count of the interrupting FIFO GICR Channel number of the interrupting channel GITR Type identification of interrupting channel GRxFIFO Pointer to the interrupting receiver FIFO GTxFIFO Pointer to the interrupting transmitter FIFO A read of the GRxFIFO will give the content of the RxFIFO that presently has the highest bid value. The purpose of this system is to enhance the efficiency of the interrupt system. The global registers and the CIR update procedure are further described in the Interrupt Arbitration system Character Recognition The character recognition circuits are basically designed to provide general purpose character recognition. Additional control logic has been added to allow for Xon/Xoff flow control and for recognition of the address character in the multi-drop or ”wake–up” mode. This logic also allows for the generation of an interrupts in either the general purpose recognition mode or the specific conditions mentioned above. Xon Xoff Characters The programming of these characters is usually done individually. However a method has been provided to write to all of registers in one operation. There are ”Gang Load” and a ”Gang Write” commands provided in the channel A Command Register. When these commands are executed all registers are programmed with the same characters. The ”write” command loads a used defined character; the ’load” command loads the standard Xon/Xoff characters. Xon is x’11; Xoff x’13’. Any enabling of the Xon/Xoff functions will use the contents of the Xon and Xoff character registers as the basis on which recognition is predicated. Multi-drop or Wake up or 9 bit mode This mode is used to address a particular UART among a group connected to the same serial data source. Normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. While this method is fully supported in the SC28L198 it also supports recognition of the character itself. Upon recognition of its address the receiver will be enabled and data pushed onto the RxFIFO. Further the Address recognition has the ability, if so programmed, to disable (not reset) the receiver when an address is seen that is not recognized as its own. The particular features of ”Auto Wake and Auto Doze” are described in the detail descriptions below. Note: Care should be taken in the programming of the character recognition registers. Programming x’00, for example, may result in a break condition being recognized as a control character. This will be further complicated when binary data is being processed. Character Stripping The MR0 register provides for stripping the characters used for character recognition. Recall that the character recognition may be conditioned to control several aspects of the communication. However this system is first a character recognition system. The status of the various states of this system are reported in the XISR and ISR registers. The character stripping of this system allows for the removal of the specified control characters from the data stream: two for the Xon /Xoff and one for the wake up. Via control in the MR0 register these characters may be discarded (stripped) from the data stream when the recognition system “sees” them or they may be sent on the RxFIFO. Whether they are stripped or not the recognition will process them according to the action requested: flow control, wake up, interrupt generation, etc. Care should be exercised in programming the stripping option if noisy environments are encountered. If a normal character was corrupted to an Xoff character turned off the transmitter and it was then stripped, then the stripping action could make it difficult to determine the cause of transmitter stopping. Interrupt Arbitration and IRQN generation Interrupt arbitration is the process used to determine that an interrupt request should be presented to the host. The arbitration is carried out between the ”Interrupt Threshold” and the ”sources” whose interrupt bidding is enabled by the IMR. The interrupt threshold is part of the ICR (Interrupt Control Register) and is a value programmed by the user. The ”sources” present a value to the interrupt arbiter. That value is derived from four fields: the channel number, type of interrupt source, FIFO fill level, and programmable value. . Only when one or more of these values exceeds the threshold value in the interrupt control register will the interrupt request (IRQN) be asserted. Following assertion of the IRQN the host will either assert IACKN(Interrupt Acknowledge) or will use the command to ”Update the CIR”. At the time either action is taken the CIR will capture the value of the source that is prevailing in the arbitration process. (Call this value the winning bid) The value in the CIR is the central quantity that results from the arbitration. It contains the identity of the interrupting channel, the type of interrupt in that channel (RxD, TxD, COS etc.) the fill levels of the RxD or TxD FIFOs and , in the case of an RxD interrupt an indicator of error data or good data. It also drives the Global Registers associated with the interrupt. Most importantly it drives the modification of the Interrupt Vector. The arbitration process is driven by the Sclk. It scans the 10 bits of the arbitration bus at the Sclk rate developing a value for the CIR every 22 Sclk cycles. New arbitration values presented to the arbitration block during an arbitration cycle will be evaluated in the next arbitration cycle.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

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For sources other than receiver and transmitters the user may set the high order bits of an interrupt source’s bid value, thus tailoring the relative priority of the interrupt sources. The priority of the receivers and transmitters is controlled by the fill level of their respective FIFOs. The more filled spaces in the RxFIFO the higher the bid value; the more empty spaces in the TxFIFO the higher its priority. Channels whose programmable high order bits are set will be given interrupt priority higher than those with zeros in their high order bits , thus allowing increased flexibility. The transmitter and receiver bid values contain the character counts of the associated FIFOs as high order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids with a progressively higher priority for interrupt service. Similarly, as empty space in a transmitter’s TxFIFO increases, its interrupt arbitration priority increases. IACKN Cycle, Update CIR When the host CPU responds to the interrupt, it will usually assert the IACKN signal low. This will cause the OCTART to generate an IACKN cycle in which the condition of the interrupting device is determined. When IACKN asserts, the last valid interrupt number is captured in the CIR. The value captured presents most of the important details of the highest priority interrupt at the moment the IACKN (or the ”Update CIR” command) was asserted. The Octal UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector may be a fixed value, the content of the Interrupt Vector Register, or ,when ”Interrupt Vector Modification is enabled via ICR, it may contain codes for the interrupt type and/or interrupting channel. This allows the interrupt vector to steer the interrupt service directly to the proper service routine. The interrupt value captured in the CIR remains until another IACKN cycle occurs or until an ”Update CIR” command is given to the OCTART. The interrupting channel and interrupt type fields of the CIR set the current ”interrupt context” of the OCTART. The channel component of the interrupt context allows the use of Global Interrupt Information registers that appear at fixed positions in the register address map. For example, a read of the Global RxFIFO will read the channel B RxFIFO if the CIR interrupt context is channel b receiver. At another time read of the GRxFIFO may read the channel D RxFIFO (CIR holds a channel D receiver interrupt) and so on. Global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from FIFOs without explicitly addressing them. The CIR will load with x’00 if IACKN or Update CIR is asserted when the arbitration circuit is NOT asserting and interrupt. In this condition there is no arbitration value that exceeds the threshold value. Polling Many users prefer polled to interrupt driven service where there are a large number of fast data channels and/or the host CPU’s other interrupt overhead is low. The Octal UART is functional in this environment. The most efficient method of polling is the use of the ”update CIR” command (with the interrupt threshold set to zero) followed by a read of the CIR. This dummy write cycle will perform the same CIR capture function that an IACKN falling edge would accomplish in an interrupt driven system. A subsequent read of the CIR, at the same address, will give information about an interrupt, if any. If the CIR contains 0s, no interrupt is awaiting service. If the value is non–zero, the fields of the CIR may be decoded for type, channel and character count information. Optionally, the global interrupt registers may be read for particular information about the interrupt status or use of the global RxD and TxD registers for data transfer as appropriate. The interrupt context will remain in the CIR until another update CIR command or an IACKN cycle is initiated by the host CPU occurs. The CIR loads with x’00 if Update CIR is asserted when the arbitration circuit has NOT detected arbitration value that exceeds the threshold value. Traditional methods of polling status registers may also be used. They of course are less efficient but give the most variable and quickest method of changing the order in which interrupt sources are evaluated and interrogated. Enabling and Activating Interrupt sources An interrupt source becomes enabled when its interrupt capability is set by writing to the Interrupt Mask Register, IMR. An interrupt source can never generate an IRQN or have its ”bid” or interrupt number appear in the CIR unless the source has been enabled by the appropriate bit in an IMR. An interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation. Most sources have simple activation requirements. The watch-dog timer, break received, Xon/Xoff or Address Recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the ICR (Interrupt Control Register). The transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt ”bidding” begins: the TxINT and RxINT fields of the MR0 and MR2 registers. These fields can be used to start bidding or arbitration when the RxFIFO is not empty, 50% full, 75% full or 100% full. For the transmitter it is not full, 50% empty, 75% empty and empty. Example: To increase the probability of transferring the contents of a nearly full RxFIFO, do not allow it to start bidding until 50% or 75% full. This will prevent its relatively high priority from winning the arbitration process at low fill levels. A high threshold level could accomplish the same thing, but may also mask out low priority interrupt sources that must be serviced. Note that for fast channels and/or long interrupt latency times using this feature should be used with caution since it reduces the time the host CPU has to respond to the interrupt request before receiver overrun occurs. Setting Interrupt Priorities The bid or interrupt number presented to the interrupt arbiter is composed of character counts, channel codes, fixed and programmable bit fields. The interrupt values are generated for various interrupt sources as shown in the table below: The value represented by the bits 9 to 3 in the table below are compared against the value represented by the “Threshold. The “Threshold” ,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such that bit 6 of the threshold is compared to bit 9 of the interrupt value generated by any of the sources. When ever the value of the interrupt source is greater than the threshold the interrupt will be generated. The channel number arbitrates only against other channels. The threshold is not used for the channel arbitration. This results in channel D having the highest arbitration number. The decreasing order is H to A. If all other parts of an arbitration are equal then the channel number will determine which channel will dominate in the arbitration process

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Table 1. Interrupt Arbitration Priority

0010 Change of Break

0110 Change of State on I/O Ports

0111 Xon/Xoff Event

0011 Address Recognition

near maximum number of characters may be transferred. be the one that caused the watch-dog to bark. sources they represent to values almost as high as a full receiver. its arbitration value could be reduced or turned off. larger than the threshold value that the IRQN will be asserted. be loaded with if the IRQN or ”Update CIR” command is asserted. will win the bid when all other parts of the bid are equal.

1. A single empty slot is left in the TxFIFO or a single

filled slot in the RxFIFO will bid with a value of zero. and remote loop back) are provided and are controlled by MR2[7:6]. reception and transmission will use the normal mode. transmitter communication has no meaning. without any external parameters to affect the transmission of data. within the UART – it is essentially ”talking to itself”.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 15

The remote loop back mode (also used for diagnostic purposes) is similar to auto echo except that the characters are not sent to the local CPU, nor is the receiver status updated. The received data is sent directly to the transmitter where it is sent out on the TxD output. The received data is not sent to the receive FIFO and hence the host will not normally be participating in any diagnostics. Minor Modes The minor modes provide additional features within the major modes. In general the minor modes provide a reduction in the control burden and a less stringent interrupt latency time for the host processor. These modes could be invoked in all of the major modes.. However it may not be reasonable in many situations. Watch-dog Timer Time–out Mode Each receiver in the Octal UART is equipped with a watch-dog timer that is enabled by the ”Watch-dog Timer Enable Register (WTER). The watch-dog ”barks” (times out) if 64 counts of the receiver clock (64 bit times) elapse with no RxFIFO activity. RxFIFO events are a read of the RxFIFO or GRxFIFO, or the push of a received character into the RxFIFO. The timer resets when the (G)RxFIFO is read or if another character is pushed into the RxFIFO. The receiver watch-dog timer is included to allow detection of the very last character(s) of a received message that may be waiting in the RxFIFO, but are too few in number to successfully initiate an interrupt. The watch-dog timer is enabled for counting if the channel’s bit in the Watch Dog Timer Control Register (WDTCR) is set. Note: a read of the GRxFIFO will reset the watch-dog timer of only the channel specified in the current interrupt context. Other watch-dogs are unaffected. The watch-dog timer may generate an input to the interrupt arbiter if IMR[6] is set. The status of the Watch-dog timer can be seen as Bit 6 of the Interrupt Status Register, ISR[6]. When a Watch-dog timer that is programmed to generate an interrupt times out it enters the arbitration process. It will then only allow receivers to enter the enter the arbitration. All other sources are bidding sources are disabled. The receivers arbitrate only amongst themselves.. The receiver only interrupt mode of the interrupt arbiter continues until the last watch-dog timer event has been serviced. While in the receiver only interrupt mode, the control of the interrupt threshold level is also disabled. The receivers arbitrate only between themselves. The threshold value is ignored. The receiver with the most FIFO positions filled will win the bid. Hence the user need not reduce the bidding threshold level in the ICR to see the interrupt from a nearly empty RxFIFO that may have caused the watch-dog time–out. Note: When any watch-dog times our only the receivers arbitrate. There is no increase in the probability of receiver being serviced causing the overrun of another receiver since they will still have priority based upon received character count. The interrupt will be cleared automatically upon the push of the next character received or when the RxFIFO or GRxFIFO is read. The ICR is unaffected by the watch-dog time–out interrupt and normal interrupt threshold level sensing resumes after the last watch-dog timer event has been processed. If other interrupt sources are active, the IRQN pin may remain low. Wake Up Mode The SC28L198 provides two modes of this common asynchronous “party line” protocol: the new automatic mode with 3 sub modes and the default Host operated mode. The automatic mode has several sub modes (see below). In the full automatic the internal state machine devoted to this function will handle all operations associated with address recognition, data handling, receiver enables and disables. In both modes the meaning of the parity bit is changed. It is often referred to as the A/D bit or the address/data bit. It is used to indicate whether the byte presently in the receiver shift register is an ”address” byte or a ”data” byte. ”1” usually means address; ”0” data. Its purpose is to allow several receivers connected to the same data source to be individually addressed. Of course addressing could be by group also. Normally the ”Master” would send an address byte to all receivers ”listening” The receiver would then recognize its address and enable itself receiving the following data stream. Upon receipt of an address not its own it would then disable itself. As descried below appropriate status bits are available to describe the operation. Enabling the Wake Up mode This mode is selected by programming bits MR1[4:3] to ’11’. The sub modes are controlled by bits 6, 1, 0 in the MR0 register. Bit 6 controls the loading of the address byte to the RxFIFO and MR0[1:0] determines the sub mode as shown in the following table. MR0[1:0] = 00 Normal Wake Up Mode (default). Host controls operation via interrupts and commands written to the command register (CR). MR0[1:0] = 01 Auto wake. Enable receiver on address recognition for this station. Upon recognition of its assigned address, in the Auto Wake mode, the local receiver will be enabled and normal receiver communications with the host will be established. MR0[1:0] = 10 Auto Doze. Disable receiver on address recognition, not for this station. Upon recognition of an address character that is not its own, in the Auto Doze mode, the receiver will be disabled and the address just received either discarded or pushed to the RxFIFO depending on the programming of MR0[6]. MR0[1:0] = 11 Auto wake and doze. Both modes above. The programming of MR0[1:0] to 11 will enable both the auto wake and auto doze features. The enabling of the wake–up mode executes a partial enabling of the receiver state machine. Even though the receiver has been reset the wake up mode will over ride the disable and reset condition. Normal Wake up (The default configuration) In the default configuration for this mode of operation, a ’master’ station transmits an address character followed by data characters for the addressed ’slave’ station. The slave stations, whose receivers are normally disabled (not reset), examine the received data stream and interrupts the CPU (by setting RxRDY) only upon receipt of an address character. The CPU (host) compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again . A transmitted character consists of a start bit, the programmed number of data bits, an address/data (A/D) bit, and the programmed number of stop bits. The polarity of the transmitted A/D bit is selected by the CPU by programming bit MR1[2]. MR1[2] = 0 transmits a zero in the A/D bit position which identifies the corresponding data bits as data. MR1[2] = 1 transmits a one in the A/D bit position which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bytes into the TxFIFO.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 16

While in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RxFIFO if the received A/D bit is a one, but discards the received character if the received A/D bit is a zero. If the receiver is enabled, all received characters are transferred to the CPU via the RxFIFO. In either case, the data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SR[5]). Framing error, overrun error, and break detect operate normally whether or not the receiver is enabled. Automatic operation, Wake Up & Doze The automatic configuration for this mode uses on-board comparators to examine incoming address characters. Each UART channel may be assigned a unique address character. See the address register map and the description of the Address Recognition Character Register (ARCR). The device may be programmed to automatically awaken a sleeping receiver and/or disable an active receiver based upon address characters received. The operation of the basic receiver is the same as described above for the default mode of wake–up operation except that the CPU need not be interrupted to make a change in the receiver status. Three bits in the Mode Register 0, (MR0), control the address recognition operation. MR0[6] controls the RxFIFO operation of the received character; MR0[1:0] controls the wake up mode options. If MR0[6] is set the address character will be pushed onto the RxFIFO, otherwise the character will be discarded. (The charter is stripped from the data stream) The MR0[1:0] bits set the options as follows: A b’00 in this field, the default or power–on condition, puts the device in the default (CPU controlled) wake up mode of operation as described above. The auto–wake mode, enabled if MR0[0] is set, will cause the dedicated comparators to examine each address character presented by the receiver. If the received character matches the reference character in ARCR, the receiver will be enabled and all subsequent characters will be FIFOed until another address event occurs or the host CPU disables the receiver explicitly. The auto doze mode, enabled if MR0[1] is set, will automatically disable the receiver if an address is received that does not match the reference character in the ARCR. The UART channel can present the address recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 5 of the Interrupt Mask Register, IMR. The bid level of an address recognition event is controlled by the Bidding Control Register, BCRA, of the channel. Note: To ensure proper operation, the host CPU must clear any pending Address Recognition interrupt before enabling a disabled receiver operating in the Special or Wake–up mode. This may be accomplished via the CR commands to clear the Address Interrupt or by resetting the receiver. Xon/Xoff Operation Receiver Mode Since the receiving FIFO resources in the Octal UART are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. The Octal UART provides two methods of controlling the data flow. A hardware assisted means of accomplishing control, the so–called out–of–band flow control, and an in–band flow control method. The out–of–band flow control is implemented through the CTSN–RTSN signaling via the I/O ports. The operation of these hardware handshake signals is described in the receiver and transmitter discussions. In–band flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. Two characters, Xon and Xoff, which do not represent normal printable characters take on flow control definitions when the Xon/Xoff capability is enabled. Flow control characters received may be used to gate the channel transmitter on and off. This activity is referred to as Auto–transmitter mode. To protect the channel receiver from overrun, fixed fill levels (hardware set at 12 characters) of the RxFIFO may be employed to automatically insert Xon/Xoff characters in the transmitter’s data stream. This mode of operation is referred to as auto–receiver mode. Commands issued by the host CPU via the CR can simulate all these conditions. Auto–transmitter mode When a channel receiver pushes an Xoff character into the RxFIFO, the channel transmitter will finish transmission of the current character and then stop transmitting. A transmitter so idled can be restarted by the receipt of an Xon character by the receiver, or by a hardware or software reset. The last option results in the loss of the un–transmitted contents of the TxFIFO. When operating in this mode the Command Register commands for the transmitter are not effective. While idle data may be written to the TxFIFO and it continues to present its fill level to the interrupt arbiter and maintains the integrity of its status registers. Use of ’00’ as an Xon/Xoff character is complicated by the Receiver break operation which pushes a ’00’ character on the RxFIFO. The Xon/Xoff character detectors do not discriminate this case from an Xon/Xoff character received through the RxD pin. Note: To be recognized as an Xon or Xoff character, the receiver must have room in the RxFIFO to accommodate the character. An Xon/Xoff character that is received resulting in a receiver overrun does not effect the transmitter nor is it pushed into the RxFIFO, regardless of the state of the Xon/Xoff transparency bit, MR0(7). Note: Xon /Xoff characters The Xon/Xoff characters with errors will be accepted as valid. The user has the option sending or not sending these characters to the FIFO. Error bits associated with Xon/Xoff will be stored normally to the receiver FIFO. The channel’s transmitter may be programmed to automatically transmit an Xoff character without host CPU intervention when the RxFIFO fill level exceeds a fixed limit (12). In this mode, it will conversely transmit an Xon character when the RxFIFO level drops below a second fixed limit (8). A character from the TxFIFO that has been loaded into the TxD shift register will continue to transmit. Character(s) in the TxFIFO that have not been popped are unaffected by the Xon or Xoff transmission. They will be transmitted after the Xon/Xoff activity concludes. If the fill level condition that initiates Xon activity negates before the flow control character can begin transmission, the transmission of the flow control character will not occur, i.e. either of the following sequences may be transmitted depending on the timing of the FIFO level changes with respect to the normal character times: Character Xoff Xon Character Character Character Hardware keeps track of Xoff characters sent that are not rescinded by an Xon. This logic is reset by writing MR0(3) to ’0’. If the user drops out of Auto–receiver mode while the XISR shows Xon as the last character sent, the Xon/Xoff logic will not automatically send the negating Xon. Host mode When neither the auto–receiver nor auto–transmitter modes are set, the Xon/Xoff logic is operating in the host mode. In host mode, all

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 17

activity of the Xon/Xoff logic is initiated by commands to the CRx command forces the transmitter to disable exactly as though an Xoff character had been received by the RxFIFO. The transmitter will remain disabled until the chip is reset or the CR(7:3) = 10110 (Xoff resume) command is given. In particular, reception of an Xon or disabling or re–enabling the transmitter will NOT cause resumption of transmission. Redundant CRTXon/off commands, i.e. CRTXon CRTXon, are harmless, although they waste time. A CRTXon may be used to cancel a CRTXoff (and vice versa), but both may be transmitted depending on the timing with the transmit state machine. The kill CRTX command can be used to cleanly terminate any CRTX commands pending with the minimum impact on the transmitter. Note: In no case will an Xon/Xoff character transmission be aborted. Once the character is loaded into the TX Shift Register, transmission continues until completion or a chip reset is encountered. The kill CRTX command has no effect in either of the Auto modes. Mode control Xon/Xoff mode control is accomplished via the MR0. Bits 3 and 2 reset to zero resulting in all Xon/Xoff processing being disabled. If MR0[2] is set, the transmitter may be gated by Xon/Xoff characters received. If MR0[3] is set, the transmitter will transmit Xon and Xoff when triggered by attainment of fixed fill levels in the channel RxFIFO. The MR0[7] bit also has an Xon/Xoff function control. If this bit is set, a received Xon or Xoff character is not pushed into the RxFIFO. If cleared, the power–on and reset default, the received Xon or Xoff character is pushed onto the RxFIFO for examination by the host CPU. The MR0(7) function operates regardless of the value in MR0(3:2) Xon/Xoff Interrupts The Xon/Xoff logic generates interrupts only in response to recognizing either of the characters in the XonCR or XoffCR (Xon or Xoff Character Registers). The transmitter activity initiated by the Xon/Xoff logic or any CR command does not generate an interrupt. The character comparators operate regardless of the value in MR0(3:2). Hence the comparators may be used as general purpose character detectors by setting MR0(3:2)=’00’ and enabling the Xon/Xoff interrupt in the IMR. The Octal UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid level of an Xon/Xoff recognition event is controlled by the Bidding Control Register X, BCRX, of the channel. The interrupt status can be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is interrupting. If set, an Xon or Xoff recognition event has been detected. The X Interrupt Status Register, XISR, can be read for details of the interrupt and to examine other, non–interrupting, status of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions. The character recognition function and the associated interrupt generation is disabled on hardware or software reset

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provided via status registers which can be read by the host CPU. interface and communication modes. is listed in the ”Register Map, Control”. section is listed in the ”Register Map, Data”. Table 2. GCCR – Global Configuration Control Register THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION . negation of CEN is required between cycles. UART. If b’00, no vector will be presented during an IACKN cycle. interrupt type and channel code replace the 5 LSBs of the IVR.

10 Receiver w/o error

11 Receiver with error

01 Transmitter

00 All remaining sources

volt of the Vcc and Vss power supply levels. long if the setup time of the CEN edge to Sclk can be guaranteed. elapse before the initiation of the next (synchronous) bus cycle(s). requirement of returning to the asynchronous bus cycling mode. mode until the end of the transmission of the stop bit.

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Table 3. MR0– Mode Register 0 MR1[5] and the general discussion on receiver error handling. Character recognition section. of characters in the TxFIFO. character when the RxFIFO has loaded to a depth of 12 characters. of the command register to transmit Xon/Xoff characters. only, not the interrupt generation. character detector by choosing any combination except b’00. Table 4. MR1 – Mode Register 1 PC UARTs that could not stop transmission at the proper time. . ISR. If set, the ISR reads the current status masked by the IMR, i.e. source without regard to the Interrupt Mask setting. last reset error command was issued.

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address or data byte in the ’wake up’ mode. Table 5. MR2 – Mode Register 2 The MR2 register provides basic channel setup control that may need more frequent updating. The receive clock is used for the transmitter. The TxRDY and TxEMT status bits are inactive. i.e., transmitted parity bit is as received. to transmitter link is disabled. Two diagnostic modes can also be selected. The transmit clock is used for the receiver. The TxD output is held high. The receive clock is used for the transmitter. transmission, i.e., the transmitted parity bit is as received. Program auto reset mode: MR2[5]= 1. bit time after the last stop bit.

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is being transmitted, do not affect the transmission of that character. This feature can be used to prevent overrun of a remote receiver. character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed. = 1 selects two stop bits to be transmitted. Table 6. RxCSR and TxCSR – Receiver and Transmitter Clock Select Registers below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double. Table 7. Data Clock Mux CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.

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Table 8. CR – Command Register CR is used to write commands to the Octal UART. completed before assuming the inactive state.

00001 Reserved

unread characters in the FIFO. next character, if any, is transmitted.

01010 Reserved

01011 Reserved

01100 Reserved

the chip or the individual receiver.

10000 Transmit an Xon Character

10001 Transmit an Xoff Character

10010 Reserved for channels b–h, for channel a: enables a

10011 Reserved for channels b–h, for channel a: enables Gang

Octal UART to the individual Xoff write mode. writes are ignored. The device resets to individual write mode.

10100 Reserved for channels b-h, for channel a: executes a Gang

10101 Reserved for channels b-h, for channel a: executes a

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 23

mechanism to initialize all the Xoff Character registers to a default value with one write. Execution of this command is immediate and does not effect the timing of subsequent host I/O operations.

10110 Xoff resume command (CRXoffre; not active in

“Auto-Transmit Mode”). A command to cancel a previous Host Xoff command. Upon receipt, the channel’s transmitter will transfer a character, if any, from the TxFIFO and begin transmission. 10111 Host Xoff command (CRXoff). This command allows tight host CPU control of the flow control of the channel transmitter. When interrupted for receipt of an Xoff character by the receiver, the host may stop transmission of further characters by the channel transmitter by issuing the Host Xoff command. Any character that has been transferred to the TxD shift register will complete its transmission, including the stop bit. 11000 Cancel Host transmit flow control command. Issuing this command will cancel a previous transmit command if the flow control character is not yet loaded into the TxD Shift Register. If there is no character waiting for transmission or if its transmission has already begun, then this command has no effect. 11001–11011 Reserved 11011 Reset Address Recognition Status. This command clears the interrupt status that was set when an address character was recognized by a disabled receiver operating in the special mode. 11100–11101 Reserved 11110 Resets all UART channel registers. This command provides a means to zero all the UART channels that are not reset to x’00 by a reset command or a hardware reset.

11111 Reserved for channels b-h, for channel a: executes a chip

wide reset. Executing this command in channel a is equivalent to a hardware reset with the RESETN pin. Executing in channel b-h, has no effect. Table 9. Command Register Code Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space. ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ CR[7:3] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ 00000 ÁÁÁÁÁÁÁÁÁÁÁ NOP ÁÁÁÁÁÁÁ 10000 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmit Xon ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00001 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10001 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmit Xoff ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00010 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reset Receiver ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10010 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Gang Write Xon Character Registers * ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00011 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reset Transmitter ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10011 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Gang Write Xoff Character Registers * ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00100 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reset Error Status ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10100 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Gang Load Xon Character Registers DC1 * ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00101 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reset Break Change Interrupt ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10101 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Gang Load Xoff Character Registers DC3 * ÁÁÁÁÁÁ 00110 ÁÁÁÁÁÁÁÁÁÁÁ Begin Transmit Break ÁÁÁÁÁÁÁ 10110 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Resume Command ÁÁÁÁÁÁ ÁÁÁÁÁÁ 00111 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ End Transmit Break ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 10111 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Host Xoff Command ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01000 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Assert RTSN (I/O2 or I/O1) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cancel Transmit X Char command ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01001 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Negate RTSN (I/O2 or I/O1) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01010 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Set time–out mode on ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁ 01011 ÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11011 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset Address Recognition Status ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01100 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Set time–out mode off ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01101 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Block Error Status configure ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01110 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset All UART channel registers ÁÁÁÁÁÁ ÁÁÁÁÁÁ 01111 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset Device * Table 10. SR – Channel Status Register stop bit check is made in the middle of the first stop bit position.

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parity error bit stores the received A/D bit. cleared by a reset error status command. and the transmit shift register are empty. immediately loaded to the RxFIFO. Table 11. ISR – Interrupt Status Register or may not mask the reading of the ISR as determined by MR1[6]. value of the ISR ANDed with the IMR. Interrupt Status Register, XISR. issues a reset break change interrupt command via the CR. and reset when the CPU reads the last character from the RxFIFO. character is transferred into the FIFO. meets or exceeds the value; it is reset when the fill level is less. See the description of the MR2 register.

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the same as the similar bit in the status register (SR). same as the similar bit in the status register (SR). Table 12. IMR – Interrupt Mask Register the state of the bit in the ISR has no affect on the IRQN output. input change detectors will cause an interrupt. begin interrupt arbitration. (multi-drop or wake–up mode). recognition of an in–band flow control character. condition has been detected by the channel receiver. Table 13. RxFIFO Receiver FIFO Table 14. TxFIFO – Transmitter FIFO the transmitter state machine and thus are effectively discarded. Table 15. BCRBRK – Bidding Control Register – for a break change interrupt. Table 16. BCRCOS – Bidding Control Register – for a Change of State, COS, interrupt. Table 17. BCRx – Bidding Control Register – Xon

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Table 18. BCRA – Bidding Control Register – for an address recognition event interrupt. Table 19. XonCR – Xon Character Register

8 Bits of the Xon Character Recognition

Table 20. XoffCR – Xoff Character Register

8 Bits of the Xoff Character Recognition

Table 21. ARCR – Address Recognition Character

8 Bits of the Multi–Drop Address Character Recognition

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Table 22. XISR – Xon–Xoff Interrupt Status Register in the Xon and Xoff Character Registers. user’s responsibility to transmit an Xon, when appropriate. 00 – normal. The flow control is under host control. transmitter will stop. The status will then change to b’00. 10 – re–enabled. The transmitter had been halted and restarted. 11 – disabled. The transmitter is flow controlled. channel is waiting for a data character to transfer from the TxFIFO. character transmission unless the TxFIFO is empty. Table 23. WDTRCR – Watch-dog Timer Enable receivers on the Octal UART. Table 24. BRGTRU – BRG Timer Reload 8 MSB of the BRG Timer divisor. Table 25. BRGTRL – BRG Timer Reload 8 LSB of the BRG Timer divisor. generating a baud rate clock. Table 26. BRGTCR – BRG Timer Control Register (BRGTCR) operation when the internal BRG timer is selected for their clock.

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Table 27. ICR – Interrupt Control Register used and only receiver codes are presented for interrupt arbitration. three (3) bits represent the channel number. Table 28. CIR – Current Interrupt Register are indicated in the count field of the CIR. Table 29. IVR – Interrupt Vector Register an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’. This is the unmodified form of the interrupt vector. Table 30. Modification of the IVR Table 31. GICR – Global Interrupting Channel CIR. It contains the interrupting channel code for all interrupts.

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Table 32. GIBCR – Global Interrupting Byte Count Table 33. Global Interrupting Type Register CIR. It contains the type of interrupt code for all interrupts. Table 34. GRxFIFO – Global RxFIFO Register The RxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a receiver interrupt. Table 35. GTxFIFO – Global TxFIFO Register The TxFIFO of the channel indicated in the CIR channel field. different channel than intended. Table 36. IPR – Input Port Register, The actual logic level at the I/O pin. 1 = high level; 0 =– low level. configured as an output, the associated change field will read b’0. Table 37. I/OPIOR – I/O Port Interrupt and Output Register

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Table 38. I/OPCR – I/O Port Configuration Register interrupts or can be polled, as required. RTSN function is automatically provided on I/O1. The following four registers control the function of the GOUT 0 pin. with an internal or external stimulus. See diagram below. Table 39. GPOSR – General Purpose Output Table 40. GPOR – General Purpose Output a GPOR Write or by the GPOC and GPOD registers shown below. value regardless of the port from which it was loaded. Table 41. GPOC – General Purpose Output Clk Table 42. GPOD – General Purpose Output Data with the clock selected in the GPOC.

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Figure 1. General Purpose Pin Control Logic Table 43. Summary Register Map, Control

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Table 44. Summary Register Map, Data Table 45. Register Map, Control

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 33

ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART B ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0000 (x10) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0b ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0b ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0001 (x11) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1b ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1b ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0010 (x12) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg b I/OPCRb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg b I/OPCRb ÁÁÁÁÁÁÁ 0001 0011 (x13) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKb ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0100 (x14) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSb ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0101 (x15) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0110 (x16) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXb ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 0111 (x17) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAb ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAb ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1000 (x18) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg b (XonCRb) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg b (XonCRb) ÁÁÁÁÁÁÁ 0001 1001 (x19) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg b (XoffCRb) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg b (XoffCRb) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1010 (x1A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character b (ARCRb) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character b (ARCRb) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1011 (x1B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ♣ Interrupt Control Register (ICR) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Control Register (ICR) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1100 (x1C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register b (RxCSRb) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register b (RxCSRb) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1101 (x1D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ♣ Watch-dog Timer Run Control (WDTRCR) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Watch-dog Timer Run Control (WDTRCR) ÁÁÁÁÁÁÁ 0001 1110 (x1E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register b (TxCSRb) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register b (TxCSRb) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0001 1111 (x1F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ♣ Interrupt Vector Register (IVR) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Vector Register (IVR) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART C ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0000 (x20) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0c ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0c ÁÁÁÁÁÁÁ 0010 0001 (x21) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1c ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0010 (x22) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg c I/OPCRc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg c I/OPCRc ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0011 (x23) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKc ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0100 (x24) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSc ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0101 (x25) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 0110 (x26) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXc ÁÁÁÁÁÁÁ 0010 0111 (x27) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAc ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1000 (x28) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg c (XonCRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg c (XonCRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1001 (x29) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg c (XoffCRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg c (XoffCRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1010 (x2A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character c (ARCRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character c (ARCRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1011 (x2B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 0010 1100 (x2C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register c (RxCSRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register c (RxCSRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1101 (x2D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1110 (x2E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register c (TxCSRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register c (TxCSRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0010 1111 (x2F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 34

ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART D ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0000 (x30) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0d ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0d ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0001 (x31) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1d ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1d ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0010 (x32) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg d I/OPCRd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Configuration Reg d I/OPCRd ÁÁÁÁÁÁÁ 0011 0011 (x33) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKd ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0100 (x34) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSd ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0101 (x35) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0110 (x36) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXd ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 0111 (x37) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAd ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAd ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1000 (x38) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg d (XonCRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg d (XonCRd) ÁÁÁÁÁÁÁ 0011 1001 (x39) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg d (XoffCRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg d (XoffCRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1010 (x3A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character d (ARCRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Character d (ARCRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1011 (x3B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1100 (x3C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register d (RxCSRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register d (RxCSRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1101 (x3D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 0011 1110 (x3E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register d (TxCSRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register d (TxCSRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0011 1111 (x3F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART E ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000000 (x40) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0e ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0e ÁÁÁÁÁÁÁ 01000001 (x41) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1e ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1e ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000010 (x42) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg e I/OPCRe ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg e I/OPCRe ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000011 (x43) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKe ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKe ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000100 (x44) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSe ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSe ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000101 (x45) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01000110 (x46) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXe ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXe ÁÁÁÁÁÁÁ 01000111 (x47) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAe ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAe ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001000 (x48) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg e (XonCRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg e (XonCRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001001 (x49) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg e (XoffCRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg e (XoffCRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001010 (x4A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char e (ARCRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char e (ARCRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001011 (x4B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 01001100 (x4C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register e (RxCSRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register e (RxCSRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001101 (x4D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001110 (x4E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register e (TxCSRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register e (TxCSRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01001111 (x4F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 35

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART F ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010000 (x50) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0f ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0f ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010001 (x51) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1f ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1f ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010010 (x52) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg f I/OPCRf ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg f I/OPCRf ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010011 (x53) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKf ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKf ÁÁÁÁÁÁÁ 01010100 (x54) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSf ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSf ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010101 (x55) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010110 (x56) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXf ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXf ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01010111 (x57) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAf ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAf ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011000 (x58) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg f (XonCRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg f (XonCRf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011001 (x59) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg f (XoffCRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg f (XoffCRf) ÁÁÁÁÁÁÁ 01011010 (x5A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char f (ARCRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char f (ARCRf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011011 (x5B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011100 (x5C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register f (RxCSRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register f (RxCSRf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011101 (x5D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01011110 (x5E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register f (TxCSRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register f (TxCSRf) ÁÁÁÁÁÁÁ 01011111 (x5F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART G ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100000 (x60) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0g ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0g ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100001 (x61) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1g ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1g ÁÁÁÁÁÁÁ 01100010 (x62) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg g I/OPCRg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg g I/OPCRg ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100011 (x63) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKg ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100100 (x64) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSg ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100101 (x65) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100110 (x66) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXg ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01100111 (x67) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAg ÁÁÁÁÁÁÁ 01101000 (x68) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg g (XonCRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg g (XonCRg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101001 (x69) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg g (XoffCRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg g (XoffCRg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101010 (x6A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char g (ARCRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char g (ARCRg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101011 (x6B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101100 (x6C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register g (RxCSRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register g (RxCSRg) ÁÁÁÁÁÁÁ 01101101 (x6D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101110 (x6E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register g (TxCSRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register g (TxCSRg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01101111 (x6F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 36

ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART H ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110000 (x70) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 0 MR0h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110001 (x71) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register 1 MR1h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110010 (x72) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg h I/OPCRh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OPort Configuration Reg h I/OPCRh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110011 (x73) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRBRKh ÁÁÁÁÁÁÁ 01110100 (x74) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRCOSh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110101 (x75) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110110 (x76) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRXh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01110111 (x77) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BCRAh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111000 (x78) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg h (XonCRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon Character Reg h (XonCRh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111001 (x79) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg h (XoffCRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xoff Character Reg h (XoffCRh) ÁÁÁÁÁÁÁ 01111010 (x7A) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char h (ARCRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Recognition Char h (ARCRh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111011 (x7B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111100 (x7C) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register h (RxCSRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Clock Select Register h (RxCSRh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111101 (x7D) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 01111110 (x7E) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register h (TxCSRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xmit Clock Select Register h (TxCSRh) ÁÁÁÁÁÁÁ 01111111 (x7F) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

1999 Jan 14 37

Table 46. Register Map, Data

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 38

ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART C ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0000 (xA0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register c (MR2c) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register c (MR2c) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0001 (xA1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register c (SRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register c (CRc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0010 (xA2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register c (ISRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register c (IMRc) ÁÁÁÁÁÁÁ 1010 0011 (xA3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg c (RxFIFOc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg c (TxFIFOc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0100 (xA4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg c (IPRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0101 (xA5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output c (I/OPIORc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output c (I/OPIORc) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0110 (xA6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/Xoff Interrupt Status Reg c (XISRc) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 0111 (xA7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1000 (xA8) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 1010 1001 (xA9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1010 (xAA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1011 (xAB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1100 (xAC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1101 (xAD) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 1010 1110 (xAE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1010 1111 (xAF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART D ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0000 (xB0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register d (MR2d) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register d (MR2d) ÁÁÁÁÁÁÁ 1011 0001 (xB1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register d (SRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register d (CRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0010 (xB2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register d (ISRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register d (IMRd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0011 (xB3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg d (RxFIFOd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg d (TxFIFOd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0100 (xB4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg d (IPRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0101 (xB5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output d (I/OPIORd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output d (I/OPIORd) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 0110 (xB6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/Xoff Interrupt Status Reg d (XISRd) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 1011 0111 (xB7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1000 (xBB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1001 (xB9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1010 (xBA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1011 (xBB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 1011 1100 (xBC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1101 (xBD) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1110 (xBE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1011 1111 (xBF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 39

ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART E ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000000 (xC0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register e (MR2e) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register e (MR2e) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000001 (xC1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register e (SRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register e (CRe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000010 (xC2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register e (ISRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register e (IMRe) ÁÁÁÁÁÁÁ 11000011 (xC3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg e (RxFIFOe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg e (TxFIFOe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000100 (xC4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg e (IPRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000101 (xC5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output e (I/OPIORe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output e (I/OPIORe) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000110 (xC6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/XoffInterrupt Status Reg e (XISRe) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11000111 (xC7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001000 (xC8) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11001001 (xC9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001010 (xCA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001011 (xCB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001100 (xCC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001101 (xCD) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11001110 (xCE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11001111 (xCF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART F ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010000 (xD0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register f (MR2f) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register f (MR2f) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010001 (xD1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register f (SRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register f (CRf) ÁÁÁÁÁÁÁ 11010010 (xD2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register f (ISRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register f (IMRf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010011 (xD3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg f (RxFIFOf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg f (TxFIFOf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010100 (xD4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg f (IPRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010101 (xD5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output f (I/OPIORf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output f (I/OPIORf) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010110 (xD6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/XoffInterrupt Status Reg f (XISRf) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11010111 (xD7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11011000 (xD8) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011001 (xD9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011010 (xDA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011011 (xDB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011100 (xDC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11011101 (xDD) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011110 (xDE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11011111 (xDF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 40

ÁÁÁÁÁÁÁ A(7:0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART G ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100000 (xE0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register g (MR2g) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register g (MR2g) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100001 (xE1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register g (SRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register g (CRg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100010 (xE2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register g (ISRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register g (IMRg) ÁÁÁÁÁÁÁ 11100011 (xE3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg g (RxFIFOg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg g (TxFIFOg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100100 (xE4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg g (IPRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100101 (xE5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output g (I/OPIORg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output g (I/OPIORg) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100110 (xE6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/XoffInterrupt Status Reg g (XISRg) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11100111 (xE7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101000 (xE8) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11101001 (xE9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101010 (xEA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101011 (xEB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101100 (xEC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101101 (xED) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11101110 (xEE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11101111 (xEF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UART H ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110000 (xF0) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register h (MR2h) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode Register h (MR2h) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110001 (xF1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Status Register h (SRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Command Register h (CRh) ÁÁÁÁÁÁÁ 11110010 (xF2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Status Register h (ISRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Mask Register h (IMRh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110011 (xF3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver FIFO Reg h (RxFIFOh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter FIFO Reg h (TxFIFOh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110100 (xF4) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Port Reg h (IPRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110101 (xF5) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output h (I/OPIORh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Interrupt and Output h (I/OPIORh) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110110 (xF6) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/XoffInterrupt Status Reg h (XISRh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11110111 (xF7) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11111000 (xF8) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111001 (xF9) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111010 (xFA) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111011 (xFB) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111100 (xFC) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 11111101 (xFD) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111110 (xFE) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 11111111 (xFF) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 41

Device Configuration after Hardware Reset or CRa cmd=x1F Cleared registers: Channel Status Registers (SR) Channel Interrupt Status Registers (ISR) Channel Interrupt Mask Registers (IMR) Channel Interrupt Xon Status Register (XISR) Interrupt Control Register (ICR) Global Configuration Control Register (GCCR) Hence the device enters the asynchronous bus cycling mode. Current Interrupt Register (CIR) BRG Timer Run Control Register (BRGTCR) Watch-dog Timer Run Control Register (WDTRCR) Channel Input/Output Port Configuration Registers (I/OPCR) Hence all I/O pins have direction = Input after reset BRG Counter/Timer Registers Clears Modes for: Power down Test modes Input Port Changed bits Gang write to Xon or Xoff Xon/Xoff/Address detection Receiver error status Disables: Transmitters Receivers Interrupts, current and future Halts: BRG Counters Bus cycle in progress (hardware RESET only) Limitations: Minimum RESETN pin pulse width is 10 SClk cycles after Vcc reaches operational range The user must allow a minimum of 6 SClk cycles to elapse after a reset (RESETN pin or CRa initiated) of the device terminates before initiating a new bus cycle.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 42

DC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (5V) VCC = 5.0 volts /C0034 10%; TA = –40 to 85°C; unless otherwise specified ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TEST ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ LIMITS ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ CONDITIONS ÁÁÁÁ ÁÁÁÁ MIN ÁÁÁÁ ÁÁÁÁ TYP 1 ÁÁÁ ÁÁÁ MAX ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ VIL VIH VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input low voltage2 Input high voltage (except X1/CLK) Input high voltage (X1/CLK) ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ VSS 2.0 0.8VCC ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ 0.8 Vcc Vcc ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ V ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ VOL 3 VOH VOL 3 ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Output low voltage4 Output high voltage (except OD outputs) Open Drain low voltage ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ IOL = 4.0mA IOH = –400 A IOH = –100 A IOL = 14.0 ma ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 0.8VCC 0.9VCC ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 0.15 <0.25 ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ 0.4 0.4 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ V V ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ IIL IIH ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input current low, I/O pins Input current high, I/O pins ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ VIN = 0 ViN = Vcc ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ –10 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ <0.1 <0.1 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ A ÁÁÁÁÁ ÁÁÁÁÁ IL ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input leakage current ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VIN = 0 to Vcc ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ IILCKX1 IIHCKX1 ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ X1/CLK input low current X1/CLK input high current ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ VIN=Vss,X2=Open VIN=Vcc, X2=Open ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ –450 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 450 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ A ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ IOZH IOZL ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Output off current high, 3–state data bus Output off current low, 3–state data bus ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ VIN = VCC VIN = 0 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ –10 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ <.1 <.1 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ A A ÁÁÁÁÁ ÁÁÁÁÁ IODL IODH ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Open–drain output low current in off state Open drain output high current in off state ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VIN = 0 VIN = VCC ÁÁÁÁ ÁÁÁÁ –10 ÁÁÁÁ ÁÁÁÁ <.1 <.1 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ICC ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Power supply current Operating mode 33 MHz Static Power down (No clocks, Open drains off, inputs at Vss or Vcc) ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ TTL Input levels CMOS input levels CMOS input levels ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 100 0.6 ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ 150 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ mA mA A NOTES: 1. Typical values are at +25°C, typical supply voltage and typical processing parameters. 2. All voltage measurements are referenced to VSS . For testing, all inputs swing between 0.4V and 2.4V with a transition time of 10nS maximum. For X1/CLK this swing is between 0.4V and 4.4V. all time measurements are referenced at input voltages of VIL and VIH as appropriate. 3. Test conditions for itnerrupt and I/O outputs: CL = 50pF. Test conditions for the rest of the outputs: CL = 60pF. 4. Simultaneous switching more than 6 I/O port pins from 5 volts to 0 volts at full capacitive load may ground bounce on the output pins up to 0.95 volts. 5. All R X, TX, Brg Timer, I/O pins operating at 16MHz. Sclk at 35MHz and VCC at 5.6 volts. A worst case environment.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 43

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V) VCC = 5.0 volts /C0034 10%; TA = –40 to 85°C; unless otherwise specified ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁ ÁÁÁ FIG # ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ LIMIT ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁÁ ÁÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset Timing ÁÁÁÁÁ ÁÁÁÁÁ tRES 1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESET pulse width ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ Sclk ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bus Timing ÁÁÁÁÁ ÁÁÁÁÁ tAS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A0–A7 setup time before Sclk C3 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tAH ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A0–A7 hold time after Sclk C3 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tCS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN setup time before Sclk C1 high (Sync) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN setup time before Sclk C2 high (Async) ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tCH ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN hold time after Sclk C3 high (Sync) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 1Sclk ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN hold time after Sclk C4 high (Async) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 1Sclk ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tSTP ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN high before next C2 to stop next cycle (Sync Mode)2 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tRWS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ W–Rn setup time before Sclk C2 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ tRWH ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ W–Rn hold time after Sclk C3 rising edge ÁÁÁ ÁÁÁÁ 1Sclk ÁÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle Data valid after Sclk C3 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tDF ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle data bus floating after CEN high (Sync) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle data bus floating after C4 end high (Async) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tDS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write cycle data setup time before Sclk C4 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ tDH ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write cycle data hold time after Sclk C4 rising edge ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tRWD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High time between CEN low (Async) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ Sclk ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Pin Timing ÁÁÁÁÁ ÁÁÁÁÁ tPS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O input setup time before Sclk C3 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tPH ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O input hold time after Sclk C4 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tPD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O output valid from: Write Sclk C4 rising edge (write to IOPIOR) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Timing ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ tIR ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IRQN from: Internal interrupt source active bid Reset to IRQN inactive Write IMR (set or clear IMR bit) ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ Sclk ns ns ÁÁÁÁÁ ÁÁÁÁÁ tDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IACKN cycle Data valid after Sclk C3 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Tx/Rx Clock Timing ÁÁÁÁÁ ÁÁÁÁÁ tRX ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxC high or low time ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ FRX 4 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxC frequency (16 X) (1 X) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Mhz Mhz ÁÁÁÁÁ ÁÁÁÁÁ tTX ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC high or low time ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ FTX 4 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC frequency (16 X) (1 X) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Mhz Mhz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter Timing ÁÁÁÁÁ ÁÁÁÁÁ tTXD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxD output delay from TxC low ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ ttcs ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC output delay from TxD output data ÁÁÁ ÁÁÁ –15 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Timing ÁÁÁÁÁ tRXS ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data setup time to RxC high (data) ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tRXH ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data hold time from RxC high (data) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ tsSTRT ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data low time for receiving a valid Start Bit ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ bit time

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 44

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V) (Continued) VCC = 5.0 volts /C0034 10%; TA = –40 to 85°C; unless otherwise specified ÁÁÁÁÁ ÁÁÁÁÁ SYMBOL ÁÁÁ ÁÁÁ FIG# ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ LIMITS ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁÁ ÁÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk Timing ÁÁÁÁÁ tsclkl ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Min low time at VIL (0.8V) ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ tsclkh ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Min high time at VIH (2.0V) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ Fsclk ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk frequency ÁÁÁ ÁÁÁ 0.1 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ MHz ÁÁÁÁÁ ÁÁÁÁÁ t/RFsck ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk rise and fall time (0.8 to 2.0Volts) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1/X2 Communication Crystal Clock ÁÁÁÁÁ Fx15 ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 clock frequency ÁÁÁ ÁÁÁÁ 3.6864 ÁÁÁ 8.0 ÁÁÁ MHz ÁÁÁÁÁ ÁÁÁÁÁ X1 L / H ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 Low / High time ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 135 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ T/RFx1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 Rise and Fall time ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Counter/Timer Baud Rate Clock (External Clock Input) ÁÁÁÁÁ ÁÁÁÁÁ FC/T4 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Clock frequency ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ MHz ÁÁÁÁÁ ÁÁÁÁÁ TC/TLH ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ C/T high and low time ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ TC/TO ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Delay C/T clock external to output pin ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DTACK Timing ÁÁÁÁÁ ÁÁÁÁÁ DAKdly ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK low from Sclk C4 rising edge ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ DAKdlya ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK high from CEN high (Async) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ DAKdlys ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK high from C4 end rising edge (Sync) ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port External Clock ÁÁÁÁÁ ÁÁÁÁÁ tgpirtx ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GPI to Rx/Tx clock out ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD setup to I/OP rising edge 1X mode ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OP falling edge to TxD out 1X mode ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Gout Timing ÁÁÁÁÁ GPOtdd ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GPO valid after write to GPOR ÁÁÁ ÁÁÁÁ 100 ÁÁÁ ÁÁÁ ns NOTES: 1. Timing is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it generates the several “C” timing as shown in the timing diagrams. 2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and before the C2 time of the next cycle. 3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode. 4. The minimum frequency values are not tested, but are guaranteed by design. 5. 1MHz specification is for crystal operation.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 45

DC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V) VCC = 3.3 volts /C0034 10%; TA = –40 to 85°C; unless otherwise specified ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ LIMITS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ SYMBOL ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ TEST CONDITIONS ÁÁÁÁ ÁÁÁÁ MIN ÁÁÁ ÁÁÁ TYP 1 ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ VIL VIH VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input low voltage2 Input high voltage (except X1/CLK) Input high voltage (X1/CLK) ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ VSS 0.8 * VCC 0.8 * VCC ÁÁÁ ÁÁ Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ 0.2 * VCC VCC VCC ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ V ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ VOL 3 VOH VOL 3 ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Output low voltage4 Output high voltage (except OD outputs) Open Drain low voltage ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ IOL = 3.2mA IOH = –400A IOH = –100A IOL = 10.0mA ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 0.8VCC 0.9VCC ÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁ 0.15 <0.25 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ 0.4 0.4 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ V V ÁÁÁÁ ÁÁÁÁ IIL IIH ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input current low, I/O pins Input current high, I/O pins ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ VIN = 0 VIN = VCC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ <0.1 <0.1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁ ÁÁÁÁ IL ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Input leakage current ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ VIN = 0 to VCC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁ ÁÁÁÁ IILCKX1 IIHCKX1 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ X1/CLK input low current X1/CLK input high current ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ VIN=VSS ,X2=Open VIN=VCC , X2=Open ÁÁÁÁ ÁÁÁÁ –300 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 300 ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ IOZH IOZL ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Output off current high, 3–state data bus Output off current low, 3–state data bus ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ VIN = Vcc VIN = 0 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁ Á ÁÁÁ <.1 <.1 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ A A ÁÁÁÁ ÁÁÁÁ IODL IODH ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Open–drain output low current in off state Open drain output high current in off state ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ VIN = 0 VIN = VCC ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ <.1 <.1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ A ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ICC ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ Power supply current Operating mode 33 MHz Static Power down (No clocks, Open drains off, inputs at Vss or Vcc) ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ TTL Input levels CMOS input levels CMOS input levels ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁ Á ÁÁ Á ÁÁÁ 0.6 ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ mA mA A NOTES: 1. Typical values are at +25°C, typical supply voltage and typical processing parameters. 2. All voltage measurements are referenced to VSS . For testing, all inputs swing between 0.4V and 2.4V with a transition time of 10nS maximum. For X1/CLK this swing is between 0.2V and 2.88V. all time measurements are referenced at input voltages of VIL and VIH as appropriate. 3. Test conditions for itnerrupt and I/O outputs: CL = 50pF. Test conditions for the rest of the outputs: CL = 60pF. 4. Simultaneous switching more than 6 I/O port pins from 5 volts to 0 volts at full capacitive load may ground bounce on the output pins up to 0.95 volts. 5. All R X, TX, Brg Timer, I/O pins operating at 16MHz. Sclk at 35MHz and VCC at 5.6 volts. A worst case environment.

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 46

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3V) VCC = 3.3 volts /C0034 10%; TA = –40 to 85°C; unless otherwise specified ÁÁÁÁ ÁÁÁÁ SYMBOL ÁÁÁÁ ÁÁÁÁ FIGURE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ LIMITS ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ SYMBOL ÁÁÁÁ ÁÁÁÁ FIGURE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁ ÁÁÁÁ MIN ÁÁÁÁ ÁÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁÁ ÁÁÁÁ UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reset Timing ÁÁÁÁ ÁÁÁÁ tRES 1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESET pulse width ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ Sclk ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bus Timing ÁÁÁÁ ÁÁÁÁ tAS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A0-A7 setup time before Sclk C3 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tAH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A0-A7 hold time after Sclk C3 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tCS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN setup time before Sclk C1 high (ASYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ tCS ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN setup time before Sclk C2 high (SYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tCH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN hold time after Sclk C3 high (SYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

1 Sclk

ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tCH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN hold time after Sclk C4 high (ASYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tSTP ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Cen high befoe next C2 to stop next cycle (Sync Mode)2 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tRWS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ W-Rn setup time before Sclk C2 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tRWH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ W-Rn hold time after Sclk C3 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ tDD ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle Data valid after Sclk C3 falling edge ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tDF ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle data bus floating after CEN high (ASYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tDF ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read cycle data bus floating after C4 end (SYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tDS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write cycle data setup time before Sclk C4 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tDH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Write cycle data hold time after Sclk C4 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ tRWD ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High time between CEN low (ASYNC) ÁÁÁÁ ÁÁÁÁ Sclk ÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O Port Pin Timing ÁÁÁÁ ÁÁÁÁ tPS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O input setup time before Sclk C3 falling edge (Read IPR) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tPH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O input hold time after Sclk C4 rising edge (Read IPR) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tPD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O output valid from: Write Sclk C4 rising edge (write to I/OPIOR) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Timing ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ tIR ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IRQN from: Internal interrupt source active bid Software reset to IRQN inactive Write IMR (set or clear IMR bit)) 3 to IRQN inactive ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁÁÁ Sclk ns ns ÁÁÁÁ ÁÁÁÁ tDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt vector valid after C3 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Tx / Rx Clock Timing, External ÁÁÁÁ ÁÁÁÁ tRX ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxC high or low time ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ fRX 4 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxC frequency (16 X) (1 X) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ MHz ÁÁÁÁ ÁÁÁÁ tTX ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC high or low time ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ fTX 4 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC frequency (16 X) (1 X) ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 8.0 ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ MHz MHz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmitter Timing ÁÁÁÁ ÁÁÁÁ tTXD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxD output delay from TxC low ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tTCS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxC output delay from TxD output data ÁÁÁÁ ÁÁÁÁ -15 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Timing ÁÁÁÁ ÁÁÁÁ tRXS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data setup time to RxC high (data) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ tRXH ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data hold time from RxC high (data) ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ tsSTRT ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD data low time to for receiving a valid Start Bit ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ bit time ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk Timing ÁÁÁÁ tSCLKL ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Min low time at Vil (0.8V) ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ tSCLKH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Min high time at Vih (2.0V) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 47

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3) (Continued) ÁÁÁÁ ÁÁÁÁ Fsclk ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk frequency ÁÁÁÁ ÁÁÁÁ 0.1 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ MHz ÁÁÁÁ ÁÁÁÁ T/RFsclk ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sclk rise/fall time (0.8 to 2.0Volts) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 / X2 Communication Crystal Clock ÁÁÁÁ ÁÁÁÁ Fx15 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 clock frequency ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 3.6864 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ MHz ÁÁÁÁ X1 L / H ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 Low / High time ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ T/RFx1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1 Rise / Fall time ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Counter/Timer Baud Rate Clock (External Clock Input) ÁÁÁÁ ÁÁÁÁ FC/T4 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Clock frequency ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ MHz ÁÁÁÁ ÁÁÁÁ TC/TLH ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ C/T high and low time ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ TC/TO ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Delay C/T clock external to output pin ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ 110 ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACKN Timing ÁÁÁÁ ÁÁÁÁ DAK DLY ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK low from Sclk C4 rising edge ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ DAK DLYA ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK high from CEN high (ASYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ DAK DLY ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACK high from C4 end rising edge (SYNC) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/O PORT External Clock ÁÁÁÁ TGPIRTX ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GPI to Rx/Tx clock out ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxD setup to I/OP rising edge 1X mode ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/OP falling edge to TxD out 1X mode ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ G OUT Timing ÁÁÁÁ ÁÁÁÁ GPO TDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GPO valid after write to GPOR ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 100 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ns NOTES: 1. Timing is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it generates the several “C” timing as shown in the timing diagrams. 2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and before the C2 time of the next cycle. 3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode. 4. The minimum frequency values are not tested, but are guaranteed by design. 5. 1MHz specification is for crystal operation.

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Figure 2. Basic Write Cycle, ASYNC Figure 3. Basic Write Cycle, SYNC

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Figure 4. Basic Read Cycle, ASYNC Figure 5. Basic Read Cycle, SYNC

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Figure 6. Basic IACKN Cycle, ASYNC/SYNC crystal manufacturer’s specification.

50 KOHMs

150 KOHMs

C1 and C2 should be based on manufacturer’s specification. X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively. The above figures for 5V operation. Operation at 3V is to be determined.

22 STANDARD

Figure 7. X1/X2 Communication Crystal Clock

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Figure 8. SCLK Timing Figure 9. Counter/Timer Baud Rate Clock, External Figure 10. Tx/Rx Clock Timing, External Figure 11. Transmitter and Receiver Timing

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 52

1x and 16x modes, Receiver, 9 1x and 16x modes, Transmitter, 9 A Address Recognition Character Register, 25 ARCR, 25 Asynchronous bus cycle, 6 B Baud Rate Generator , 7 BCRA, 25 BCRBRK, 24 BCRCOS, 24 BCRx, 24 Bidding Control Register – Address, 25 Bidding Control Register – Break Change, 24 Bidding Control Register – Change of State, 24 Bidding Control Register – Xon, 24 Block diagram, 6 Break, transmission of, 9 BRG Timer Control Register, 26 BRG Timer Reload Registers, Lower, 26 BRG Timer Reload Registers, Upper, 26 BRGCTCR , 26 BRGTRL, 26 BRGTRU, 26 C CEN, 6 Channel Blocks, 7 Channel Status Register, 22 Character Recognition, 7 CharacterStripping, 11 CIR, 27 Clock Register, Rx & Tx, 20 Command Register, 21 COMMAND REGISTER TABLE, 22 CR , 21 Crystal oscillator, 7 Current Interrupt Register, 27 D Description, 2 DESCRIPTION, over all, 6 F Framing error, 10 G GCCR, 17 General Purpose Output Clk Register, 29 General Purpose Output Data Register, 29 General Purpose Output Register, 29 General Purpose Output Select Register, 29 General Purpose Pins, 11 GIBCR, 28 GICR, 27 GITR, 28 Global Configuration Control Register (GCCR), 17 Global Interrupting Byte Count Register, 28 Global Interrupting Channel Register, 27 Global Registers, 8, 11 Global RxFIFO Register, 28 Global TxFIFO Register, 28 GPOC , 29 GPOD, 29 GPOR, 29 GPOSR, 29 GRxFIFO, 28 GTxFIFO, 28 H Host Interface, 6 Host interface, 6 I I/O Port Configuration Register, 29 I/O Port Interrupt and Output Register, 28 I/O ports, 10 I/OPCR, 10, 29 I/OPIOR, 28 IACKN, 8 IACKNCycle, 12 ICR, 27 IMR, 8, 24 INDEX, 51 Input Port Register, 28 Interrupt Arbitration, 11 Interrupt Control, 8 Interrupt Mask Register, 24 Interrupt priorities, Setting, 12 Interrupt sources, Enabling, 12 Interrupt Status Register, 23 Interrupt Vector Register, 27 Interrupts, Xon/Xoff, 16 IOPIOR register, 11 IPR , 28 ISR, 8, 23 IVR, 27 M Minor Modes, 14 Mode control, Xon/Xoff, 16 Mode Register 0, 18 Mode Register 1, 18 Mode Register 2, 19 Mode Registers, Initialization, 17 Modes of Operation, 13 MR0 , 18 MR1, 18 MR2, 19 Multidrop mode, 11 O Overrun error, 10 P Parity error, 10 Pin Description, 5 Pinout, 4 Polling, 12 R Receiver, 9 Receiver FIFO, 10, 24 Receiver Status Bits, 9 REGISTER DESCRIPTIONS, 17 Register Map, 30 Register Map, Control, 30, 31 Register Map, Data, 31, 36 Reset Conditons, 40 RxCSR , 20 RxFIFO, 24

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 53

S Sclk, 6 SR , 22 Synchronous bus cycle, 6 System Clock, 7 T Timing Circuits, 6 Transmitter, 8 Transmitter FIFO, 9, 24 Tx, Status Bits , 8 TxCSR , 20 TxEMT, 8 TxFIFO, 24 TxRDY, 8 U UCIR, 27 Update CIR, 12, 27 W Wake Up Mode, 14 Wake up mode, 11 Wake Up modes, 14 Wake up. Default, 14 Watch–dog Timer , 14 Watch–dog Timer Enable Register, 26 WDTRCR, 26 X XISR, 26 Xoff Character Register, 25 XoffCR, 25 Xon /Xoff characters , 15 Xon Character Register, 25 Xon–Xoff Interrupt Status Register, 26 Xon/Xoff modes, 15 Xon/Xoff Operation, 15 XonCR , 25

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 54

PLCC84: plastic leaded chip carrier; 84 leads; pedestal SOT189-3

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 55

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

Philips Semiconductors Product specification SC28L198Octal UART for 3.3V and 5V supply voltage

1999 Jan 14 56

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 01–99 Document Order No. 9397 750 04754 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.