SC26C562C1N

SC26C562 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 SC26C562 CMOS dual universal serial communications controller (CDUSCC) Product specification Supersedes data of 1995 May 01 IC19 Data Handbook

1998 Sep 04

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

21998 Sep 04 853-1663 19973

DESCRIPTION

The Philips Semiconductors SC26C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC26C562 interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER) software compatible with the existing SCN26562 (DUSCC). CDUSCC will automatically configure to the NMOS DUSCC register map (default mode) on power up. The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides sixteen common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the CDUSCC well-suited for dual-speed channel applications. Data rates up to 10Mbits per second are supported. The transmitter and receiver each contain a sixteen-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to sixteen characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions. The SC26C562 CDUSCC is optimized to interface with processors using a synchronous bus interface, such as the 8086, and iAPX86 family. For systems using an asynchronous bus, such as the 68000 and 68010, refer to the SC68C562 documentation. Refer to the CMOS Dual Universal Serial Communication Controller (CDUSCC) User’s Manual for a complete operational description.

FEATURES

• Dual full-duplex synchronous/ asynchronous receiver and transmitter
• Multi-protocol operation – BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. – COP: Single SYNC, dual SYNC, BiSYNC, DDCMP – ASYNC: 5-8 bits plus optional parity
• Sixteen character receive and transmit FIFOs with interrupt threshold control
• FIFO’ed status bits
• Watchdog timer
• 0 to 10 Mbit/sec data rate
• Programmable bit rate for each receiver and transmitter selectable from: – 19 fixed rates: 50 to 64K baud – One user-defined rate derived from programmable counter/timer – External 1X or 16X clock – Digital phase-locked loop
• Parity and FCS (frame check sequence LRC or CRC) generation and checking
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1, Manchester
• Programmable channel mode: full- or half-duplex, auto-echo, or local loopback
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface – Compatible with Synchronous and Asynchronous bus DMA controllers – Half- or full-duplex operation – Single or dual address data transfers – Automatic frame termination on counter/ timer terminal count or DMA DONE (EOPN)
• Transmit path clear status
• High speed data bus interface: 160ns bus cycle
• DPLL operation up to 312.5kHz with internal clock
• Interrupt capabilities – Vector output (fixed or modified by status) – Individual interrupt enable bits – Programmable internal priorities – Maskable interrupt conditions – 80XX/X compatible
• Multi-function programmable 16-bit counter/timer – Bit rate generator – Event counter – Count received or transmitted characters – Delay generator – Automatic bit length measurement
• Modem controls – RTS, CTS, DCD, and up to four general purpose I/O pins per channel – CTS and DCD programmable auto-enables for Tx and Rx – Programmable interrupt on change of CTS or DCD
• On-chip oscillator for crystal
• TTL compatible
• Single +5V power supply Asynchronous Mode Features
• Character length: 5 to 8 bits

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

1998 Sep 04 3

• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X Rx and Tx clock factors
• Parity, overrun and framing error detection
• False start bit detection
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Character compare with optional interrupt on match
• Transmit and receive up to 10Mbps at 1x or 1Mbps at 16x data rates Bit-Oriented Protocol
• Character length: 5 to 8 bits
• Detection and transmission of residual character: 0–7 bits
• Automatic switch to programmed character length for I field
• Zero insertion and deletion
• Optional opening PAD transmission
• Detection and generation of FLAG, ABORT, and IDLE bit patterns
• Transmit 7 or 8 bit ABORT
• Detection and generation of shared (single) FLAG between frames
• Detection of overlapping (shared zero) FLAGs
• Idle in MARK or FLAGs
• Secondary address recognition including group and global address
• Single- or dual-octet secondary address
• Extended address and control fields
• Short frame rejection for receiver
• Detection and notification of received end of message
• CRC generation and checking
• SDLC loop mode capability Character-Oriented Protocols
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• LRC or CRC generation and checking
• Optional opening PAD transmission
• One or two SYN characters
• External sync capability
• SYN detection and optional stripping
• SYN or MARK line-fill or underrun
• Idle in MARK or SYNs
• Parity, FCS, overrun and underrun error detection
• Optional SYNC exclusion from FCS
• BISYNC features – EBCDIC or ASCII header, text and control messages – SYN, DLE stripping – EOM (end of message) detection and transmission – Auto transparency mode switching – Auto hunt after receipt of EOM sequence (with closing PAD check after EOT or NAK) – Control character sequence detection for both transparent and normal text – Parity generation for data and LRC characters

ORDERING INFORMATION

DESCRIPTION Serial Data Rate = 10Mbps Maximum Serial Data Rate = 8Mbps Maximum DWG # 48-Pin Plastic Dual In-Line Package (DIP) SC26C562C1N Not available SOT240-1 52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC26C562C1A SC26C562A8A SOT238-3 ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER RATING UNITSYMBOL PARAMETER COMMERCIAL INDUSTRIAL UNIT TA Operating ambient temperature2 0 to +70 -40 to +85 °C TSTG Storage temperature -65 to +150 -65 to +150 °C VCC Voltage from VCC to GND3 –0.5 to +7.0 –0.5 to +7.0 V VS Voltage from any pin to ground3 –0.5 to VCC +0.5 –0.5 to VCC +0.5 V

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1 IACKN 27 CEN

2 A3 28 WRN

3 A2 29 EOPN

5 RTxDAKBN/ 31 D2

6 IRQN 33 D0

8 RDYN 35 CTSAN/LCAN

9 RTSBN/ 36 TxDRQAN/

10 TRxCB 37 RTxDRQAN/

11 RTxCB GPO1AN

12 DCDBN/ 38 TxDAKAN/

13 NC 39 TxDA

14 RxDB 40 RxDA

15 TxDB 41 NC

16 TxDAKBN/ 42 DCDAN/

17 RTxDRQBN/ 43 RTxCA

18 TxDRQBN/ 45 RTSAN/

19 CTSBN/LCBN 46 X2

20 D7 47 X1/CLK

21 D6 48 RTxDAKAN/

22 D5 GPI1AN

23 D4 49 A6

24 RDN 50 A5

25 RESETN 51 A4

26 GND 52 V

Figure 1. Pin Configurations

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16 DEEP

Figure 2. Block Diagram

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

1998 Sep 04 6

PIN NO. TYPE NAME AND FUNCTIONMNEMONIC DIP PLCC TYPE NAME AND FUNCTION A1–A6 4-2, 47-45 4-2, 51-49 I Address Lines: Active-high. Address inputs which specify which of the internal registers is accessed for read/write operation. D0–D7 31-28, 21-18 33-30, 23-20 I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data, command and status transfers between the CPU and the CDUSCC take place over this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during interrupt acknowledge cycles and single address DMA acknowledge cycles. RDN 22 24 I Read Strobe: Active-low input. When active and CSN is also active, causes the content of the addressed register to be present on the data bus. RDN is ignored unless CSN is active. WRN 26 28 I Write Strobe: Active-low input. When active and CSN is also active, the content of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of WRN. WRN is ignored unless CEN is active. CSN 25 27 I Chip Select: Active-low input. When active, data transfers between the CPU and the CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When CSN is high, the data lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single address DMA transfers). RDYN 7 8 O Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and the CDUSCC. It is valid only during read and write cycles where the CDUSCC is configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in the TxFIFO in the case of a write). IRQN 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC to output an interrupt vector on the data bus. IACKN 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds by either forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data bus. The vector number can be modified or unmodified by the status. If no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance. X1/CLK 43 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. When a crystal is used, a capacitor must be connected from this pin to ground. X2 42 46 O Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must be connected from this pin to ground. If an external clock is used on X1, this pin should be left floating. RESETN 23 25 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is required. RxDA, RxDB 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. TxDA, TxDB 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This output is in the marking (high) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X). TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2).

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

1998 Sep 04 7

PIN DESCRIPTION (Continued) MNEMONIC PIN NO. TYPE NAME AND FUNCTIONMNEMONIC DIP PLCC TYPE NAME AND FUNCTION CTSA/BN, LCA/BN 32, 17 35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal can be programmed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be- comes a loop control output which is asserted and negated by CDUSCC commands. This output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop. DCDA/BN, SYNIA/BN 38, 11 42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is programmable. As a DCD active-low input, it acts as an enable for the receiver or can be used as a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin and can be programmed to generate an interrupt when a transition occurs. As an active-low external sync input, it is used in COP mode to obtain character synchronization for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller applications or for the optional byte timing lead in X.21. RTxDRQA/BN, GPO1A/BN 34, 15 37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be asserted and negated under program control. TxDRQA/BN, GPO2A/BN, RTSA/BN 33, 16 36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the DMA controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be asserted and negated under program control. RTxDAKA/BN, GPI1A/BN 44, 5 48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-low. For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in single address DMA mode. TxDAKA/BN, GPI2A/BN 35, 14 38, 16 I Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low. When the channel is programmed for full-duplex single address DMA operation, this input is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode. EOPN 27 29 I/O Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and non-DMA modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO. As an output, EOPN indicates either the last DMA transfer from the RxFIFO or that the transmitted character count has reached terminal count. RTSA/BN, SYNOUTA/BN 41, 8 45, 9 O Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin. VCC 48 34, 52 I +5V Power Input GND 24 26, 13, 41, 7 I Signal and Power Ground Input

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

1998 Sep 04 8

DC ELECTRICAL CHARACTERISTICS 4,5 TA = 0°C to +70°C, VCC = 5.0V +10% 4,5 SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT Input low voltage: VIL All except X1/CLK 0.8 V X1/CLK 0.8 V VIH Input high voltage except X1/CLK 0 to 70C 2.0 V –40 to +85C 2.3 V X1/CLK 0.8 x VCC VCC V VOL Output low voltage: All except IRQN7 IOL =5.3mA(Comm), 4.8mA(Ind) V IRQN IOL =8.8mA(Comm), 7.8mA(Ind) 0.5 V VOH Output high voltage: 0.5 (Except open drain outputs) IOH = –400µA VCC –0.5 V IILX1 X1/CLK input low current10 VIN = 0, X2 = open –150 0.0 µA IIHX1 X1/CLK input high current10 VIN = VCC , X2 = GND –150 150 µA ISCX2 X2 short circuit current X1 = open, VIN = 0 VIN = VCC –15 +15 mA mA IIL Input low current –15IIL RESETN, TxDAKN, RxDAKN VIN = 0 –15 –0.5 µA II Input leakage current VIN = 0 to VCC, 0 to 70C –40 to +85C –10 +10 µA IOZH Output off current high, 3-State data busVIN = VCC, 0 to 70C –40 to +85C +10 µA IOZL Output off current low, 3-State data bus VIN = 0, 0 to 70C –40 to +85C –10 µA IODL Open drain output low current in off state: EOPN, RDYN –15 –0.5 µA IRQN VIN = 0 –1 µA IODH Open drain output high current in off state: EOPN, IRQN, RDYN VIN = VCC –1 1 µA ICC 13 Power supply current (see Figure 19 for graphs) 0 to 70C –40 to +85C 25 80 95 mA C IN Input capacitance9 VCC = GND = 0 10 pF C OUT Output capacitance9 VCC = GND = 0 15 pF C I/O Input/output capacitance9 VCC = GND = 0 20 pF NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi- tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of 6. See Figure 20 for test conditions for outputs. 7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true switching has occurred. 8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15). 9. These values were not explicitly tested; they are guaranteed by design and characterization data. 10. X1/CLK and X2 are not tested with a crystal installed. 11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate. 12. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 13. V O = 0 to VCC , Rx and Tx clocks at 10MHz, X1 clock at 10MHz.

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Figure 3. Reset Timing Wait on Rx. Receiver FIFO empty. Figure 4. Read Cycle12

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Wait on Tx. Transmitter FIFO full. Figure 5. Write Cycle12

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Figure 6. Interrupt Acknowledge Cycle Figure 7. Output Port Timing

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Figure 8. Input Port Timing Figure 9. Clock Timing

10 MHz

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CDUSCC)

1998 Sep 04 13

AC ELECTRICAL CHARACTERISTICS (Continued)

1 BIT TIME

(1 OR 16 CLOCKS) tCILTXV tCOLTXV TxC (INPUT) TxD TxC (1X OUTPUT) tCILTXV tCOLTXV TxC (INPUT) TxD TxC (1X OUTPUT) tCILTXV tCOLTXV a. Transmit Timing NRZ b. Transmit Timing FM0/1, Manchester Encoding SD00244 Figure 10. LIMITS SYMBOL PARAMETER INDUSTRIAL SC26C562 COMMERCIAL SC26C562 UNIT Min Max Min Max tCILTXV TxC input low (1X) to TxD output 120 120 nstCILTXV TxC input low (16X) to TxD output 120 120 ns tCOLTXV * TxC output low to TxD output9 (NRZ, NRZI) 25 20 nstCOLTXV FM, MAN 35 30 ns *Characterized with no loads on TxD and TxC outputs. Tester load is approximately 50pF. tRCHSOL tSILRCH tRCHSIH tRXVRCH tRCHRXI SYNOUTN SYNIN RXC (1X) INPUT RxD tRXVRCH RXC (INPUT) RxD tRCHRXI tRCHRXI tRXVRCH a. Receive Timing NRZ b. Receive Timing FM0/1, Manchester Encoding SD00245 Figure 11. LIMITS SYMBOL PARAMETER INDUSTRIAL SC26C562 COMMERCIAL SC26C562 UNIT Min Max Min Max tRXVRCH RxD data valid to RxC high: For NRZ data 25 20 ns For NRZI, Manchester, FM0, FM1 data 30 30 ns tRCHRXI RxC high to RxD data invalid: For NRZ data 25 20 ns For NRZI, Manchester, FM0, FM1 data 30 30 ns tSILRCH SYNIN low to RxC high 50 50 ns tRCHSIH RxC high to SYNIN high 20 20 ns tRCHSOL RxC high to SYNOUT low 110 100 ns

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A The TxFIFO is addressed during this write cycle. Figure 12. Transmit Dual Address DMA Timing

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A The RxFIFO is addressed during this read cycle. Figure 13. Receive Dual Address DMA Timing

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Ignored by the CDUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN. Memory read signal; not seen by CDUSCC. Figure 14. DMA-Transmit Single Address Mode

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Ignored by the CDUSCC bit; it can be used to qualify RxDAKN. Memory read signal; not seen by CDUSCC. Figure 15. DMA-Receive Single Address Mode

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Figure 16. Interrupt Timing Figure 17. Command Timing Figure 18. Relationship Between Received Data and the Loop Control Output

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i.e., CL = 150pF = 100pF discrete +50pF stray. Figure 20. Test Conditions for Outputs

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CSUSCC)

1998 Sep 04 20

DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CSUSCC)

1998 Sep 04 21

PLCC52: plastic leaded chip carrier; 52 leads; pedestal SOT238-3

Philips Semiconductors Product specification SC26C562CMOS dual universal serial communications controller (CSUSCC)

1998 Sep 04 22

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 08-98 Document order number: 9397 750 04355 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.