SC2615MLTR

SC2615 SEMTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

3.3VCC SS/EN NC 12VCC TG NC NC AGND BF_CUT PGOOD HSINKPAD BF_CUT 5V STBY BF_CUT Cout Cin 12V VDDQ VTT PWRGD 1uF 0.1uF

retemaraPl obmySs noitidnoCn iMp yTx aMs tinU egatloVylppuSV21V 21CC 8.012 12 .31V egatloVybdnatSV5V BS5 5.455 .5V tnecseiuQtupnIYBTSV5 tnerruC I )YBTS(Q 0S4 .2A m dlohserhTTUC_FB LTT tuokcoLegatloVrednUV21O LVU 21 72 .80 1V ecnerefeRkcabdeeFV FER 52.1V tnerruCkcabdeeFI BF 2A µ tnerruC3SniYBTSV5I )YBTS(Q 25 A m dlohserhTnwodtuhSNE/SSV )HT(NE 2.0V nwodtuhSlamrehT 051C °

Electrical Characteristics

Unless specified: TA = 0 to 70°C, VCC12 = 12V, VCC3 = 3.3V, 5VSTBY = 5V. Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of th e parameters specified in the Electrical Characteristics section is not implied. retemaraPl obmySm umixaMs tinU CCV3.3,egatloVylppuStupnIV 3CC 7V CCV21,egatloVylppuStupnIV 21CC 51V tnerruCtuptuOTTVI )TTV(O 3±A egatloVtupnIybdnatSV5V BS5 7V stuptuOdnastupnIO /I3 .0-DNG,3.0+YBTSV5V DNGLotDNGA 3.0±V egnaRerutarepmeTtneibmAgnitarepOT A 07ot0C ° erutarepmeTnoitcnuJgnitarepOT J 521C ° tneibmAotnoitcnuJecnatsiseRlamrehT )1( θJA 52W /C° esaCotnoitcnuJecnatsiseRlamrehT )1( θJC 4W /C° erutarepmeTegarotST STG 051ot56-C ° sdnoces01)gniredloS(erutarepmeTdaeLT LEAD 003C ° )ledoMydoBnamuH(gnitaRDSED SE2 V k POWER MANAGEMENT SC2615 2 2003 Semtech Corp. www.semtech.com

Notes: (1) Mounting considerations: The thermal copper pad on bottom of device must be soldered to a solid copper area, of 1 inch * 1 inch (min.) with multiple vias under the device to achieve specified θ JA and θ JC, (See recommended land pattern). (2) This limit indicates that the regulator has a current limit threshold that is greater than the rated Minimum current. The rated current can only be achieved if the Absolute Maximum Junctions temperatures are not violated. The amount of heatsinking determines the maximum usable VTT current. retemaraPl obmySs noitidnoCn iMp yTx aMs tinU raeniLQDDV egatloVtuptuOV TUO 1RDD0 54.25 .20 55.2V 2RDD4 67.18 .16 38.1V tnerruCtratStfoSI SS 52A µ egatloVpirTtnerrucrevOV PIRT 050 60 7% htdiwdnaBreifilpmArorrEW B5 z HM noitalugeRdaoLT xamj C°521<2 % niaGreifilpmArorrEL OA5 7b d woLdooGrewoPk nisAm10 50 04V m egakaeLhgiHdooGrewoPV 51 .02 A µ ODLYBTS tnerruCtuptuO3 S0 56A m noitalugeRdaoLT xamj C°521<2 % ODLTTV stnerruCkniSdnaecruoS )2( I TT 8.10 .2A noitalugeRdaoL 5.2% niaGreifilpmArorrEG AE 57b d Electrical Characteristics (Cont.) Unless specified: TA = 0 to 70°C, VCC12 = 12V, VCC3 = 3.3V, 5VSTBY = 5V. POWER MANAGEMENT SC2615 3 2003 Semtech Corp. www.semtech.com

4 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2615 Pin Configuration Ordering Information Pin Descriptions Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. srebmuNtraPe gakcaP RTLM5162CS )1( 81-PLM Top View (MLP-18) #niPe maNniPn oitcnuFniP 1B F. ODLybdnatsdnaQDDVehtrofkcabdeeF 2S NSTTVV TT .tupniesnesetomerdnakcabdeefODL 3D NGL. dnuorgrotalugerTTV 4Y BTSV5V CI CC morf. ybdnatsV5 6,5T TV nahtsseldecalpebtsumroticapaccimarecFµ1-Fµ1.0A.tuptuorotalugerTTV .dnuorGotsnipTTVmorfhcni52.0 7Y BTSQDDV. tuptuorotaluger"yromemotdnepsus"QDDV 8N IQDDVV ottupniylppusQDDV TT .rotaluger 9C CV3.3. liarrewoPtupnI 01D OOGP. rotacidnidoogrewoprotalugerQDDV 11T UC_FB .3SgnirudTEFSOMTUC_FBehtslortnoC.pihc"eulG"morflangisTUC_FB 21D NGA. dnuorggolanA 41,31C N. noitcennoCoN 51G T. TEFSOMtuptuoQDDVroflortnocrotalugeR 61C CV21. lortnocQDDVrofylppuS 71C N. noitcennocoN 81N E/SS. lortnocelbanE/tratstfoS

5 2003 Semtech Corp. www.semtech.com Block Diagram

6 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2615 Timing Diagram

7 2003 Semtech Corp. www.semtech.com

Description

The Semtech SC2615 DDR power supply controller is the latest and most complete linear regulator, providing the necessary functions to comply with the BF_CUT signal generated by Intel R Motherboards. The BF_CUT input signal is generated via an External “Glue Chip” and can be logically defined as : BF_CUT=S0 .NAND.P_OK Where S0 is the “Motherboard Active signal”. When S0 is logic “Low”, the motherboard is in S3 mode. The Latched BF_CUT signal is the input to the SC2615 controller, and is generated by using the S5 signal. All references made to BF_CUT are referring to the latched signal. The BF_CUT signal is inverted to externally drive a Back_Feed_Cut MOSEFT, used to prevent current flow from the VDDQ supply back to the 3.3V supply during S3 state. VDDQ supply and the VTT termination voltages are supplied to the DDR SDRAM databus during S0 (normal operation) state. During S0, VDDQ is supplied via the an external pass MOSFET from the 3.3V rail , sourcing high output currents to the VDD bus as well as supplying the termination supply current. The VTT termination voltage is an internal sink/source linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking 1.8 Amps (Min) . The current limit on this pin is set to 3 Amps (typical). The current handling capacity of this pin depends upon the amount of heat the PC board can sink from the SC2615 thermal pad. (See mounting instructions). The PC board layout must take into consideration the high current paths, and ground returns for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 3.3VCC traces must also be routed using wide traces to minimize power loss and heat in these traces, based on the current handling requirements. S3 and S5 States The operation of the VDDQ and VTT supplies is governed by the internal sequencing logic in strict adherence with Intel TM specifications with regards to the BF_CUT signal. The timing diagram demonstrates the state of the controller, and each of the VDDQ and VTT supplies during S3 and S5 transitions. When S3 is low, the VDDQ internal regulator supplies the “Suspend To RAM” current of 650 mA (max) to maintain the information in memory while in standby mode. Since the Memory read/write cycles are suspended during S3, the VTT termination voltage is not needed and is tri-stated during S3. Once BF_CUT goes low, signifying S0 mode, the VDDQ supply recovers and takes control of the VDDQ bus. The memory read-write cycles start after the Silver box POWER_OK signal goes high. The Silver-Box supply POWER_OK signal goes high when all the voltages are within a tight tolerance of the nominal voltage (typically with 1-2%). Thus, the transition from S3 to S0 does not cause a drop out in VDDQ voltage, since the higher VDDQ currents follow the transition of POWER_OK signal from the input Silver Box supply. The External VDDQ MOSFET, which is capable of supplying the higher current, is activated from the UVLO transition of the Input Rails, which occur much earlier. Thus the External MOSFET will be activated in time for the Memory’s Active state. Initial Conditions When the S5 and S3 go high (BF_CUT goes low) for the first time, the VDDQ is supplied via the external MOSFET, thus removing the burden of charging the output capacitors via the internal linear VDDQ regulator. Reset/restart The SS/EN pin must be pulled low and high again to restart the SC2615. This can be achieved by cycling the input supplies, 3.3VCC/12VCC. There is a 50mV Hysteresis on the UVLO threshold. When the rails are near the UVLO thresholds, it is possible for noise to trigger the UVLO. Since the reference for the UVLO threshold is derived from the 5VSBY voltage, sufficient bypassing of the 5VSBY improves noise immunity of the UVLO circuit. The Short Circuit Protection function is disabled when any of the input rails are below their respective UVLO thresholds. Back-feeding the Input Supply When in S3 state, VDDQ is supplied by the internal linear regulator. Current can flow back from the VDDQ supply through the body diode of the Top MOSFET to the 3.3V input supply from the Silver Box, which is off during this state. This in turn shorts out the VDDQ bus and is not Applications Information

8 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2615 desirable. A MOSFET in series with the top pass MOSFET (See typical application circuit) must block this reverse current during S3. This MOSFET can be driven from the inverted BF_CUT signal. By removing the gate drive for this series MOSFET, the current path from the VDDQ supply back into the input power source is removed. This MOSFET is enhanced during S0 state. Short Circuit Protection Short Circuit Protection is implemented by sensing the VDDQ voltage. If the SS/EN pin has risen above 1.25V (i.e. the controller has completed the startup cycle), and the output falls to 60% of its nominal voltage, as sensed by the FB pin, the TG pin is latched off and the linear controllers shut down. To recover from this condition, either the power rails have to be recycled, or the SS/EN pin must be pulled low and released to restart controller operation. The short circuit protection function is disabled when any of the input rails are below their respective UVLO thresholds. Thermal Shutdown There are three independent Thermal Shutdown protection circuits in the SC2615, the VDDQ linear regulator the VTT source regulator, and the VTT sink regulator. If any of the three regulators’ temperature rises above the threshold, that regulator will turn off independently, until the temperature falls below the thermal shutdown limit. Power Good An open collector output provides indication that the VDDQ is regulating. This is accomplished by monitoring the SS/EN pin. When the voltage on this pin has risen above 1.0V, the PGOOD goes high (open). When BF_CUT goes high (standby), the 5V and 12V rails go low, and the SS/EN also goes low. Subsequently, PWRGD will also go low, and stays low until the 3.3V and/or 12V rails are recycled and rise above their respective UVLO thresh- olds. Applications Information (Cont.)

9 2003 Semtech Corp. www.semtech.com SC2615 DDR controller’s timing : BF_CUT generated from S3 and P_OK Ch1: S3 signal to Silverbox Ch2: Power_OK from Silverbox Ch3: BF_CUT(NOT)=S3.AND.P_OK Ch4: SS/EN SC2615 DDR controller’s timing : VDDQ and VTT vs. BF_CUT Ch1: BF_CUT (NOT) Ch2: VDDQ with 2.5V offset, @ 650mA Typical Characteristics Ch3: VTT @ 650 mA Ch4: PGOOD output

10 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2615 SC2615 DDR controller’s timing : Power Good vs. SS/EN pin Ch1: BF_CUT (NOT) Ch2: VDDQ with 2.5V offset, @ 650mA Ch3: VTT @ 650 mA Ch4: PGOOD output Typical Characteristics (Cont.)

11 2003 Semtech Corp. www.semtech.com The MLP18 is a leadless package whose electrical connections are made by lands on the bottom surface of the component. These lands are soldered directly to the PC board. The MLP has an exposed die attach pad, which enhances the thermal and electrical characteristics enabling high power applications. Power handling capability of the MLP package is typically >2x the power of other SMT packages. In order to take full advantage of this feature the exposed pad must be physically connected to the PCB substrate with solder. Thermal Pad Via Design Thermal data ( θja) for the MLP18 is based on a 4 layer PCB incorporating vias which act as the thermal path to other layers. (Ref: Jedec Specification JESD 51-5). Based on thermal performance, four-layer PCB’s with vias are recommended to effectively remove heat from the device. Vias should be 0.3mm diameter on a 1.2mm pitch, and should be plugged to prevent voids being formed between the exposed pad and PCB thermal pad due to solder escaping by capillary action. Plugging can be accomplished by “tenting” the via during the solder mask process. The via solder mask diameter should be 100µm larger than the via diameter. Two layer boards have no vias, thus any heat sinking must be accomplished in the same plane as the metal traces. This will typically require an increase in the PC board area. Mounting Considerations Solder Mask Design the solder mask around all pads on each side, i.e. there should be no solder mask between adjacent terminal fingers. Exposed Pad Stencil Design It is good practice to minimize the presence of voids within the exposed pad inter-connection. Total elimination is difficult but the design of the exposed pad stencil is important, a single slotted rectangular pattern is recommended. (If large exposed pads are screened with excessive solder, the device may “float”, thus causing a gap between the MLP terminal and the PCB land metalization.) The proposed stencil designs enables out- gassing of the solder paste during reflow as well as controlling the finished solder thickness.

12 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2615 Outline Drawing - MLP-18

13 2003 Semtech Corp. www.semtech.com Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804