SC2516

SC2516 SEMTECH | Alldatasheet

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Technical content

Features

Applications

Revision 8, May. 2005 Typical Application Circuit

Description

The SC2516 is a fully integrated, Three-in-One DDR Con- troller supplying power to the VDDQ, VTT and GMCH rails. Two synchronous buck controller provide the VDDQ and GMCH at high efficiency, while an internal linear regu- lator supplies the termination voltage with 1.8A(min) Source/Sink capability. The SC2516 uses the Intel ® defined Latched BF_Cut signal to comply with motherboard state transitions. The regulator uses the 5VDUAL rail to supply VDDQ under all motherboard states, via the VDDQ switcher. The GMCH regulator is slaved off the 5V main regulator, using a sepa- rate UVLO on that rail. Additional logic and supervisory circuitry complete the functionality of this single chip DDR power solution in compliance with ACPI requirements. The MLP package with a copper pad provides excellent thermal impedance while keeping small footprint. VDDQ short circuit protection along with VTT current limit as well as two independent thermal shutdown circuits as- sure safe operation under all fault conditions. ‹ Power Solution for DDR memory per Intel motherboard specification ‹ High speed data line termination ‹ Uses Latched BF_Cut from Intel Glue Chip to control regulators ‹‹‹‹‹ External VDDQ divider allows DDRI or DDRII Com- patibility ‹ High efficiency VDDQ switcher ‹‹‹‹‹ External GMCH divider allows 1.5V or 1.25V pro- gramming ‹ High efficiency GMCH switcher supplies pro- grammed output from the 5V or 3.3V rail ‹ Single chip solution complies fully with ACPI power sequencing specifications ‹ 1.8A (min) VTT Source/Sink capability ‹ High current 1Amp gate driver for VDDQ switcher ‹ Independent thermal shutdown for VTT ‹ Fast transient response ‹ Space saving 22-pin MLP package with copper thermal pad for heatsinking to PC Board VDDQ 3VCC 5VSBY GMCH VTT 12VCC FB_GMCH FBVDDQ FBVDDQ VDDQ Latched BF_CUT SC2516 11 12 COMP FBVDDQ SS/EN VTTGND VTT VDDQ AGND VTTFB REFSENS FB_GMCH SS_GMCH POK GND_GMCH BG_GMCH TG_GMCH BF_CUT COMP_GMCH 5VSBY BST TG BG PGND TH_PAD ATXPWR_OK VDDQ FB_GMCH 5Vdual SS/EN

2© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of th e parameters specified in the Electrical Characteristics section is not implied. retemaraPl obmySm umixaMs tinU DNGAotTSB,egatloVylppuSV TSB 02V egatloVtupnIybdnatSV YBSV5 7V stupnIO /I3 .0-DNGA,3.0+YBTSV5V DNGLroDNGPotDNGA 3.0V tnerruCtuptuOTTVI )TTV(O 2-/+A egnaRerutarepmeTtneibmAgnitarepOT A 07ot0 oC erutarepmeTnoitcnuJgnitarepOT J 521 oC tneibmAotnoitcnuJecnatsiseRlamrehT θ AJ 52 o W/C esaCotnoitcnuJecnatsiseRlamrehT θ CJ 4 o W/C egnaRerutarepmeTegarotST GTS 051ot56- oC egatloVCDHCMG_GB/HCMG_GT/GB/GT 3.0-DNGP,3.0+TSBV egatloVCAHCMG_GB/HCMG_GT/GB/GT 0.4-DNGP,0.1+TSB Sn001<t )%05ot%05morfderusaem( V )ledoMydoBnamuH(gnitaRDSED SE2 V K

Electrical Characteristics

retemaraPl obmySs noitidnoCn iMp yTx aMs tinU egatloVYBSV5V YBSV5 5.455 .5V tnerruCtnecseiuQI )YBSV5(Q wolTUC_FB2 16 1 Am hgiHTUC_FB8 0 1 dlohserhTTUC_FB 8.0L TT4 .2V dlohserhTKO_P 8.0L TT4 .2V tuokcoLegatloVrednUYBSV5O LVU YBSV5 4.27 .23 V ecnerefeRkcabdeeFQDDVV FER 832.15 2.13 62.1V QDDVt nerruCkcabdeeFI BF V BF V52.1=2 -A u dlohserhTnwodtuhSNE/SSV )HT(NE nwodtuhS@TTV/QDDV3 .05 .0V nwodtuhSlamrehTT NDHS-J 051 oC nwodtuhSlamrehTs iseretsyHT TSYH-J 01 oC Unless specified: T A = 25 oC , 5VSBY = 5V

3© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Electrical Characteristics (Cont.) retemaraPl obmySs noitidnoCn iMp yTx aMs tinU rehctiwS noitalugeRdaoLI QDDV A01otA0=2 .0% ycneuqerFrotallicsOf CSO 5220 525 72z HK tnerruCtratStfoSI SS V SS Vm008=0 25 20 3A u elcyCytuDmumixaM 570 8% egatloVpirTtnerrucrevOV PIRT tniopteSQDDVfo%0 75 70 8% emiTesiRetaGpoTG T R Fp0004=ecnaticapacetaG5 2S n emiTllaFetaGpoTG T F Fp0004=ecnaticapacetaG5 2S n emiTesiRetaGmottoBG B R Fp0004=ecnaticapacetaG5 3S n emiTllaFetaGmottoBG B F Fp0004=ecnaticapacetaG5 3S n emiTdaeDt d 020 50 8S n ecnatcudnocsnarTreifilpmArorrEG m 8.01 2 .1S m CD@niaGreifilpmArorrEA AE R PMOC nepo=8 3B d htdiwdnaBreifilpmArorrEG WB 5z HM tnerruCecruoSreifilpmArorrE V1=PMOC,0=BF5 50 75 8A u tnerruCkniSreifilpmArorrE V1=PMOC,V5.1=BF0 70 90 11A u pmaRlanretnIV PMAR kaeP-ot-kaeP5 5.0V ODLTTV egatloVtuptuOT TVV QDDV V005.2=5 32.10 52.15 62.1V stnerruCkniSdnaecruoSI TTV V QDDV V005.2=8 .1-8 .1+A stnerruCkniSdnaecruoSI TTV V QDDV V005.1=4 .1-4 .1+A noitalugeRdaoL ∆ /TTV ∆I I TTV A8.1-otA8.1+=1 -1 +% niaGreifilpmArorrEA TTV_AE 57B d timiLtnerruCT TV MILI wol=TUC_FB3 A Unless specified: TA = 25oC, 5VSBY = 5V.

4© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Electrical Characteristics (Cont.) Unless specified: TA = 25oC,5VSBY = 5V. retemaraPl obmySs noitidnoCn iMp yTx aMs tinU rehctiwSHCMG ecnerefeRkcabdeeFHCMGV HCMG_FER 832.15 2.13 62.1V tnerruckcabdeeFHCMGI HCMG_BF V HCMG_BF V52.1=2 -A u noitalugeRdaoLI HCMG A5otA0=2 .0% ycneuqerFrotallicsOf CSO 5220 525 72z HK tnerructratstfoSI HCMG_SS V SS Vm002=8 0 12 1A u elcyCytuDmumixaM 570 8% emiTesiRetaGpoTG T R Fp0002=ecnaticapacetaG0 4S n emiTllaFetaGpoTG T F Fp0002=ecnaticapacetaG0 4S n emiTesiRetaGmottoBG B R Fp0002=ecnaticapacetaG0 4S n emiTllaFetaGmottoBG B F Fp0002=ecnaticapacetaG0 4S n emiTdaeDt d 055 80 21S n ecnatcudnocsnarTreifilpmArorrEG m 8.01 2 .1S m CD@niaGreifilpmArorrEA AE 83B d htdiwdnaBreifilpmArorrEG WB 1z HM tnerruCecruoS/kniSreifilpmArorrEV HCMG_BF V1=PMOC,V5.1-0=0 65 70 9A u pmaRlanretnIV PMAR kaeP-ot-kaeP5 5.0V Pin Configuration Ordering Information Note: Pin 23 is the thermal Pad on the bottom of the device srebmuNtraPe gakcaP RTLM6152CS )1( 22-PLM TRTLM6152CS )2(,)1( 22-PLM Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free package. Device is fully WEEE and RoHS compliant.

5© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 #niPe maNniPn oitcnuFniP 1P MOC .rehctiwSQDDVehtrofreifilpmaecnatcudnocsnartMWPehtrofnipnoitasnepmoC 2Q DDVBF .daolfotniopehttaesnesQDDVehtottcennoC.rotalugerQDDVehtrofkcabdeeF 3N E/SS. rellortnocelbasidotwollluP.DNGotroticapactratstfoS 4D NGTTVT TV nipsihtotgnitcennocecartehT.tnerrucnruterTTVgniyrracenalpreppocottcennoC.nruter .spmA2yrracotelbaebtsum 5T TV gnitcennocecartehT.spmA8.1sknisrosecruoS.QDDV2/1otsetalugeR.tuptuorotalugeRTTV .spmA2yrracotelbaebtsumnipsihtot 6Q DDVT TVottupnirewopQDDV .spmA2yrracotelbaebtsumnipsihtotgnitcennocecartehT.ODL 7D NGA .dnuorgsihtottcennocroticapaCtratStfoSehtdnastnenopmocnoitasnepmoC.dnuorggolanA 8B FTTV .liarTTVehtrofdaoLfotnioPottcennoC.rotalugerTTVehtroftupniesneS 9S NSFER fotnioPottcennoC.egatlovstifo2/1otdetalugereblliwTTV.liarQDDVehtroftupniesneS .detarenegsiyromemehtrofFERVehterehw,daoL 01H CMG_BF .liarHCMGehtrofdaoLfotnioPottcennoC.HCMGehtroftupniesneS 11H CMG_SS .DNGotroticapacatcennoC.rehctiwsHCMGroftratstfoS 21K OP. rewopXTAmorflangisKOrewopottcennoC 31H CMG_DNG .TEFmottobfoecruoSottcennoC.rotalugerHCMGehtrofdnuorGnruterevirDetaG 41H CMG_GB. rotalugerHCMGehtrofevirdetaGTEFmottoB 51H CMG_GT. rotalugerHCMGehtrofevirdetaGTEFpoT 61T UC_FB. pihCeulGmorftupniTUC_FBdehctaL 71H CMG_PMOC rehctiwSHCMGehtrofreifilpmaecnatcudnocsnartMWPehtrofnipnoitasnepmoC 81Y BSV5. tupniYBTSV5ottcennoC 91T SB lanoitiddanA.roticapac/edoidpartstoobgnisudetareneG.subevirdetaGmottoBdnapoTehT lacipytees(.evirdGBehtrofegatlovpartstooBkaepehtpartotderiuqeroslasiedoid )tiucricnoitacilppa 02G T. evirdetagTEFpoT 12G B. evirdetagTEFmottoB 22D NGP. ecruosTEFmottobotesolcnipsihtpeeK.nruterevirdetaG 32D AP_HT rednuenalpdnuorgotdetcennocebtsumtI.gniknistaehrofdesupihcfomottobnodapreppoC .CI Pin Descriptions

6© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Block Diagram

7© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Timing Diagram ATX _POK SS/EN VTT VDDQ S5 S0 S0 S5S3 VCC_Rail BF_CUT TG BG GMCH TG_GMCH BG_GMCH SS_GMCH ATX _POK SS/EN VTT VDDQ S5 S0 S0 S5S3 VCC_Rail BF_CUT TG BG GMCH TG_GMCH BG_GMCH SS_GMCH

8© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516

Application information

The SEMTECH SC2516 DDR power supply controller is the latest and most complete, Three in One switching and linear regulator controller, providing the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. The SC2516 uses the Latched BF_CUT input signal which is generated externally on Intel R P4 Motherboard glue chip to comply with the power sequencing requirements. Logically, the BF_CUT signal can be represented as: OKPSCUTBF _3_ •= (For details of the Latched BF_CUT signal definition, refer to Intel documentation). Where S3 is the input to the Silver-box Supply for Suspend to RAM, (S3=1 for Suspend to RAM) and P_OK is a signal generated by the Silver-box supply, indicating that all rails are within specification. S3 and S5 StatesS3 and S5 StatesS3 and S5 StatesS3 and S5 StatesS3 and S5 States During S3 and S5 sleep states, The operation of the VDDQ and VTT is governed by the intel R specifications with regards to the BF_CUT signal. The timing diagram demonstrates the state of the controller and each of the VDDQ, VTT and GMCH supplies during S3 and S5 transitions VDDQ Power Section SC2516 architecture eliminates the need for the Back- Feed Cut MOSFET, since the VDDQ is always supplied from the same input voltage bus (5V dual). The SC2516 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply from the 5V main input rail. Power SequencingPower SequencingPower SequencingPower SequencingPower Sequencing Once BF_CUT signal low and P_OK signal goes high, The VDDQ supply will be activated with S0 as well. The SS/ EN pin voltage is charged by internal constant current source. When SS/EN voltage reaches to 0.3V (typical), High side driver begins chopping and main power is activated as an asynchronous Buck converter. When SS/ EN voltage reaches to 1.25V (typical), Low side driver begins chopping and main power is activated as a synchronous Buck converter. When BF_CUT signal goes high (S3 state), the VDDQ switcher is always on and is sourced by 5VSTBY rail during this time. When both BF_CUT and P_OK signals are low, The VDDQ supply be disabled with S5 as well. Both high side and low side drivers are pulled low. Short Circuit ProtectionShort Circuit ProtectionShort Circuit ProtectionShort Circuit ProtectionShort Circuit Protection Short circuit protection is implemented by sensing the VDDQ output voltage. If it falls to 75% (typical) of its nominal voltage, as sensed by the FB pin, the TG and BG pins are latched off and the VDDQ switcher is shutdown. It will shutdown the VTT also, since the VTT regulator is fed from the VDDQ bus. To recover from the short circuit protection mode, either the 5VSBY rail has to be recycled, or the SS/EN pin must be pulled below 0.3V and released to restart VDDQ switcher operation. GMCH Power Section The SC2516 Switching controller supplies a 1.5V or 1. 25V GMCH (Graphic Memory Control Hub) voltage via a standard synchronous BUCK converter typically connected to the 5VCC or 3.3VCC power rail from Silver- box supply. Base on the basic advantage of switching mode controller, The GMCH output current can support up to 20A. Power SequencingPower SequencingPower SequencingPower SequencingPower Sequencing Since the Chip-Set supply should come up before the Active Memory cycle, the GMCH supply is sequenced with the rising edge of the P_OK signal from Sliver-box supply. Thus the GMCH regulator drivers are on when P_OK signal is greater than its respective threshold. The external MOSFET gates are pulled low when P_OK signal is lower than its threshold. Thus the GMCH is disabled during S3 and S5 (See timing diagram). VTT Rail The VTT termination voltage is supplied via an internal sink/source linear regulator when BF_CUT is low, and the P_OK signal has met its threshold voltage and SS/ EN voltage reaches to 1V. When BF_CUT is high, the VTT termination voltage is not needed and is thus tri-stated. The VTT linear regulator is capable of sourcing and sinking 1.8 Amps (Minimum). It is recommended that one should use at least 470uF low ESR capacitor and 1uF ceramic capacitor (from VTT pin to Ground with short distance) to ensure the stable operation. Short Circuit ProtectionShort Circuit ProtectionShort Circuit ProtectionShort Circuit ProtectionShort Circuit Protection The VTT regulator has two internal current limit circuits, one for the sink and one for the source regulators. Both current limits are set at 3Amp (typical). If maintained at current limit, the internal regulators act like constant current sources, and supply the max current until the device temperature raises above thermal shutdown thresholds, at which point that regulator shuts down.

9© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Applications Information (Cont.) The control model of SC2516 VDDQ and GMCH section can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of: The compensation network includes a resistor and a ca- pacitor in series, which terminates from the output of the error amplifier to the ground. The PWM gain is inver- sion of the ramp amplitude, and this gain is given by: where the ramp amplitude (peak-to-peak) is 0.55 volts . The total control loop-gain can then be derived as follows: Ts() T o 1s R . C. sR. C. 1s R c. C o. 1s R c C o. L R o . s2 L. C o. 1 R c R o where The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accom- plish the goal: (1) Calculate the corner frequency of the output filter: (2) Calculate the ESR zero frequency of the output filter capacitor: (3) Check that the ESR zero frequency is not too high. If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high fre- quency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB fre- quency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: when Fig. 1. SC2516 small signal model. C Vbg 1.25Vdc L RcR Co Gpwm EA Ro Vin F esr F sw G pwm V ramp T o G m G pwm⋅ V in⋅ R⋅ V bg Vo ⋅:= F o 2 π⋅ LC o⋅⋅ F esr 2 π⋅ R c⋅ C o⋅ F x_over F sw R 1 Gpwm Vin⋅ G m⋅ F esr F o F x_over F esr Vo V bg ⋅:= F o F esr< F x_over< Gm 0.001 A⋅ V Compensation design of the VDDQ ChannelCompensation design of the VDDQ ChannelCompensation design of the VDDQ ChannelCompensation design of the VDDQ ChannelCompensation design of the VDDQ Channel

10© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Applications Information (Cont.) Step 1. Output filter corner frequency F o = 1.6 KHz Step 2. ESR zero frequency: F esr = 3.537 KHz Step 3. Check the following condition: Which is satisfied in this case. Step 4. Choose crossover frequency and calculate compensator R: F x_over = 50 KHz R = 15 K Ω Step 5. Calculate the compensator C: C = 33 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85 oC that en- sures the loop stability. Fig. 2 shows the Bode plot of the loop. or R 1 Gpwm Vin⋅ G m⋅ F o F esr F x_over F o Vo V bg ⋅:= when (5) The compensation capacitor is determined by choos- ing the compensator zero to be about one fifth of the output filter corner frequency: (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equa- tions provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. (7) An additional capacitor should be reserved at the compensation pin to ground to have another high fre- quency pole. An example is given below to demonstrate the proce- dure introduced above. The parameters of the power supply (typical for VDDQ section) are given as : F esr F sw F esr F o< F x_over< F zero F o C 1 2 π. R. F zero. Vin 5V⋅:= Vo 2.5 V⋅:= Io 20 A⋅:= Fsw 250 KHz⋅:= L 2.2 µH⋅:= Co 4500 µF⋅:= Rc 0.01 Ω⋅:= Vbg 1.25 V⋅:= Vramp 0.55 V⋅:= Gm 0.001 A⋅ V Compensation design of the GMCH ChannelCompensation design of the GMCH ChannelCompensation design of the GMCH ChannelCompensation design of the GMCH ChannelCompensation design of the GMCH Channel The configuration of the PWM comparator of GMCH channel is such that its inverter input is connected to Comp_GMCH and the non-inverter input is connected to the internal ramp. The peak voltage of the internal ramp is 1.1V and the valley voltage is 0.55V. When COMP_GMCH voltage is below 0.55V, the maximum duty cycle will be generated by PWM comparator. If COMP_GMCH voltage is over 1.1V then the minimum duty cycle will be generated. To ensure proper soft start function of the GMCH channel, COMP_GMCH voltage must rise above 1.1V at the beginning of soft start period quickly. So a higher compensation gain is required. The following example shows that by choosing the compensation parameters as 15kOhm and 27nF for a typical output filter with 1~2uH inductor and 2000uF capacitor (ESR of 8~12 mOhm), the circuit will yield smooth soft start, stable control loop, and satisfactory transient response. The measured Bode plot of the loop gain is shown in Figure

11© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Applications Information (Cont.) 10 100 1 .10 3 1 .10 4 1 .10 5 1 .10 650 100 Loop Gain Mag (dB) mag i () F i 10 100 1 .10 3 1 .10 4 1 .10 5 1 .10 6180 135 Loop Gain Phase (Degree) phase i () F i Fig. 2. Bode plot of the VDDQ Channel Fig. 3. Bode plot of the GMCH Channel

12© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Typical application Schematic IPD 09N 03 C11 1500uF Q1IPD 09N 03 C20 1500uF SC2516 1234567891011 12 13 14 15 16 17 18 19 20 21 22 COMPFBVDDQSS/ENVTTGNDVTTVDDQAGNDVTTFBREFSENSFB_GMCHSS_GMCH POK GND_GMCHBG_GMCHTG_GMCHBF_CUT COM P_GM CH 5VSBY BST TG BG PGND TH_PAD IPD 09N 03 2R2 C151uF VDDQ R61k Latched BF_CUT 1500uF R8200R FB_GMCH 27nF C23 1000uF D31N4148 C52.2nF C131uF C10 1500uF C22 1000uF 1.5V GMCH C4 33n 1N 4148 L2 1.5uH IPD 09N 03 1N 4148 2R2 FBVDDQ C161uF SS/EN C71uF R2 2R2 2R2 R101K FBVDDQ L1 1.5uH C81uF C1100p C6100n R41k FB_GMCH 5VSBY 12VCC 3VCC C181uF VDDQ VDDQ R1 15K C19 4.7uF ATXPWR_OK VTT C2122nF R5 15K C14 470uF 4.7uF C17 non pop. 5Vdual C12 1500uF

13© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Application Schematic for Intel Broadwater platform R4442R C21 10uF FB_GMCH C14 470uF R80R L2 1.2uH 5VSBY IPD 05N 03LA 1500uF C20 1500uF VDDQ 2R2 IPD 05N 03LA R10non. pop. 27nF 2R2 FBVDDQSS/EN C181uF C71uF R5 15K FB_GMCH C12 1500uF 1.25V GMCH C1100p C25 10uF R61k FBVDDQ 2R2 C161uF 1N 4148 C4 33n C81uF IPD 05N 03LA SC2516 1234567891011 12 13 14 15 16 17 18 19 20 21 22 COMPFBVDDQSS/ENVTTGNDVTTVDDQAGNDVTTFBREFSENSFB_GMCHSS_GMCH POK GND_GM CHBG_GMCHTG_GMCHBF_CUT COMP_GMCH 5VSBY BST TG BG PGND TH_PAD C26 10uF R2 2R2 12VCC 1.8VDDQ C22 2200uF 5Vdual 0.9VTT C19 4.7uF C52.2nF L1 1.2uH C10 1500uF C11 1500uF ATXPWR_OK C23 2200uF C24 10uF 4.7uF Q1IPD 05N 03LA C151uF 1N 4148 C2122nF C131uF D31N4148 Latched BF_CUT VDDQ C17 non pop. 3VCC C6100n 15K

14© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Outline Drawing - MLP-22

15© 2005 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2516 Contact Information Semtech Corporation Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804 Land Pattern- MLP-22