SC2450_07 SEMTECH | Alldatasheet
Document overview
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Technical content
Features
Applications
Revision: January 17, 2007 Typical Application Circuit
Description
Selectable dual output or bi-phase operation Direct drive for N-channel MOSFETs Undervoltage lockout Synchronization to external clock Multi-converter synchronization Soft start Fast transient response Max duty cycle 45% Output over voltage protection Thermal shutdown 28-Pin SO lead free package available. Fully WEEE and RoHS compliant Power supplies for advanced telecoms/datacoms SO IP, Ethernet and PABX power supplies The SC2450 can be configured as a dual converter or a bi-phase converter for high current applications. The part is designed for point of use power supplies with 8.5-30V nominal backplane power sources. Multiple supplies can be synchronized together to prevent low frequency har- monics on the backplane. The power dissipation is con- trolled using a novel low voltage supply technique, allow- ing high speed and integration, with the high drive cur- rents to ensure low MOSFET switching loss. The use of high speed switching circuits allows very nar- row PWM outputs down to 15:1 voltage ratios. Single pin compensation for each channel simplifies develop- ment as well as reducing external pin count. Capable of driving MOSFETs via external driver transis- tors for phase currents beyond 20A.
2 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450
Electrical Characteristics
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3 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristics (Cont.) retemaraPs noitidnoCn iMp yTx aMs tinU kcolClanretxE emiTtceteDs n05<emiTesiR2 s µ emiTkcolnU 010 5s µ egnaRycneuqerF 72.01 z HM evirDetaGediShgiH elcyCytuDxaM 54% ecruoSkaePC DAOL Fn01=1 A kniSkaePC DAOL Fn01=1 A evirDetaGediSwoL ecruoSkaePC DAOL Fn01=2 A kniSkaePC DAOL Fn01=2 A gnimiTevirDcnyS palrevo-noNniMC DAOL V1<evirDteFFn1=0 20 5s n hctaMMWPF ,elcyCytuD%05 CSO zHM1=1 -1 % sniPtupnIcigoL tnerruCsaiBtupnIV NI V5-0=0 1-0 1A µ dlohserhTcigoL 8.0V dlohserhTelbasiD2BF V CC V7.0-V noitcetorPtnerruCrevO dlohserhTPCO 3015 117 21V m tnerruCsaiBP/I+COV NI V42=0 07A µ tnerruCsaiBP/I-CO 05A µ noitcetorPegatloVrevO dlohserhTPVO 021% nwodtuhSlamrehT 051C ° Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. Unless specified VIN = 24V, TA = 25°C
4 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Pin Configuration Ordering Information Notes: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. rebmuNtraPE GAKCAP )1( T BMA T( A) RTWSI0542CS 82-OSC °58+-04- TRTWSI0542CS )2( BVE0542CSd raoBnoitaulavE0542CS Top View (28-Pin SOIC) Block Diagram
5 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 niPe maNniPn oitcnuFniP 11 BF. 1lennahcrofkcabdeeF 21 PMOC. 1lennahcrofnoitasnepmoC 3C N. noitcennocoN 4G B. ecnadepmiecruosK3,sreifilpmarorrerofecnereferV1 52 BF. 2lennahcrofkcabdeeF 62 PMOC. 2lennahcrofnoitasnepmoC 7V RDGER. rotsisnartssaplanretxerofevirdrotalugeR 8E LBANE. elbasidotdnuorgottcennoc,V50.2sidlohserhtelbanE 92 ESAHP. 2lennahcroftupniedonesahP 012 HVRD. 2lennahcedishgihrofevirdetaG 112 HTSB. 2lennahcedishgihroftupnipartstooB 212 LVRD. 2lennahcediswolrofevirdetaG 312 LTSB. 2lennahcediswolrofylppuS 41C CV. ylppusrewopCIdetaluger-erP 511 LTSB. 1lennahcediswolrofylppuS 611 LVRD. 1lennahcediswolrofevirdetaG 711 HTSB. 1lennahcedishgihroftupnipartstooB 811 HVRD. 1lennahcedishgihrofevirdetaG 911 ESAHP. 1lennahcedishgihroftupniedonesahP 02D NGP. dnuorgrewoP 12+ CO. tupnignitrevnirotarapmoctnerrucrevO 222 -CO. 2lennahcroftupnignitrevni-nonrotarapmoctnerrucrevO 321 -CO. 1lennahcroftupnignitrevni-nonrotarapmoctnerrucrevO 42K LCTXE .tneserpsilangisdilavanehwtupnisihtotskcolretrevnoc,kcolclanretxE 52T UOKLC .sretrevnocrehtoroflangisgnizinorhcnysedivorpotevirdlevelcigol,tuokcolC 62C N. noitcennocoN 72D NGA. dnuorggolanA 82F ERR .rotarenegpmardnarotallicsolanretnirofrotsiserecnereferlanretxE Pin Descriptions
6 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Typical Application Schematic for Two Channel Operation
7 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Bill of Material for Two Channel Operation Typical Application (Cont.) metIy tQe cnerefeRe ulaV/rebmuNtraPr erutcafunaM 18 8 C-1C. reC,V05,Fµ74.0y nA 23 5 2C,42C,9C6 021,.reC,Fµ33.0y nA 32 1 1C,01C6 021,.reC,Fn22y nA 41 2 1C6 021,.reC,Fµ1.0y nA 52 4 1C,31C6 021,.reC,Fn01y nA 61 5 1C6 021,.reC,Fp74y nA 76 3 2C,22C,12C,02C,91C,61C. tnaT,V53,Fµ22y nA 82 8 1C,71C. mulA,V53,Fµ086y nA 92 7 2C,62C6 021,.reC,Fn2.2y nA 013 0 5C,92C,82C6 021,.reC,Fn0.1y nA 111 0 3C6 021,.reC,Fµ0.1y nA 211 15 4C,44C,34C,24C,14C,04C,73C,63C,33C,23C,13C6 021,.reC,Fµ01y nA 314 9 3C,83C,53C,43C .mulA,V3.6,Fµ0051y nA 414 6 D,5D,2D,1D ,FLEM,ykttohcS,V04,A1 M9185N1 ynA
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8 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Typical Application (Cont.) Bill of Material for Two Channel Operation (Cont.) metIy tQe cnerefeRe ulaV/rebmuNtraPr erutcafunaM 524 6 1R,51R,41R,31R 0121,%5,W4/1,2.2y nA 621 * 13R,91R,*71R 6021,0,rotsiserpihCy nA 722 1 2R,02R6 021,%1,k00.1y nA 821 2 2R6 021,%1,k23.2y nA 921 3 2R6 021,%1,k20.4y nA 032 7 2R,62R6 021,%5,02y nA 131 8 2R6 021,%5,01y nA 231 9 2R6 021,%5,15y nA 331 4 3R6 021,%5,k51y nA 431 6 3R6 021,%1,k1.86y nA 531 7 3R6 021,%1,k0.01y nA 630 * 2coR,*1coR6 021,%1,DBTy nA 731 0 542CS ,rellortnoClauD/esahP-iB W82-OS .proChcetmeS WSI0542CS:N/P 1112-894-508 Notes: 1. * Indicates optional parts. 2. Some parts are selected due to availability or lead time, and are not optimized.
9 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Typical Application (Cont.) Schematic for Bi-Phase Operation
10 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristic Curves Phase Node Waveform of Two-Channel Application Circuit (Vin = 24V, Load Current = 12A for 5V, Load Current = 18A for 3.3V) Overall System Efficiency vs. Overall Load (W) of the 5V and 3.3V channels 60.00% 65.00% 70.00% 75.00% 80.00% 85.00% 90.00% 95.00% 0 20 40 60 80 100 120 Output Power (W) Efficiency Efficiency ch1: Vphase5V; ch2: Vphase3.3V Efficiency in Two-Channel Application Circuit (5V/12A, 3.3V/18A) Two Channel Operation
11 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristic Curves (Cont.) 3.3V Channel Gate Waveform (Vin = 24V, Load Current = 18A) ch1: VgateH; ch2: VgateL 5.0V Channel Gate Waveform (Vin = 24V, Load Current = 12A) ch1: VgateH; ch2: VgateL
12 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout1 = 5.0V/12A, Vout2 = 3.3V /18A) ch1: Vout5.0V; ch2: Vout3.3V Bi-Phase Operation (Vout = 3.3V, Max. Load Current = 20A) Overall System Efficiency vs. iLoad 60.00% 65.00% 70.00% 75.00% 80.00% 85.00% 90.00% 0 5 10 15 20 Load Current (A) Efficiency Overall Efficiency Efficiency in Bi-Phase Application Circuit (3.3V/20A)
13 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristic Curves (Cont.) Phase Node Waveform (Vin = 24V, Vout = 3.3V, Load Current = 20A) ch1: Vphase1; ch2: Vphase2 Gate Waveform (Vin = 24V, Vout = 3.3V, Load Current = 10A/phase) ch1: VgateL; ch2: VgateH
14 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout = 3.3V, Load Current = 5A/phase) ch1: Vout Theory of Operation The SC2450 employs a voltage mode control with feed forward to provide fast output response to load and line transients. The SC2450 has two outputs, which can be used to gen- erate two separate supply voltages or can be combined in bi-phase operation to generate one single supply volt- age. The internal reference is trimmed to 1 V with +/-1% accuracy, and the outputs voltages can be adjusted by two external resistors. In bi-phase operation, the dual switching regulators are operated 180° out of phase. Load current sharing between phases is normally re- quired, and this can be achieved by using precise feed- back voltage divider resistors (typically 0.1%) to match individual phase output voltage. In addition, small droop- ing resistors ( could be PCB traces) are employed at the output of each phase to enhance phase current balance. PWM Control Changes on the output voltages are fed to the inverting input of the Error Amplifiers, by the FB1 and FB2 pins, and compared with the internal 1 V reference. The com- pensation to the transconductance amplifier is achieved by connecting a capacitor in series with a resistor from the COMP1 and COMP2 pins to AGND respectively. The error signal from the error amplifier is compared to the saw tooth waveform by the PWM comparator, and Oscillator Frequency Selection The sawtooth signal is generated by charging an internal capacitor with a current source. The charge current is set by an external resistor connected from the RREF pin to AGND. The oscillator frequency and the external resis- tance follow an inversely proportional relationship. Feed Forward The SC2450 incorporates a voltage feed forward scheme to improve line transient immunity when changes of the input voltage occur. As the input voltage changes, the ramp valley to peak voltage of the internal oscillator fol- lows this change instantly. As a result the output voltage will have minimum disturbance due to the input line change. Synchronized Operation The internal oscillator can be synchronized to an exter- nal clock operating in the range of 270 kHz to 1 MHz. The switching frequency of each channel is one half of the oscillator frequency. The oscillator clock is also avail- able externally through the CLKOUT pin and can be used to provide synchronization for other converters. matched timing signal is generated to control the upper and lower gate drives of the two phases. A single Ramp signal is used to generate the control signals for both of phases, hence the maximum duty cycle is less than 50%.
15 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Bias Generation A 6-7 Volt supply voltage is required to power up the SC2450. This voltage could be provided by an external power supply or derived from VIN through an external pass transistor. REGDRV is the control signal to the base of the pass transistor that will regulate VCC. The voltage at the VCC pin is compared to the internal voltage refer- ence, and the REGDRV pin can sink up to 5 mA current to regulate the voltage at the VCC pin. Enable If the ENABLE pin is connected to logic high, the SC2450 is enabled, while connecting it to ground will put the de- vice into disabled mode. The ENABLE pin can also be configured as input UVLO through input voltage divider resistors. The controller will be enabled when the EN- ABLE pin voltage reaches 2.05 V, and will be disabled with 400 mV hysteresis. Under Voltage Lockout Under Voltage lockout (UVLO) circuitry senses VCC through a voltage divider. If this signal falls below 5.8 V, with a typical hysteresis of 400 mV, the BG pin is pulled low by an internal transistor causing the lower MOSFET gate to be on and the upper MOSFET gate off for both phases. Over Voltage Protection The SC2450 provides OVP protection for each output individually. Once the converter output voltage exceeds 120% nominal output voltage, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset once the OVP condition is removed. Soft Start An external capacitor at the BG pin is used to set up the Soft Start duration. The capacitor value, in conjunction with the internal 3K resistor at the BG pin, control the duration to bring up the bandgap to its final level. As the BG capacitor is being charged through the internal resis- tor, the PWM pulse opens accordingly until the bandgap is charged completely. This controlled start up of the PWM prevents output voltage overshoot, unnecessary component stress, and noise generation during start up. Theory of Operation (Cont.) Over Current Protection The SC2450 current limit provides protection during an over current condition. A sense resistor or PCB trace can be used to sense the input supply current. The over current protection trip point is determined by the voltage drop across the sense resistor. Once this voltage drop exceeds 115 mV, OCP protection circuit will be triggered. Due to component and layout parasitics, filtering might be necessary across the OC+ and OC- pins. It is recommended to use 20 Ohm resistor and 10 nF capacitor for filtering. The OCP accuracy may be affected by non-ideal PCB layout and MOSFET variations. To ac- commodate these variations, the OCP threshold can be externally adjusted by a voltage divider across the sense resistor to attenuate the voltage drop across the sense resistor, so that increase the OCP threshold accordingly. See application circuits. Once an over current condition occurs, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset at the beginning of the next clock cycle. The cycle is repeated indefinitely until the over current condition removed. Thermal Shutdown In addition to current limit, the SC2450 monitors over temperature condition. The over temperature detection will shut down the part if the SC2450 die temperature exceeds 150°C, and will auto reset once the die tem- perature is dropped down. Gate Drive The SC2450 integrates high current gate drivers for fast switching of large MOSFETs. The high-side gates can be switched with peak currents of 1 Amp, while the larger low-side gates can be switched with peak currents of 2 Amps. A cross conduction prevention circuitry ensures a non-overlapping operation between the Upper and Lower MOSFETs. This prevents false current limit tripping and provides high efficiency.
16 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 The control model of SC2450 can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of: Vbg C R Vin Co Rc Ro L R2 R1 Error-Amp 0 0 0 0 Gpwm Verror Duty The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accom- plish the goal: (1) Calculate the corner frequency of the output filter: O O CL2 1:F
- •π• (2) Calculate the ESR zero frequency of the output filter capacitor: OC esr CR2 1:F
- •π• (3) Check that the ESR zero frequency is not too high. FF SW ers < If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner fre- quency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. Control Loop Design Fig. 1. SC2450 control model. The compensation network includes a resistor and a ca- pacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is propor- tional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by: RAMP PWM V 1:G = where the ramp amplitude (peak-to-peak) is 3 volts when input voltage is 24 volts. The total control loop-gain can then be derived as follows: Ts() T o 1s R. C. sR. C. 1s R c. C o. 1s R c C o. L R o . s2 L. C o. 1 R c R o where R 1 R 2 . . . (4) Choose the loop gain cross over frequency (0 dB fre- quency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency or the output ripple frequency in bi-phase mode opera- tion: FF SW OVER_X ≤ If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immu- nity. The resistor in the compensation network can then be calculated as: R 1 G pwm V in. G error. F esr F o F x_over F esr V o V bg when: F o F esr < F x_over < V A002.0:GERROR =
17 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Control Loop Design (Cont.) Step 1. Output filter corner frequency Fo = 1.453 KHz Step 2. ESR zero frequency: Fesr = 2.653 KHz Step 3. Check the following condition: Which is satisfied in this case. Step 4. Choose crossover frequency and calculate compensator R: Fx_over = 30 KHz R = 5.89 K Ω Step 5. Calculate the compensator C: C = 92.98 nF Step 6. Generate Bode plot and check the phase mar- gin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. or when (5) The compensation capacitor is determined by choos- ing the compensator zero to be about one fifth of the output filter corner frequency: (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equa- tions provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. An example is given below to demonstrate the proce- dure introduced above. The parameters of the power supply are given as: R 1 G pwm V in. G error. F o F esr F x_over F o V o V bg F zero F o C 1 2 π. R. F zero. F esr F o< F x_over< F ers F sw V in := 24 V V o := 2.5 V I o := 20 A F sw := 150 KHz L := 4 µH C o := 3000 µF R c := 0.02 Ω R 1 := 1.5 KΩ R 2 := 1.0 KΩ
18 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Good layout is necessary for successful implementation of the SC2450 bi-phase/dual controller. Important layout guidelines are listed below. 1). The high power parts should be laid out first. The para- sitic inductance of the pulsating power current loop (start from positive end of the input capacitor, to top MOSFET, then to bottom MOSFET back to power ground) must be minimized. The high frequency input capacitors and top MOSFETs should be close to each other. The freewheel- ing Schottky diode, the bottom MOSFET snubber, and the bottom MOSFET should be placed close to each other. The MOSFET gate drive and current sense loop areas should be minimized. The gate drive trace should be short and wide. 2). The layout of the two phases should be made as sym- metrical as possible. The SC2450 controller should be placed in the center of the two phases. Please see evalu- ation board layout as an example. 3). Separate ground planes for analog and power should be provided. Power current should avoid running over the analog ground plane. The AGND is star connected to the PGND at the converter output to provide best possible ground sense. Refer to the application schematics, cer- tain components should be connected directly to the AGND. 4). If a multi-layer PCB is used, power layer and ground layer are recommended to be adjacent to each other. Typically the power layer is on the top, followed by the ground layer. This results in the least parasitic inductance in the MOSFET-capacitor power loop, and reduces the ringing on the phase node. The rest of the layers could be used to run DC supply traces and signal traces. An example of a two-layer PCB layout is given below to illustrate these layout principles. Control Loop Design (Cont.) ma g i() Fi 10 100 1103 1104 1105 1106 100 Loop Gai n M ag (dB) phase i() Fi 10 100 1103 1104 1105 1106 180 135 Loop Gai n Phase (Degree) Layout Guidelines Fig. 2. Bode plot of the loop
19 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Component Side (TOP) Copper (TOP) Layout Guidelines (Cont.)
20 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Copper (BOTTOM) Layout Guidelines (Cont.) PGND AGND
21 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2450 Semtech Corporation Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804 Contact Information Land Pattern - SO-28 DETAIL A N D .041 .013 .104 .100 .012 2.35 (1.04) 1.04 0.33 - 2.65 2.55 0.30 h h 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. -B- CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS AND TO BE DETERMINED AT DATUM PLANE NOTES: 2. -A- -H- SIDE VIEW A B C De H e/2 bbb C A-B D SEE DETAIL A L (L1) 0.25 PLANE GAGE c (.041) .013 .004 .016 .008 .081 .004 .093 8° 0° 0.33 0.10 - 8° 0.40 0.20 2.05 0.10 .050 BSC .406 BSC .010 .291 .295 .012 - 0.25
1.27 BSC
10.30 BSC
7.50 .299 7.40 .020 0.31 7.60 0.51 .705 2X N/2 TIPS SEATING aaa C E/2 ccc C 2 3 AA2 A1bxN PLANE REFERENCE JEDEC STD MS-013, VARIATION AE.4. E ccc aaa bbb MAX DIMENSIONS e L N h c E D b MINDIM A INCHES NOM MILLIMETERS NOMMIN MAX THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: REFERENCE IPC-SM-782A, RLP NO. 307A.2. X P (.362) (9.20) ZG Y (C) 7.00.276 1.27.050 0.60.024 2.20.087 11.40.449 INCHES DIMENSIONS Z P Y X DIM C G MILLIMETERS Outline Drawing - SO-28