SC2441A

SC2441A_09 SEMTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 37

Technical content

Features

Applications

/g117Low voltage distributed DC-DC converters /g117Telecommunication power supplies /g117Servers and base stations 2-Phase Synchronous Step-down Controllers /g1172-Phase Synchronous Continuous Conduction Mode /g117Out of Phase Operation for Low Input Current Ripple /g117Operates up to 1MHz Per Channel /g117Excellent Current Sharing Between Phases /g117Duty Cycle Up to 90% /g1170.5V Feedback voltages for Low-Voltage Outputs /g117Starts into Pre-biased Outputs /g117Adaptive Shoot-through Protection /g117Lossless Inductor DCR Current Sensing /g11723mV Current-limit Threshold /g117Individual Soft-start, Overload Hiccup and Enable Step-up Regulator /g1170.27V VCESAT Switch at 0.6A /g117Fixed frequency Current-mode Control Common Features /g117Wide input Voltage Range: 1.8V to 20V /g117Synchronizing Frequency Equal to that of the Step- down Converters /g11728-lead TSSOP-EDP Lead-free package, fully WEEE and RoHS compliant Typical Application Circuit Figure 1 R21 Vin RCS+2 C21 R26 VCC R23 VCC C8 D4 R11 22 20 SW3 PGND1 GDH2 BST2 FB1 PGND2 SYNC/SHDN CS1+ CKOUT COMP1 SS1/EN1 CS1- SS2/EN2 COMP2 FB2 COMP3 CS2- CS2+ PLLF FB3 BST1 GDH1 GDL1 GDL2 VCC ROSC GND IN R15 R16 R19 VOUT1 C22 L2 R8 VCC Signal Ground C24 R24 C26 R13 Power Ground C25 R10 R18 L1 C5 C20 R20 R25 R12 C19 C23 C13 C11 VOUT2 Vin R27 RCS+1 C12 SC2441A

2 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Absolute Maximum Rating

Electrical Characteristics

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of th e parameters specified in the Electrical Characteristics section is not implied. retemaraPl obmySs noitidnoCn iMp yTx aMs tinU tuokcoLegatlovrednU V CC dlohserhTtratSV HTCC V CC gnisaercnI5 4.45 5.4V V CC siseretsyHOLVUV LTCC V CC gnisaerceD0 51V m V CC tnerruCtupnII CC V CC V,V8= S/S V2= V CC V,V4= LTCC V, S/S V2= V CC V,V8= S/S )2(V0= 50.0 0.1 Am sreifilpmArorrE2dna1lennahC egatloVkcabdeeFV ,1BF V 2BF VNI V5,V3=V < CC V01<4 94.00 05.06 05.0V VNI V5,V3=V < CC ,V01< C°58otC°04- 594.00 05.05 05.0V tnerruCsaiBtupnIniPkcabdeeF I 1BF 06-0 02-A n I 2BF 082-0 05-A n ecnatcudnocsnarTreifilpmAG ,1M G 2M 513 Ωµ 1− niaGegatloVpooLnepOa 1o a, 2o 57B d htdiwdnaBniaGytinUreifilpmA) 1etoN(5 z HM tnerruCkniStuptuOreifilpmAV 2,1BF V,V1= 2,1PMOC V5.2=6 14 29 2 µA tnerruCecruoStuptuOreifilpmAV 2,1BF V,V0= 2,1PMOC V5.2=9 3 16 1 µA Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ , -40°C < TA = TJ < 105°C retemaraPl obmySs gnitaRmumixaMs tinU egatloVtupnIV NI 02ot3.0-V rellortnoCnwoD-petSroFegatloVylppuSV CC 02ot3.0-V segatloVylppuSrevirDediS-hgiHV 1TSB V, 2TSB 82ot3.0-V egatloV2BF,1BFV 1BF V, 2BF 02ot3.0-V segatloV2PMOC,1PMOCV 1PMOC V, 2PMOC 5.4ot3.0-V )-(2SCdna)+(2SC,)-(1SC,)+(1SC segatloV V ,)+(1SC V )-(1SC V, )+(2SC ,V )-(2SC Vot3.0- CC V egatloVNDHS/CNYSV S/S Vot3.0- NI 1+V egatloVCSORV CSOR 2ot3.0-V segatloV2NE/2SSDNA1NE/1SSV 1SS V, 2SS 4ot3.0-V egatloV3BFV 3BF 4V egatloV3WSV 3WS 03ot3.0-V erutarepmeTnoitcnuJmumixaMT J 051C ° esaCotnoitcnuJecnatsiseRlamrehT θ CJ 2W /C° tneibmAotnoitcnuJecnatsiseRlamrehT θ AJ 73W /C° egnaRerutarepmeTegarotST GTS 051ot06-C ° ces01)gniredloS(erutarepmeTdaeLT DAEL 003C ° )ledoMydoBnamuH(sgnitaRDSED SE0 002V

3 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Electrical Characteristics (Cont.) Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ , -40°C < TA = TJ < 105°C retemaraPl obmySs noitidnoCn iMp yTx aMs tinU noitarepOMWProfdlohserhTPMOC V )+(1SC =V )-(1SC 0= tuptuOelgniSesahP-2roFegatloV2BF noitarepOfoedoM 55.1V pooLdekcoL-esahPdnarotallicsO ycneuqerFgninnuReerFf OCC TJ V;C°52= FLLP V1>0 540 050 55z HK ycneuqerFgnikcoLmuminiMV FLLP nepo0 42z HK gnikcoLmuminiM/ycneuqerFgninnuReerF ycneuqerF TJ C°52=7 .10 .2 tnerruCtuptuOpmuPegrahCI FLLP V FLLP V1=0 15 10 2 µA elcyCytuDmumixaM D ,1XAM D 2XAM 880 9% elcyCytuDmuminiMD ,1NIM D 2NIM 0% egatloVhgiHtupnINDHS/CNYSV HS/S 5.1V egatloVwoLtupnINDHS/CNYSV LS/S 5.0V tnerruCtupnINDHS/CNYSI S/S V S/S V2.0= V S/S V2=0 4 06 µA yaleDnwodtuhS )1etoN(5 8 µs egatloVhgiHtuptuOkcolCT UOKC H I TUOKC 08-= µA6 .18 .1V egatloVwoLtuptuOkcolCT UOKC L I TUOKC 002= µA4 .0V srotarapmoCtimiL-tnerruCdnaMWP,sreifilpmAesneS-tnerruC egnaRedoMnommoCtupnI 0V CC 1-V dlohserhTtimiLtnerruCV ,1MILI V 2MILI V CC V8= V )-(1SC =V )-(2SC V0= 813 28 2V m dlohserhTtimiLtnerruCV ,1MILI V 2MILI V CC V8= V )-(1SC =V )-(2SC V5= 813 28 2V m tnerruCsaiBtupnIesneS-tnerruCevitisoPI ,)+(1SC I )+(2SC V )+(1SC =V )-(1SC 0= tnerruCsaiBtupnIesneS-tnerruCevitageNI ,)-(1SC I )-(2SC V )+(1SC =V )-(1SC 0= V )+(2SC =V )-(2SC 0= 04-5 7- µA emit-nOMWPmuminiM TA 52=° ) 1etoN(,C 081s n srevirDetaG tnerruCecruoSkaePevirDetaGediS-hgiH )1etoN(2 A tnerruCkniSkaePevirDetaGediS-hgiH )1etoN(2 A tnerruCecruoSkaePevirDetaGediS-woL )1etoN(2 A

4 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Electrical Characteristics (Cont.) retemaraPl obmySs noitidnoCn iMp yTx aMs tinU tnerruCkniSkaePevirDetaGediS-woL )1etoN(2 A emiTesiRevirDetaGC L Fp0033=0 3s n emiTllaFevirDetaGC L Fp0033=0 3s n elbanEdnaffotuhSdaolrevO,tratS-tfoS daolrevOelbanEotegatloVtratS-tfoS pucciH V ,1NESS V 2NESS V 1SS dnaV 2SS gnisaercnI3 .3V dlohserhTBFpucciHdaolrevO V ,1LOBF V 2LOBF V 2,1SS V5.3= BF 1 dnaB F 2 gnisaerceD 53.08 3.01 4.0V tnerruCegrahcsiDtratS-tfoS I ,)SID(1SS I )SID(2SS V 1BF =V 2BF =V 3.0 V 1SS =V 2SS =V3 69 2 1 µA retfAtratseRotegatloVtratS-tfoS nwodtuhSdaolrevO V ,1TSRSS V 2TSRSS V 1SS dnaV 2SS gnisaerceD5 .0V egatloVNE/SSelbasiDlennahC 6.0V noitarepOMWProfdlohserhTNE/SS V )+(1SC V= )-(1SC 0= retrevnoCtsooB VNI dlohserhTtratSV HTNI VNI gnisaercnI3 7.16 7.1V VNI siseretsyHV LTNI 001V m tnerruCsaiBniPkcabdeeFI 3BF 040 52A n ecnatcudnocsnarTreifilpmAkcabdeeFG 3M 07 Ωµ 1- niaGpooL-nepOreifilpmAkcabdeeFa 3o 05B d ycneuqerFgnihctiwSretrevnoCtsooB f 3CSO 1z HM elcyCytuDhctiwSmumixaMD 3XAM 582 9 % egatloVnoitarutaShctiwSretrevnoCtsooBV TASEC I WS A6.0=7 2.0V tnerruCegakaeLhctiwStsooBI EGAKAEL V WS V21=5 µA timiLtnerruChctiwStsooBI TIMIL 6.08 .0A nwodtuhSlamrehT 551C ° siseretsyHnwodtuhSlamrehT 01C ° Notes: (1) Guaranteed by design not tested in production. (2) Input current is dominated by the equivalent gate drive current to external MOSFETs in active switching condition. Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ , -40°C < TA = TJ < 105°C

5 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Pin Configurations Ordering Information eciveDe gakcaP erutarepmeT T(egnaR A) TRTETA1442CS )2,1( PDE-82-POSSTC °58ot04- BVEA1442CSd raoBnoitaulavE Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for the TSSOP-28-EDP package. (2) Lead free product. This product is fully WEEE and RoHS compliant. CKOUT IN SW3 PLLF PGND2 SS1/EN1 BST1 CS1+ PGND1 CS1- GDH1 SYNC/SHDN GDL1 FB3 VCC COMP3 GDL2 GND GDH2 ROSC BST2 FB1 SS2/EN2 COMP1 CS2+ COMP2 CS2- FB2 TSSOP-28 EDP Top View

6 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Pin Descriptions niPe maNniPn oitcnuFniP 1N I etarenegotdesutonsiretrevnoctsoobfiCCVoteiT.retrevnoCtsooBehtrofegatloVylppuS .ylppusyrailixua 2F LLP. pooLkcoLesahPehtrofniPnoitasnepmoC

31 NE/1SS

retrevnocnwod-petstsrifehttesnipsihtotdeitroticapaclanretxenadnarotsiserlanretxenA 1lennahcffostuhsV6.0wolebnipsihtgnilluP.emitelcycpuccihdaolrevostidnaemittrats-tfos .srevirdetag 4+ 1SC .rotarapmoC/reifilpmAesnes-tnerruC1lennahCehtottupnIgnitrevni-noNehT 5- 1SC ehtotdeityllamroN.rotarapmoC/reifilpmAesnes-tnerruC1lennahCehtottupnIgnitrevnIehT .retrevnocehtfotuptuo 6N DHS/CNYS elbaneotV5.1evobaegatlovaotro)1niP(NIotnipsihteiT.tupnInwodtuhSdnanoitazinorhcnyS tsoobehtdnasrellortnocnwod-petshtobffostuhsV5.0wolebnipsihtgnilluP.A1442CSeht retrevnoctsoobehT.A1442CSehtsezinorhcnyskcolclanretxenahtiwnipsihtgnivirD.rotaluger ehttaetareposrellortnocnwod-petsehtsaerehwycneuqerfkcolclanretxeehtfoeciwttasnur .ycneuqerfkcolc 73 BF 3TUOrofredividevitsiserlanretxenaotdeitsi3BF.reifilpmArorrEtsooBottupnIgnitrevnIehT .gnittesegatlov 83 PMOC V4.0wolebnipsihtgnilluP.noitasnepmocpoolrofdesU.tuptuOreifilpmArorrEretrevnoCtsooB .retrevnocpu-petsehtselbasid 9D NG. dnuorGgolanA 01C SOR .ycneuqerfgninnur-eerfrotallicsoehtstesDNGotnipsihtmorfdetcennocrotsiserlanretxenA 111 BF neewtebredividevitsiserlanretxenaoteiT.reifilpmArorrE1lennahCehtottupnIgnitrevnIehT .gnisnesegatlovtuptuorofdnuorgehtdna1TUO 211 PMOC .noitasnepmocpoolrofdesU.tuptuOreifilpmArorrE1lennahC 312 PMOC .noitasnepmocpoolrofdesU.tuptuOreifilpmArorrE2lennahC 412 BF neewtebredividevitsiserlanretxenaoteiT.reifilpmArorrE2lennahCehtottupnIgnitrevnIehT tuptuoelgnisesahp-owtrofCCVroNIoteiT.gnisnesegatlovtuptuorofdnuorgehtdna2TUO .noitarepo 51- 2SC ehtotdeityllamroN.rotarapmoC/reifilpmAesnes-tnerruC2lennahCehtottupnIgnitrevnIehT .retrevnocehtfotuptuo 61+ 2SC .rotarapmoC/reifilpmAesnes-tnerruC1lennahCehtottupnIgnitrevni-noNehT

712 NE/2SS

retrevnocnwod-petsdnocesehttesnipsihtotdeitroticapaclanretxenadnarotsiserlanretxenA 2lennahcffostuhsV6.0wolebnipsihtgnilluP.emitelcycpuccihdaolrevostidnaemittrats-tfos .noitarepotuptuoelgnisesahp-owtrofnepoevaeL.srevirdetag 812 TSB nadnaroticapacpartstoobaottcennoC.evirDetaGreppU2lennahCrofylppuSdeppartstooB .edoidlanretxe 912 HDG otdnuorgmorfsgniwsegatlovevirdetaG.TEFSOMreppU2lennahCroftuptuOevirDetaG .2TSBV

7 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Pin Descriptions (Cont.) 022 LDG morfsgniwsegatlovevirdetaG.TEFSOMsuonorhcnyS2lennahCroftuptuOevirDetaG .CCVotdnuorg 12C CV ehT.srevirDetaGTEFSOMsuonorhcnySehtdnasrellortnoCnwod-petShtoBrofegatloVylppuS sTEFSOMrewopehtecnahneyllufothguonehgihtonsiNIVfiCCVsetarenegretrevnoctsoob eiT.srellortnocnwod-petsehtrofegatlovylppusyrailixuanasedivorpretrevnoctsoobehtdna .dedeentonsiretrevnoctsoobehtfiNIVotCCV 221 LDG morfsgniwsegatlovevirdetaG.TEFSOMsuonorhcnyS1lennahCroftuptuOevirDetaG .CCVotdnuorg 321 HDG otdnuorgmorfsgniwsegatlovevirdetaG.TEFSOMreppU1lennahCroftuptuOevirDetaG .1TSBV 421 DNGP .srevirDetaGehtfonruteRdnuorGrewoP 521 TSB nadnaroticapacpartstoobaottcennoC.evirDetaGreppU1lennahCrofylppuSdeppartstooB .edoidlanretxe 622 DNGP .rettimEhctiwStsooB 723 WS .edoidgnileehweerfdnarotcudnitsoobaottcennoC.rotcelloChctiwStsooB 82T UOKC. )b(5erugiFnimargaidgnimiteeS.tuptuokcolC DAPdesopxE .noitcudnoclamrehtecnahneotenalpdnuorglangisehtotderedlosylreporpebtsuM

8 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Block Diagram Figure 2 Functional Diagram of the Step-down Controllers IN OSCILLATOR AND PHASE DETECTOR SLOPE1 ILIM1 CLK2 R Q S OL1 Soft-Start And Overload Hiccup Control 1 UVLO 4.3V/4.5V Adaptive Shoot-through Protection PWM1 ROSC CS1+ CS1- CLK1 REFERENCE ISEN1 /g83/g32 /g32 DSBL1 VCC BST1 GDH1 GDL1 PGND1 25mV SS1/EN1 FB1 FAULT GND COMP1 VIN UVLO 0.5V 0.35V FREQUENCY DIVIDER CLK 1.25V 1.6/1.7V SLOPE COMP SHDN SLOPE2 SHDN SYNC/SHDN GDH2 GDL2 PLLF BST2 VCC SLOPE2 I ILIM2 R Q S OL2 Soft-Start And Overload Hiccup Control 2 PWM2 FB2 CS2- ISEN2 25mV /g83/g32 /g32 DSBL2 COMP2 CS2+ SEL CLK2 1.25V ANALOG SWITCH SS2/EN2 SEL A Y B Adaptive Shoot-through Protection EA1 0.5V 1.25V R CKOUT TG1ON 1.25V R TG2ON EA2 0.5V 1.25V 1.25V CH 1 CH 2 MUX

Figure 5. Phase-Locked Loop (a) and Its Timing Diagram in Locked Condition (R2 not Used) (b).

12 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Typical Characteristics Feedback Pin Input Bias Current vs Tem perature 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 Temperature (°C) Feedback Pin Input Bias Current (nA) VCOMP2 = 3V Channel 2 VCOMP1 = 3V Channel 1 Amplifier Transconductance vs Temperature 200 220 240 260 280 300 320 340 360 380 400 -50 -25 0 25 50 75 100 125 Temperature (°C) Amplifier Transconductance ( /g109/g87/g45/g49) Amplifier Open Loop Gain vs Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Amplifier Open Loop Gain (dB) Step-down Channel Feedback vs Temperature 0.45 0.47 0.49 0.51 0.53 0.55 -50 -25 0 25 50 75 100 125 Temperature (°C) Reference Voltage (V) VIN = 3V VCC = 8V Percenatge Frequency Deviation From Nominal vs Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Deviation (%) ROSC = 40.2K/g87 ROSC = 51.1K/g87 ROSC = 66.5K/g87 Step-down Channel Switching Frequency vs T em perature 350 400 450 500 550 600 650 -50 -25 0 25 50 75 100 125 Temperature (°C) Frequency (KHz) ROSC = 40.2K/g87 ROSC = 51.1K/g87 ROSC = 66.5K/g87

13 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Typical Characteristics Clock Output High Voltage vs Tem perature 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 -50 -25 0 25 50 75 100 125 Temperature (°C) Clock Output High Voltage (V) ICLK_OUT = - 80 µA Clock Output Low Voltage vs Temperature 0.03 0.04 0.05 0.06 0.07 0.08 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) Clock Output Low Voltage (V) ICLK_OUT = 200 µA Charge Pump Current IPLLF vs Tem perature 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) Charge Pump Current I PLLF (µA) VPLLF = 1V Current Sense A mplifier Input Bias Current vs Temperature (Non-inverting Pin) -0.60 -0.55 -0.50 -0.45 -0.40 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Sense Amplifier Input Bias Current ( µA) VCC = 8V, V CS1 (-) = VCS2 (-) = 0V SYNC/SHDN Input Voltage vs Temperature 0.9 1.0 1.1 1.2 1.3 1.4 1.5 -50 -25 0 25 50 75 100 125 Temperature (°C) SYNC/SHDN Input High Voltage (V) SYNC/SHDN Input High SYNC/SHDN Input Low

14 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Typical Characteristics VIN Start-up Threshold Voltage vs Temperature 1.70 1.71 1.72 1.73 1.74 1.75 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) VIN Start-up Threshold Voltage (V) VIN Hy steresis Voltage vs Tem perature 0.075 0.080 0.085 0.090 0.095 0.100 0.105 0.110 -50 -25 0 25 50 75 100 125 Temperature (°C) VIN Hysteresis Voltage (V) Overload Hiccup Threshold vs Temperature 0.350 0.355 0.360 0.365 0.370 0.375 0.380 0.385 0.390 0.395 0.400 -50 -25 0 25 50 75 100 125 Temperature (°C) Overload Hiccup Threshold (V) VSS1,2 = 3.5V Soft-Start Voltage Threshold (to Enable Overload Hiccup Protection) vs Tem perature 3.0 3.2 3.4 3.6 3.8 4.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Soft-Start Voltage Threshold (to Enable Overload Hiccup Protection) (V) Soft-Start Discharge Current vs Temperature 7.0 7.5 8.0 8.5 9.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Soft-Start Discharge Current ( µA) VFB1=VFB2=0.3V, V SS1=VSS2=3V Soft-Start Voltage (to Restart Overload Shutdown) vs Tem perature 0.50 0.52 0.54 0.56 0.58 0.60 - 5 0 - 2 5 0 2 55 07 5 1 0 0 1 2 5 Temperature (°C) Soft-Start Voltage (to Restart Overload Shutdown) (V) Soft-Start Disable Voltage vs Temperature 0.75 0.77 0.79 0.81 0.83 -50 -25 0 25 50 75 100 125 Temperature (°C) Soft-Start Voltage (to Restart Overload Shutdown) (V) VFB1=VFB2=0.45V, V COMP1=VCOMP2=2V Soft-Start Threshold Voltage (to Eable PWM Operation) vs Tem perature 1.20 1.22 1.24 1.26 1.28 1.30 -50 -25 0 25 50 75 100 125 Temperature (°C) Soft-Start Threshold Voltage (to Eable PWM Operation) (V) VFB1=VFB2=0.03V Current Sense A mplifier Input Bias Current vs Temperature (Inverting Pin) -40 -35 -30 -25 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Sense Amplifier Input Bias Current ( µA) VCC = 8V, V CS1 (-) = VCS2 (-) = 0V

15 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Typical Characteristics Boost Section Feedback Pin Bias Current vs Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Boost Section Feedback Pin Bias Current (nA) Boost Section Amplifier Transconductance vs Tem perature 105 -50 -25 0 25 50 75 100 125 Temperature (°C) Boost Section Amplifier Transconductance ( /g109/g87/g45/g49) Boost Section Amplifier Open Loop Gain vs Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Boost Section Amplifier Open Loop Gain (dB) Boost Section Switch Saturation Voltage vs Tem perature 0.25 0.27 0.29 0.31 0.33 0.35 -50 -25 0 25 50 75 100 125 Temperature (°C) Boost Section Switch Saturation Voltage (V) ISW = 0.6A Boost Section Switch Current Limit vs Tem perature 0.60 0.65 0.70 0.75 0.80 0.85 0.90 -50 -25 0 25 50 75 100 125 Temperature (°C) Boost Section Switch Current Limit (A) Boost Section Feedback Voltage vs Temperature 1.20 1.22 1.24 1.26 1.28 - 5 0 - 2 50 2 55 07 5 1 0 0 1 2 5 Temperature (°C) Boost Section Reference Voltage (V) 1.8V < VIN < 16.5V Bottom Gate Driver Transition Time vs Load Capacitance 100 01 1 0 Load Capacitance (nF) Transition Time (nS) VCC = 12V tr tf 25°C Bottom Gate Driver Transition Time vs Load Capacitance 100 01 1 0 Load Capacitance (nF) Transition Time (nS) VCC = 5V tr tf 25°C

16 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Typical Characteristics Phase Shift vs Temperature 135 180 225 -50 -25 0 25 50 75 100 125 Temperature (°C) Phase (deg) ROSC = 66.5K/g87 R2 = 31.6K/g87 R2 = 41.2K/g87 R2 = 61.9K/g87 R2 = 121K/g87 fSYNC = 300KHz Phase Shift vs Temperature 135 180 225 -50 -25 0 25 50 75 100 125 Temperature (°C) Phase (deg) ROSC = 40.2K/g87 R2 = 36.5K/g87 R2 = 47.5K/g87 R2 = 71.5K/g87 R2 = 143K/g87 fSYNC = 500KHz Phase Shift vs Temperature 135 180 225 - 5 0 - 2 5 0 2 55 07 5 1 0 0 1 2 5 Temperature (°C) Phase (deg) fSYNC = 400KHz R2 = 34.8K/g87 R2 = 46.4K/g87 R2 = 68.1K/g87 R2 = 140K/g87 ROSC = 51.1K/g87 Upper Gate Driver Transition Time vs Load Capacitance 100 01 1 0 Load Capacitance (nF) Transition Time (nS) VCC = 12V tr tf 25°C Upper Gate Driver Transition Time vs Load Capacitance 100 01 1 0 Load Capacitance (nF) Transition Time (nS) VCC = 5V tr tf 25°C Percentage Deviation In Phase Shift vs Temperature -25 -20 -15 -10 -50 -25 0 25 50 75 100 125 Temperature (°C) Phase Deviation (%) ROSC = 40.2K/g87 R2 = 36.5K/g87 R2 = 47.5K/g87 R2 = 71.5K/g87 R2 = 143K/g87fSYNC = 500KHz Percentage Deviation In Phase Shift vs Temperature -60 -50 -40 -30 -20 -10 -50 -25 0 25 50 75 100 125 Temperature (°C) Phase Deviation (%) ROSC = 66.5K/g87 R2 = 31.6K/g87R2 = 41.2K/g87 R2 = 61.9K/g87 R2 = 121K/g87 fSYNC = 300KHz Percentage Deviation In Phase Shift vs Temperature -20 -10 - 5 0 - 2 50 2 55 07 5 1 0 0 1 2 5 Temperature (°C) Phase Deviation (%) fSYNC = 400KHz ROSC = 51.1K/g87 R2 = 34.8K/g87 R2 = 46.4K/g87 R2 = 68.1K/g87 R2 = 140K/g87

17 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Overview The SC2441A is a constant-frequency switching regulator capable of operating from 1.8V to 20V input. It consists of two current-mode step-down switch-mode PWM controllers driving all N-channel MOSFETs and an auxiliary step-up current-mode converter with an integrated 0.6A power switch. A local supply (>5V) can be generated from a low voltage input (3.3V, 2.5V or 1.8V) to provide sufficient gate drives for the step-down converters. The two step-down channels of the SC2441A operate at 180 degrees out of phase from each other. Input currents are interleaved in a two-phase converter so input ripple current is lower and lower input capacitance can be used for filtering. The step-down controllers of the SC2441A operate in synchronous continuous-conduction mode. They can function either as two independent step-down controllers producing two separate outputs or as a dual-phase single- output controller by tying the FB2 pin to V IN (Figure 2). In single output mode, the channel 1 error amplifier controls both channels and the channel 2 error amplifier is disabled. Soft-start and overload hiccup of both channels are also controlled by channel 1. In Figure 2 the output SEL of the comparator A1 determines which error amplifier outputs and fault signals are routed to channel 2. The minimum required FB2 voltage for single output mode is 1.55V. Phase-Locked Loop and Synchronization The SC2441A utilizes a phase-locked oscillator (Figure 5) for clock generation and external synchronization. The advantages of using a phase-locked loop (PLL) are: (i) when the step-down channels are synchronized, the auxiliary step- up regulator in the SC2441A can be made to run at twice the external clock frequency to reduce component size and (ii) two or more SC2441A can be daisy chained using the clock output (pin 28) and interleaved with programmable phase shift. Each step-down controller within a SC2441A operates at 180 degrees out of phase from the other step- down controller. The switching frequency of the step-down controllers can be set with an external resistor ROSC. The boost regulator and the step-down controllers are capable of operating up to 2 MHz and 1 MHz respectively. It is necessary to consider the operating duty-ratio range before deciding the switching frequency. See Applications Information section for more details. Consider the detailed block diagram of the PLL in Figure 5. The phase/frequency detector compares the buffered external clock XCLK with the TQ output of the toggle flip- flop. If the rising edge of XCLK leads that of TQ , then QU will go high between the two corresponding rising edges. Switch S1 is closed, charge is delivered to the loop filter and the voltage at the PLLF pin increases. This in turn causes the current output of the voltage to current converter (V/I) and the switching frequency of the current-controlled oscillator (CCO) to increase. If TQ rises before XCLK, then QD will go high from the rising edge of TQ to the rising edge of XCLK. Switch S 2 is closed, charge is drawn from the loop filter and the PLLF voltage falls. The switching frequency of the current-controlled oscillator (CCO) decreases. When the PLL is in lock, the rising edges of XCLK and TQ are aligned. QU and QD will go high for only a few gate delays. The PLLF stabilizes to a constant DC voltage and the CCO runs at the same frequency as the external clock. In the absence of an external clock, S 2 is closed and the PLL loop filter is continuously discharged. Not shown in Figure 5 is an internal PLLF lower clamp circuit that limits the minimum voltage at the PLLF pin to 0.17V. This sets the lowest operating frequency and thus the lower bound of the PLL lock-range. The V/I in Figure 5 is shown with two non-inverting inputs. The lower voltage non-inverting input takes control of the V/I. If the PLLF pin is tied to VIN (>1.8V) through a current-limiting resistor, then the 0.4V input of the V/I will predominate. The 0.4V input therefore sets the upper excursion limit of the V/I and the maximum operating frequency of the PLL at a given ROSC. The maximum PLL frequency to the minimum locking frequency ratio is about 2. When the SC2441A is not synchronized externally, the PLLF pin should be tied high through a resistor. The CCO will then run at its maximum frequency. When two SC2441As are used in a master-slave configuration, the PLLF pin of the master SC2441A is tied high and its free running frequency is set with the resistor ROSC. CKOUT of the master is then tied to the SHDNSYNC/ input of the slave SC2441A. The free running and the Operation

18 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A minimum locking frequencies of the slave should be selected to accommodate the variation in the master ’s frequency. Phase shift between the master and the slave can be programmed with an optional resistor (Figure 5). More detailed discussion can be found in the Application Information. Pulling the SHDNSYNC/ pin below 0.5V shuts off the SC2441A after 85µs time delay. Control Loop The step-down controllers and the boost regulator in the SC2441A use peak current-mode control for fast transient response and current sharing in single output operation. Current-mode switching regulators utilize a dual-loop feedback control system. The error amplifier output controls the peak inductor current of that channel. This is the inner current loop. The double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop, easing loop compensation. Fast transient response can be obtained with a simple Type-2 compensation network. In the outer loop, the error amplifier regulates the output voltage. Referring to the block diagrams in Figures 2 and 3, the sensed inductor current is summed with the slope- compensating ramp before compared to the output of the error amplifier. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed current exceeds the corresponding current-limit threshold. ILIM therefore provides cycle-by-cycle current limit. All three converters in the SC2441A have internal ramp- compensation to prevent sub-harmonic oscillation when operating above 50% duty cycle. The internal compensating ramp is designed for an inductor ripple-current between 1 and of the maximum inductor current and the peak- to-peak current-sense voltage (CSP-CSN of the step-down controllers) between and of the current-limit threshold (25mV). The current-limits of all three converters are unaffected by the compensation ramps. Current-Sensing The inductor current needs to be sensed for use as PWM modulating ramp. Either sense resistor or inductor series resistance (DCR) can be used as the sensing element for the step-down controllers. Since the maximum current- sense voltage (CSP-CSN) is only 25mV, a precision sense resistor in series with the inductor can be used at the output without resulting in excessive power dissipation. Alternatively the DCR of the inductor can also be used. Both methods are less sensitive to supply and ground transients than high-side or low-side sensing because the sensed voltage is developed at the output of the step- down converter. DCR sensing will be described in more details in the Applications Information section. Boost switch current is sensed with an integrated sense resistor with a minimum current-limit of 0.6A. Error Amplifiers All error amplifiers in the SC2441A are of transconductance type. Converters are compensated with series RC network from the COMP pins to the ground. An additional small parallel capacitor may be required for stability. In Figure 2 the error amplifiers EA1 and EA2 are shown with two non-inverting inputs. The non-inverting input with lower voltage predominates. One positive input is biased to a 0.5V precision reference. The other non-inverting input of the error amplifier is tied to a voltage equal to SS/EN - 1.25V)/3. During converter start up, the effective positive input of the error amplifier stays at 0 until the soft-start capacitor at the SS/EN pin is charged above 1.25V. The corresponding COMP pin is also pulled low by the comparator A 2 or A 3. After the SS/EN voltage exceeds 1.25V, the COMP pin is released. Both the upper and the lower gate drives remain low until the COMP voltage exceeds 1.85V. If the soft-start capacitor charging time is sufficiently long, then both the FB and the output voltage will track the divided SS/EN voltage on their way to regulation. If the starting output voltage is non-zero, then the COMP voltage and the corresponding gate drives will remain low until the divided SS/EN voltage exceeds the feedback voltage. Starting into a pre-existing output is seamless. Operation (Cont.)

19 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Operation (Cont.) In closed loop operation, EA1 and EA2 output voltage vary from 1.2V to 3.5V with the range 1.2V to 1.85V corresponding to negative peak sense voltages. Both gate drives are kept off until the COMP voltage exceeds 1.85V in start up. The error amplifier of the step-up converter has a 1.25V reference voltage. Its output voltage excursion is from 0.8V to 1V in closed-loop operation. Current-Limit The 25mV maximum current sense voltage is the cycle-by- cycle peak current limit of the step-down controller. Gate Drivers The SC2441A uses an adaptive non-overlapping control scheme to switch the upper and the synchronous MOSFETs. The synchronous MOSFET of each step-down channel is turned off at the falling-edge of the phase clock. The control (upper) MOSFET is not turned on until the synchronous gate drive goes low. The phase inductor current ramps up. When the sensed inductor current reaches the threshold determined by the error amplifier output and ramp compensation, the control MOSFET is turned off. The synchronous MOSFET is not turned on until the upper gate drive goes low. The supply voltage for the upper gate driver is obtained from a diode-capacitor bootstrap circuit. If the bootstrap capacitor is charged from V CC, then the high-side gate drive voltage will swing from approximately 2VCC to ground. The synchronous gate drive swings from VCC to ground. Soft-Start and Overload Protection Figure 4 shows the functional diagram of the soft-start and overload protection circuit. The soft-start capacitor C SS and its charging resistor RSS are tied to the SS/EN pin. Together they set the soft-start time. Before V CC rises to 4.5V, the undervoltage lockout circuit discharges C SS to ground. After VCC rises above 4.5V, Q1 turns off and C SS is slowly charged by R SS. Comparator C 2 and latch L 2 first disable both the upper and lower gate drives. Hysteretic comparator C 1 resets the latch L1 so that hiccup is disabled during start up. As mentioned above, there is no PWM (=TGON) pulse until C SS is above 1.25V and the corresponding COMP rises above 1.85V. Once the first TGON pulse appears, L 2 is reset and both gate drivers of that channel are enabled. After C SS is charged above 3.3V, C 1 output goes low. Hiccup is armed. If the output voltage is less than 70% of the set value due to improper start up or output overload, then C 3 will set the overload latch L1. Both gate drivers of the channel are turned off and the 10 µA current source discharges CSS. RSS must be large enough to ensure full discharge of C SS down to 0.5V. Soft-start process should be slow enough to allow the output to reach 70% of its final value before hiccup is armed. The overload latch L 1 is reset when the C SS capacitor is discharged below 0.5V. The 10 µA current source turns off. CSS capacitor is recharged by R SS and the converter undergoes soft-start. If overload persists, the step-down converters will undergo repetitive shutdown and restart (hiccup). If the output is short-circuited, the inductor current will not increase indefinitely between the times the inductor current reaching its current limit and shutdown. This is due to cycle skipping reduces the actual operating frequency. Pulling the SS/EN pin below 0.8V with an open-collector transistor sets the disable latch L 2 and turns off the gate drives. The SS/EN pin can be used as the enable input for the controller. The soft start timing diagram and the hiccup operation timing diagram are shown in Figures 6a and 6b respectively.

the following trade-offs should be considered. ROSC is in KΩ and FSW is in KHz. the boost section will be running at 500KHz. Figure 7. ROSC vs. Step-down Channel Free-running the top MOSFET at all or turns it on for at least 180ns.

frequency is 1MHz, the lowest output voltage will be 0.6V. to allow modulating headroom. Figure 8. RC Network Connections for V IN and V CC pins threshold is typically 0.8A. gate drive of the step-down controllers.

start-up is shown as in Figure 14. Figure 14. Test Setup for Pre-biased Start Up run or it can be phase-locked to an external clock. output of the boost converter reaches the setpoint. switch if the PLLF pin is at zero volt. clock for other SC2441As in a master-slave configuration.

SC2441A is the input sync signal for the slave SC2441A. the slave CKOUT and its SYNC input. ringing at PLLF pin is minimized. change the inductor current during load transients. but with attendant higher core losses. the synchronizing range of the slave. on the PLLF pin are necessary for the slave SC2441A . the “Typical Characteristics”. Figure 15. Master-Slave Synchronization

the rated DC output current. Figure 16. C o equivalent circuit and Co on the output voltage. The first term is the DC voltage across C o at time t=0. sum of the last three terms. rating is normally suggested to be greater than 1.5 Vo.

Figure 19. Typical waveforms at the input of a inductances around the pulse current loop. increase the ripple current handling capability. inductors speeds up output load transient. RMS value of the ripple current in the input capacitor. 1, D2 and I o1, Io2 respectively.

c) the gate loss due to the gate resistance R G. Rds(on) varies with temperature and gate-source voltage. junction temperature increases from 25°C to 125°C. inductive mode in Figure 21. Figure 21. MOSFET switching characteristics FOM follow the same curve in Figure 20.

201 Rds

Figure 20. Figure of merit curves. The closer the curve is to the origin, the lower is the FOM. MOSFET’s with low Rds(on) are used for the bottom switch.

31 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Applications Information In Figure 21, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold V gs_th, Qgs2 is the additional gate charge required for the switch current to reach its full-scale value I ds.and Qgd is the charge needed to charge gate-to-drain (Miller) capacitance when V ds is falling. Switching losses occur during the time interval [t 1, t 3]. Defining tr = t3-t1. tr can be approximated as .VV R)QQ(t gspcc gtgd2gs r /g45 /g43/g61 where R gt is the total resistance from the driver supply rail to the gate of the MOSFET. It includes the gate driver internal impedance R gi, external resistance R ge and the gate resistance R g within the MOSFET i.e. Rgt = Rgi+Rge+Rg. Vgsp is the Miller plateau voltage shown in Figure 21. Similarly an approximate expression for t f is gsp gtgdgs2 f V )RQ(Qt /g43/g61 Only a portion of the total losses P g = QgVccfs is dissipated in the MOSFET package. Here Qg is the total gate charge specified in the datasheet. The power dissipated within the MOSFET package is .fVQR RP sccg gt g tg /g61 The total power loss of the top switch is then P t = Ptc+Pts+Ptg. If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction loss is inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. Bottom Switch: The RMS current in bottom switch can be calculated .)1)(D1(II 12orms,2Q 2/g100/g43/g45/g61 The conduction loss is then Pbc=IQ2,rms

2 Rds(on),

where Rds(on) is the channel resistance of bottom MOSFET. If the input voltage to output voltage ratio is high (e.g. V in=12V, Vo=1.5V), the duty ratio D will be small. Since the bottom switch conducts with duty ratio (1-D), the corresponding conduction losses can be quite high. Due to non-overlapping conduction between the top and the bottom MOSFET’s, the internal body diode or the external Schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. The switching loss sdo2fr2 bs fVI)1)(tt(P /g100/g43/g43/g61 is negligible due to near zero-voltage switching. The gate loss is estimated as .fVQR RP sccg gt g bg /g61 The total bottom switch loss is then P b=Pbc+Pbs+Pbg. Once the power losses P loss for the top (P t) and bottom (Pb) MOSFET’s are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature (Tj,max, usually 125oC) is not exceeded under the worst-case conditions. The equivalent thermal impedance from junction to ambient (θ ja) should satisfy TT loss max,amax,j ja /g45/g163/g113 θja depends on the die to substrate bonding, packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area and the air flow condition (free or forced convection). Actual temperature measurement of the prototype should be carried out to verify the thermal design. Integrated Power MOSFET Drivers There are four internal MOSFET drivers in a dual- channel step-down converter.

32 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Once either R o1 or R o2 is chosen, the other can be calculated for the desired output voltage V o. Since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the converter output voltage. This non-random error is The following table lists a few standard resistor combinations for realizing some commonly used output voltages. )mhO(1oR 002 608 K4.1K 2 K16.2K 20.4K 26.5 )mhO(2oR K1 K1 K1K 1 K1K 1K 1 Only the voltages in boldface can be precisely set with standard 1% resistors. The input bias current of the error amplifier also causes an error in the output voltage. The inverting input bias currents of error amplifiers 1 and 2 are –60nA and –280nA respectively. Since the non-inverting input is biased to 0.5V, the percentage error in the second output voltage will be –100% · (0.28 µA) · R o1Ro2 /[0.5 · (Ro1+Ro2)]. To keep this error below 0.2%, R o2 < 4kΩ . Loop Compensation in Step-down Section The SC2441A uses current-mode control for both step- down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This pole-splitting property of current- mode control greatly simplifies loop compensation. Applications Information Using low gate charge MOSFETs reduces switching loss. It is possible to trade driver IC losses for MOSFET switching losses by adjusting the gate resistance. Lower gate resistance results in higher gate driving current and faster MOSFET switching. However the driver incurs higher losses. Conversely higher gate drive resistance limits the gate drive current, thus lowering the driver dissipation. MOSFET switching loss is higher. To prevent shoot-through between the top and the bottom MOSFETs during commutation, one MOSFET should be completely turned off before the other is turned on. The SC2441A uses adaptive non-overlapping timing to prevent shoot-through. Optimize MOSFET Driving Voltage The on-state DC resistance of a MOSFET, R DS_ON , is determined by its gate to source voltage. The higher the V GS, the lower the R DS_ON will be. Once the gate-source voltage exceeds a certain level, the R DS_ON becomes relatively constant. There is no benefit except higher dissipation if you further increase the MOSFET gate drive voltage. It is recommended to select gate drive voltage CC pin) of the SC2441A in between 5V to 7V. Setting the Output Voltage of the Step-down Section The non-inverting inputs of the error amplifiers are internally biased to 0.5V voltage reference. A simple voltage divider (R o1 at top and R o2 at bottom) sets the converter output voltage. R o2 can be expressed as a function of the voltage feedback gain h=0.5/V o and R o1 .1o2o Rh1 hR /g45/g61 caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop.

34 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A P2 is a pole for suppressing high-frequency switching noise. So P2 >> Z2. To simplify design, one usually assumes that C 3<<C2, R oesr<<Ro, S p1=Sz2 and specifies the loop crossover frequency f c. The loop crossover frequency determines the converter dynamic response. With these assumptions, the controller parameters are determined as follows ,f2 hkRgC c om /g112/g61 oo C CRR /g61 and CRC ooesr 3 /g61 For example, if V in=3.3V, V o=1.2V, I o=4A, f s=500kHz, Co=390µF, Roesr=16mΩ , one can calculate that ,m300I VR o o o /g87/g61/g61 42.0V 5.0h o /g61/g61 and .60.2V Ik c o /g61/g68 /g68/g61 If the converter crossover frequency is set around 1/10 of the switching frequency, f c=50kHz, the controller parameters then can be calculated. ,nF326.0f2 hkRgC c om 2 /g187/g112/g61 use C 2=0.33nF. ,k5.354C CRR oo 2 /g87/g187/g61 use R 2=357kΩ . It is further calculated that ,pF48.17R CRC ooesr 3 /g187/g61 use C3=22pF. The Bode plots of the loop transfer function (magnitude and phase) are shown in Fig. 25. Applications Information function from the voltage error amplifier output v c to the converter output v o can be derived from Figure 24. s s kR)s(G:)s(V )s(V ovc c o /g43 /g43 /g61/g61 where the single dominant-pole is ooesro C)RR( 1s /g43/g61 and the zero associated with the output capacitor ESR is .CR ooesr 1z /g61 The dominant-pole changes with the converter output load. The controller transfer function (from the converter output v o to the voltage error amplifier output vc) is s s )CC(s hg)s(C m /g43 /g43 /g43/g61 where CR 1s /g61 and CC CCR /g43 /g61 The loop transfer function is then T(s)=Gvc(s)C(s).

Figure 25. Bode plots of the loop response. output voltage is within the specification window. operation of high frequency switching power converters. bounces. The followings are suggested for proper layout. output capacitor (output return terminal). ground to improve high frequency bypass. ring with the gate capacitance. supplies (BST and VCC) close to the IC and power ground.

36 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Applications Information Control Section 6) The frequency-setting resistor Rosc should be placed close to Pin 10. Trace length from this resistor to the analog ground should be minimized. 7) Solder the VCC decoupling capacitor next to the VCC and power ground PGND pins. 8) Place the current-sensing components away from the power circuit and close to the corresponding CS+ and CS- pins. Use X7R type ceramic capacitors for current sensing due to their thermal stability. The distance between the two trace should be as close as possible to minize the noise pick-up. 9) Use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank. 10) A large copper area underneath the SC2441A IC is nessary for heat sinking purpose. And multiple layers of large copper area connected through vias can be used for better thermal performance. The size of the vias as the connection between multiple layers should not be too large or solder may seep through the big vias to the the bottom layer during the re-flow process.

37 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2441A Outline Drawing - TSSOP-28 Semtech Corporation Power Management Products Division

200 Flynn Road, Camarillo, CA 93012-8790

Phone: (805)498-2111 FAX (805)498-3804 Contact Information Land Pattern - TSSOP-28 N AA2 A1bxN PLANE bbb C A-B D ccc C DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS3. OR GATE BURRS. DATUMS AND TO BE DETERMINED AT DATUM PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). -B- NOTES: 2. -A- -H- SIDE VIEW A B C De H e/2 (.039) .008 .004 .024 .018 .003 E INCHES b N bbb aaa ccc E L e D c DIM A MIN MAX MILLIMETERS DIMENSIONS MINMAXNOM NOM BOTTOM VIEW EXPOSED PAD F H .031 .000 8° 0° 0.20 0.10 - 8° 0.45 0.09 0.80 0.00 .030 .008 .047 .041 .006 0.60 (1.0) 0.75 0.20 - 1.20 1.05 0.15 D REFERENCE JEDEC STD MO-153, VARIATION AET.4. L (L1) c GAGE PLANE SEE DETAIL DETAIL A A 0.25 .026 BSC .252 BSC .004 .169 .173 .007 - 0.10

0.65 BSC

6.40 BSC

4.40 .177 4.30 .012 0.19 4.50 0.30 .382 2X N/2 TIPS SEATING aaa C E/2 INDICATOR PIN 1 213 (.222) (5.65) ZG Y P (C) 4.10.161 0.65.026 0.40.016 1.55.061 7.20.283 X THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: F H INCHES DIMENSIONS Z P Y X DIM C G MILLIMETERS F 5.70 .224 H 3.20 .126