SC202A

SC202AMLTRT SEMTECH | Alldatasheet

Document overview

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Technical content

Features

Input Voltage — 2.9V to 5.5V Output Voltage — 0.8V to 3.3V Output current capability — 500mA Internal inductor Programmable output voltages — 15 High light-load efficiency via automatic PSAVE mode Fast transient response Temperature range — -40 to +85°C Oscillator frequency — 3.5MHz 100% duty cycle capability Quiescent current — 38µA typical Shutdown current — 0.1µA typical Internal soft-start Over-voltage protection Current limit and short circuit protection Over-temperature protection Under-voltage lockout Floating control pin protection MLPQ-13 — 2.5 x 3.0 x 1.0 (mm) package Lead-free and halogen-free WEEE and RoHS compliant

Applications

Smart phones and cellular phones MP3/personal media players Personal navigation devices Digital cameras Single Li-ion cell or 3 NiMH/NiCd cell devices Devices with 3.3V or 5V internal power rails

Description

The SC202A is a high efficiency 500mA step-down regula- tor that includes an integrated inductor inside the package. The input voltage range makes it ideal for battery operated applications with space limitations. The SC202A also includes 15 programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. The output voltage can be fixed to a single setting or dynami- cally switched between different levels. Pulling all four control pins low disables the output. The SC202A operates at a fixed 3.5MHz switching fre - quency in normal PWM (Pulse-Width Modulation) mode. A variable frequency PSAVE (power-save) mode is used to optimize efficiency at light loads for each output setting. Built-in hysteresis prevents chattering between the two modes. The SC202A provides several protection features. These include short circuit protection, over-temperature protec- tion, under-voltage lockout, and soft-start to control in-rush current. These features, coupled with the small 2.5 x 3.0 x 1.0 (mm) package, make the SC202A a versatile device ideal for step-down regulation in products needing high efficiency and a small PCB footprint. SC202A IN CTL3 CTL2 CTL1 CTL0 SNS OUT GND VOUT 0.8V to 3.3V VIN 2.9V to 5.5V COUT 10µF CIN 4.7µF Control Logic Lines LX NC Typical Application Circuit Rev. 1.2

Ordering Information

SC202AMLTRT(1)(2) MLPQ-13 — 2.5 x 3.0 SC202AEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. TOP VIEW 7 8 13LX LX LX OUT OUT OUT GND IN CTL2CTL1 CTL0 CTL3 SNS MLPQ-13; 2.5 x 3.0, 13 LEAD θJA = 58°C/W Table 1 – Output Voltage Settings CTL3 CTL2 CTL1 CTL0 Vout 0 0 0 0 Shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0 1 1 0 1.60 0 1 1 1 1.80 1 0 0 0 1.85 1 0 0 1 1.90 1 0 1 0 2.00 1 0 1 1 2.20 1 1 0 0 2.50 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 yyww = Date Code xxxx = Semtech Lot Number 202A yyww xxxx

Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards. Absolute Maximum Ratings Recommended Operating Conditions Thermal Information Unless otherwise specified: VIN= 3.6V, CIN= 4.7µF, COUT=10µF, VOUT=1.8V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C Parameter Symbol Condition Min Typ Max Units Output Voltage Range VOUT 0.8 3.3 (1) V Output Voltage Tolerance VOUT_TOL IOUT = 200mA -2.0 2.0 PSAVE mode 1.5 Line Regulation ΔVLINEREG 2.9 ≤ VIN ≤ 5.5V, IOUT = 200mA 0.3 %/V Load Regulation ΔVLOADREG 200mA ≤ IOUT ≤ 500mA -1 %/A Output Current Capability IOUT 500 mA Current Limit Threshold ILIMIT 800 1300 mA Foldback Current Limit IFB_LIM ILOAD > ILIMIT 150 mA Under-Voltage Lockout VUVLO Rising VIN 2.9 V Hysteresis 200 mV Quiescent Current IQ No switching, IOUT = 0mA 38 60 µA Shutdown Current ISD VCTL 0-3= 0V 0.1 1.0 µA Output Leakage Current IOUT Into OUT pin 0.1 1.0 µA High Side Switch Resistance(2) RDSON_P IOUT= 100mA 250 mΩ Low Side Switch Resistance(3) RDSON_N IOUT= 100mA 350

Electrical Characteristics

Parameter Symbol Condition Min Typ Max Units Switching Frequency fSW 2.8 3.5 4.2 MHz Soft-Start tSS VOUT = 90% of final value 100 500 µs Thermal Shutdown TOT Rising temperature 160 °C Thermal Shutdown Hysteresis THYST 20 °C Logic Inputs - CTL0, CTL1, CTL2, and CTL3 Input High Voltage VIH 1.2 V Input Low Voltage VIL 0.4 V Input High Current IIH VCTL 0-3= VIN -2.0 5.0 µA Input Low Current IIL VCTL 0-3= GND -2.0 2.0 µA Notes (1) Maximum output voltage is limited to VIN if the input is less than 3.3V. (2) Measured from IN to LX (3) Measured from LX to GND Electrical Characteristics (continued)

Efficiency vs. IOUT (TA = -40°C) Load Current (mA) Efficiency (%) VOUT = 1V, 1.8V, 2.8V, and 3.3V 100 0.1 1 10 100 1000 3.3V 2.8V 1.8V Efficiency vs. IOUT (TA = 25°C) Load Current (mA) Efficiency (%) VOUT = 1V, 1.8V, 2.8V, and 3.3V 100 0.1 1 10 100 1000 3.3V 2.8V 1.8V Efficiency vs. IOUT (TA = 85°C) Load Current (mA) Efficiency (%) VOUT = 1V, 1.8V, 2.8V, and 3.3V 100 0.1 1 10 100 1000 3.3V 2.8V 1.8V VOUT (V) Efficiency (%) 4.2V 5.0V 100 3.6V IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V Efficiency (%) 4.2V 5.0V 100 VOUT (V) 3.6V IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V VOUT (V) Efficiency (%) 4.2V 100 5.0V 3.6V IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V Efficiency vs. VOUT (TA = -40°C) Efficiency vs. VOUT (TA = 25°C) Efficiency vs. VOUT (TA = 85°C)

Frequency vs. Temperature Temperature (°C) Frequency (MHz) 1.0V 3.3V 3.1 3.2 3.3 3.4 3.5 3.6 -40 -20 0 20 40 60 80 100 2.8V 1.8V VOUT = 1V, 1.8V, 2.8V, and 3.3V Load Regulation (VOUT = 1.8V) Load Current (mA) Output Voltage (V) 1.77 1.78 1.79 1.80 1.81 1.82 1.83 0 100 200 300 400 500 25°C 85°C -40°C -40°C VIN (V) VOUT (V) IOUT = 200mA 25°C 85°C 1.77 1.78 1.79 1.80 1.81 1.82 1.83 Line Regulation (VOUT =1.8V) VIN (V) Efficiency (%) IOUT = 200mA -40°C 25°C 85°C Efficiency vs. VIN (VOUT =1.8V) Typical Characteristics (continued)

Typical Characteristics (continued) Light Load Switching — VOUT = 1.8V Time (400nsdiv)sdiv)div) VLX (5V/div) VOUT (50mV/div) ILX (200mA/div) Light Load Switching — VOUT = 1.0V Time (400nsdiv)sdiv)div) VLX (5V/div) VOUT (50mV/div) ILX (200mA/div) Light Load Switching — VOUT = 2.8V Time (400nsdiv)sdiv)div) VLX (5V/div) VOUT (50mV/div) ILX (200mA/div) Light Load Switching — VOUT = 3.3V Time (400nsdiv)sdiv)div) VLX (5V/div) VOUT (50mV/div) ILX (200mA/div) Heavy Load Switching — VOUT = 1.0V Time (200nsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VLX (5V/div) Heavy Load Switching — VOUT = 1.8V Time (200nsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VLX (5V/div)

Typical Characteristics (continued) Heavy Load Switching — VOUT = 2.8V Time (200nsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VLX (5V/div) Heavy Load Switching — VOUT = 3.3V Time (200nsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VLX (5V/div) Heavy Load Soft-start Time (40μsdiv)sdiv)div) VOUT (1.0V/div) IIN (200mA/div) ILX (500mA/div) Light Load Soft-start Time (40μsdiv)sdiv)div) Vout (1.0V/div) IIN (200mA/div) ILX (500mA/div) Load Transient Response — 25 to 90mA Time (20μsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) ILOAD (50mA/div) Load Transient Response — 25 to 500mA Time (20μsdiv)sdiv)div) ILX (500mA/div) VOUT (100mV/div) ILOAD (500mA/div) ILOAD = 10mAILOAD = 500mA

Typical Characteristics (continued) Load Transient Response — 200 to 500mA Time (20μsdiv)sdiv)div) ILX (500mA/div) VOUT (100mV/div) ILOAD (500mA/div) Line Transient Response — PWM Time (400μsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VIN (500mV/div) VID Transient Response — PWM Time (20μsdiv)sdiv)div) VCTL2 (2V/div) VOUT (500mV/div) ILX (500mA/div) 1.2V to 1.8V transition VID Transient Response — PSAVE Time (20μsdiv)sdiv)div) VCTL2 (2V/div) VOUT (500mV/div) ILX (500mA/div) 1.2V to 1.8V transition Line Transient Response — PSAVE Time (400μsdiv)sdiv)div) ILX (200mA/div) VOUT (50mV/div) VIN (500mV/div) Shutdown Transient Response Time (20μsdiv)sdiv)div) ILX (500mA/div) VOUT (2V/div) VCTL3-0 (2V/div) 4.0V to 3.5V using Li-Ion battery 4.0V to 3.5V using Li-Ion battery

1, 2, 3 LX Switching node sense pin — for test purposes only 4 SNS Output sense pin — connect to output capacitor for proper sensing of output voltage. 5 CTL3 Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL3 is pulled above the logic high threshold. 6 CTL0 Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL0 is pulled above the logic high threshold. 7 CTL1 Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL1 is pulled above the logic high threshold. 8 CTL2 Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL2 is pulled above the logic high threshold. 9 IN Input power supply pin — connect a bypass capacitor from this pin to GND.

10 GND Ground reference and power ground for the SC202A

11, 12, 13 OUT Regulator output pin — connect a 10µF ceramic capacitor to this pin for proper filtering.

OSC & Slope Generator PWM Comp Error Amp 500mV Ref CTL2 CTL1 CTL0 SNS CTL3 GND OUT IN Voltage Select B PSAVE Comp A = pins 1, 2, 3 B = pins 11, 12, 13 LXA 1µH

The SC202A is a synchronous step-down PWM (Pulse Width Modulated) DC-DC regulator utilizing a 3.5MHz fixed-frequency voltage-mode architecture and an inter - nal 1 µH inductor. The device is designed to operate in fixed-frequency PWM mode and enter PSAVE (power save) mode utilizing pulse frequency modulation under light load conditions for maximizing efficiency. Two capacitors are the only external components required — one for input decoupling and one for output filtering. The output voltage is programmable, eliminating the need for exter - nal programming resistors. Loop compensation is also internal, eliminating the need for external components to control stability. Programmable Output Voltage The SC202A has 15 fixed output voltage levels which can be individually selected by programming the CTL control pins (CTL3-0 — see Table 1 on page 2 for settings). The device is disabled whenever all four CTL pins are pulled low and enabled whenever at least one of the CTL pins is pulled high. This configuration eliminates the need for a dedicated enable pin. Each CTL pin is internally pulled down via 1MΩ if VIN is below 1.5V or if the voltage on the control pin is below the input high voltage. This ensures that the output is disabled when power is applied if there are no inputs to the CTL pins. Each weak pull-down is dis- abled whenever its pin is pulled high and remains disabled until all CTL pins are pulled low. The output voltage can be set using different methods. If a static output voltage is required, the CTL pins can be tied to either IN or GND to set the desired voltage when - ever power is applied at IN. If enable control is required, each CTL pin can be tied to either GND or to a micropro - cessor I/O line to create the desired control code whenever the control signal is forced high. This method is equivalent to using the CTL pins collectively as a single enable pin. A third option is to connect each of the four CTL pins to individual microprocessor I/O lines. Any of the 15 output voltages can be programmed using this method. If only two output voltages are needed, the CTL pins can be com- bined in a way that will reduce the number of I/O lines to 1, 2, or 3, depending on the control code for each desired voltage. Dynamic Output Voltage Adjustment Dynamically changing the CTL pins allows dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. This should done using specific procedures. Attention needs to be made so that applying all zeros in a very short period to the CTL pins when changing the output voltage will temporarily disable the device. Therefore it is important to avoid these combinations of all zero when dynamically chang- ing the CTL levels. For example, when the CTLs change from 0001 to 0010 (0.8V to 1.2V), a transitional state of 0000 (shut down) state might occur in a very short period of time, which could result the device to be disabled unintentionally. In order to achieve such operation, the correct logic transition stages should be 001000110001 (1V1.2V0.8V). The 0011 (1.2V) state should be kept short to prevent from the 0000 state. If the output voltage level is not within the specified the CTL voltage levels, the resistor divider ratio can be switched by a logic voltage level through an external MOSFET to achieve the dynamic output voltage transition. Secondly, when the CTL pin is toggled for the output voltage to increase, the regulator will increase the induc- tor current and force the output voltage follow. When the CTL pin is toggled for the output voltage to decrease, the regulator will force the output voltage go down immediately (at heavy load conditions) when the device is in CCM. If the device is in DCM operation (the inductor current does not go negative) then the output voltage will go down as the load current drains the output capacitor. Adjustable Output Voltage Selection If an output voltage other than one of the 15 program - mable settings is needed, an external resistor divider network can be added to the SC202A to adjust the output voltage setting. This network scales the output based on the resistor ratio and the programmed output setting. Applications Information

setting, optimizing efficiency for all possible load currents in PWM or PSAVE mode. While in PSAVE mode, output voltage regulation is controlled by a series of switching bursts. During a burst, the inductor current is limited to a peak value which controls the on-time of the PMOS switch. After reaching this peak, the PMOS switch is disabled and the inductor current decreases to near 0mA. Switching bursts continue until the output voltage climbs to V OUT +2.5% or until the PSAVE current limit is reached. Switching is then stopped to eliminate switching losses, enhancing overall efficiency. Switching resumes when the output voltage reaches the lower threshold of VOUT and continues until the upper threshold again is reached. Note that the output voltage is regulated hysteretically while in PSAVE mode between VOUT and VOUT + 2.5%. The period and duty cycle while in PSAVE mode are solely determined by V IN and VOUT until PWM mode resumes. This can result in the switching frequency being much lower than the PWM mode frequency. If the output load current increases enough to cause V OUT to decrease below the PSAVE exit threshold (VOUT -2%), the device automatically exits PSAVE and operates in continu- ous PWM mode. Note that the PSAVE high and low threshold levels are both set at or above VOUT to minimize undershoot when the SC202A exits PSAVE. Figure 2 illus- trates the transitions from PWM mode to PSAVE mode and back to PWM mode. VOUT -2% VOUT VOUT +2.5% Load Demand (IOUT) BURST OFF VLX Time PWM Mode at Medium/High Load PSAVE Mode at Light Load PWM Mode at Medium/High Load PSAVE EXIT Figure 2 — Transitions Between PWM and PSAVE Modes Applications Information (continued) Protection Features The SC202A provides the following protection features: Soft-Start Operation Over-Voltage Protection Current Limit Thermal Shutdown Under-Voltage Lockout Soft-Start The soft-start sequence is activated after a transition from an all zeros CTL code to a non-zero CTL code enables the device. At start-up, the PMOS current limit is stepped through four levels: 25%, 40%, 60%, and 100%. Each step is maintained for 60μs following an internal reference start up of 20μs, resulting in a total nominal start-up period of 260μs. If VOUT reaches 90% of the target within the first 2 steps, the device continues in PSAVE mode at the end of soft-start; otherwise, it goes into PWM mode. Note the VOUT ripple in PSAVE mode can be larger than the ripple in PWM mode. Over-Voltage Protection Over-voltage protection ensures the output voltage does not rise to a level that could damage its load. When V OUT exceeds the regulation voltage by 15%, the PWM drive is disabled. Switching does not resume until VOUT has fallen below the regulation voltage by 2%. Current Limit The SC202A switching stage is protected by a current limit function. If the output load exceeds the PMOS current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150mA. Under these conditions, the output voltage will be the product of IFB-LIM and the load resistance. The load must fall below IFB-LIM for the device to exit fold-back current limit mode. This function makes the device capable of sustaining an indefinite short circuit on its output under fault conditions. Thermal Shutdown The SC202A has a thermal shutdown feature to protect the device if the junction temperature exceeds 160°C. During thermal shutdown, the PMOS and NMOS switches are both disabled, tri-stating the LX output. When the junction temperature drops by the hysteresis value (20°C),

the device goes through the soft-start process and resumes normal operation. Under-Voltage Lockout UVLO (Under-Voltage Lockout) activates when the supply voltage drops below the falling UVLO threshold. This pre- vents the device from entering an ambiguous state in which regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the threshold. COUT Selection The internal voltage loop compensation in the SC202A limits the minimum output capacitor value to 10μF. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. Increasing the output capacitor above this minimum value will reduce the cross- over frequency and provide greater phase margin. Capacitors with X7R or X5R ceramic dielectric are recom - mended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. In addition to ensuring stability, the output capacitor serves other important functions. This capacitor deter - mines the output voltage ripple — as capacitance increases, ripple voltage decreases. It also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Once the loop responds, regulation is restored and the desired output is reached. During the period prior to PWM operation resuming, the relationship between output voltage and output capacitance can be approximated using the following equation. fV I3C DROOP LOAD OUT u This equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. For example, a load step from 50mA to 400mA requiring droop less than 50mV would require the minimum output capacitance as shown by the following equation. Applications Information (continued) Manufacturer/Part No. L (μH) DCR Max (Ω) Rated Current (A) L at Rated Current (μH) Dimensions LxWxH (mm) Murata Murata Coilcraft Coilcraft shielded FDK FDK Tayo Yuden F0.6105.305.0 4.03C 6OUT P uu u In this example, using a standard 10µF capacitor would be adequate to keep voltage droop less than the desired limit. Note that if the voltage droop limit were decreased from 50mV to 25mV, the output capacitance would need to be increased to at least 12µF (twice as much capaci - tance for half the droop). Capacitance will decrease from the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the pro- grammed output voltage. Check the manufacturer’s capacitance vs. DC voltage graphs when selecting an output capacitor to ensure the capacitance will be adequate. Table 2 lists the manufacturers of recommended output capacitor options. Table 2 — Recommended Output Capacitors Manufacturer Part Nunber Value (μF) Type Rated Voltage (VDC) Dimensions LxWxH (mm) Case Size Murata GRM188R60J106ME47D 10±20% X5R 6.3 1.6x0.8x0.8 0603 Murata GRM21BR60J106K 10±10% X5R 6.3 2.0x1.25x1.25 0805 Taiyo Yuden JMK107BJ106MA-T 10±20% X5R 6.3 1.6x0.8x0.8 0603 TDK C1608X5R0J106MT 10±20% X5R 6.3 1.6x0.8x0.8 0603 CIN Selection The SC202A input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coeffi- cient characteristics when determining the actual required value. For example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5μF . The value of required input capacitance is estimated by determining the acceptable input ripple voltage and

Applications Information (continued) calculating the minimum value required for CIN using the following equation. fESRI V V V1V V C OUT IN OUT IN OUT IN § ' The input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capaci- tor should be placed as close as possible to the IN and GND pins. Table 3 lists recommended input capacitor options from different manufacturers. Table 3 — Recommended Input Capacitors Manufacturer Part Nunber Value (μF) Type Rated Voltage (VDC) Dimensions LxWxH (mm) Case Size Murata 0603 Murata GRM188R60J106K 10±10% X5R 6.3 1.6x0.8x0.8 0603 Taiyo Yuden 0603 TDK 0603 PCB Layout Considerations The layout diagram in Figure 3 shows a recommended PCB top-layer for the SC202A and supporting compo - nents. Specified layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can also result. The following guidelines are recommended for designing a PCB layout: CIN should be placed as close to the IN and GND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to minimize trace impedance. This will also minimize EMI and input voltage ripple by localizing the high frequency current pulses. COUT should be connected as closely as possible to the OUT pin. Use a ground plane referenced to the GND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. Route the output voltage feedback/sense trace (connected to the SNS pin) away from the LX node as shown in Figure 3 to minimize noise and magnetic interference. Minimize the resistance from the OUT and GND pins to the load. This will reduce errors in DC regulation due to voltage drops in the traces. The two smaller exposed pads on this package should not be connected to any traces. The area beneath these two pads must be kept clear so that they do not make electrical contact with any traces, including ground. CIN CTL2 CTL0 CTL1 CTL3 LX (no connection needed) SNSGND IN OUT 3.8mm 3.5mm SC202A These pads should not be electrically connected to the PCB. COUT Figure 3 — Recommended PCB Layout

2.502.40 2.60 NOTES: 0.08 0.60 0.00 0.80 0.750.70 0.05 1.00 (0.20) 0.10 1.17 2.90 1.27 1.32 3.00 3.10

0.40 BSC

0.40 0.45 0.50 COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).1. DIMENSIONS e bbb aaa DIM N L E D A MILLIMETERS MAXMIN NOM b 0.15 0.20 0.25 SEATING PLANE bbb C A B aaa C C PIN 1 INDICATOR (LASER MARK) D E BA A Lx7 0.355 0.30 x 45° CHAMFER e 0.238 SEE DETAIL A CL CL 0.363 0.684 0.157 0.312 2X 0.200 2X 0.110 8X 0.025 DETAIL A SCALE: 4/1 1.30 N

0.800 E/2

0.265 0.950.25 D/2 e bxN CL LC Outline Drawing — MLPQ-13

Land Pattern — MLPQ-13 THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR NOTES: DIM X Y H K P G MILLIMETERS 0.20 0.80 1.27 0.40 0.75 1.50 DIMENSIONS COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3.10Z LAND PATTERNS ( SOLDER PADS) NOT REQUIRED FOR SMALLER EXPOSED PADS.3. G 2X 0.110 2X 0.200 8X 0.025 SMALL EXPOSED PADS LOCATION CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 4. DO NOT PLACE EXPOSED TRACES OR VIAS UNDER SMALLER EXPOSED PADS. 0.80P1 0.157 0.312 0.265 H 0.684 0.363 P1P 0.355 1.55 CCL CCL (P) 0.55 .250 K X 0.238 Z (P) (3.10) 1.30 Y

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