SC171

SC171 SEMTECH | Alldatasheet

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Features

3 to 5.5V VIN EN/ PSV PGND Enable / Power Save AGND LX VDD Power Good FB PGOOD BST TON VOUT = 0.75V to 95% VIN 1A EcoSpeedTM Synchronous Step-Down Regulator with Optional Ultrasonic Power Save SC171 POWER MANAGEMENT Typical Application Circuit

© 2010 Semtech Corporation Pin Configuration Ordering Information Marking Information AGND TON BST VIN LX PGND PGOOD VDD EN/PSV FB Device Top Mark Package(2) SC171MLTRT(1) 171 MLPD-10 3x3 SC171EVB Evaluation Board Notes: 1) Available in tape and reel packaging only. A reel contains 3000 devices. 2) Available in lead-free packaging only. WEEE compliant and Halogen free. This component and all homogenous sub-components are RoHS compliant. θJA= 40°C/W.

10 Pin MLPD

yyww= Date Code(Example:0952) xxxx= Semtech Lot Number(Example:3901) SC171

© 2010 Semtech Corporation Recommended Operating ConditionsAbsolute Maximum Ratings Thermal Information LX to GND(3)……………………… - 0.3(DC) to +6.0V(DC) Max VIN to PGND, EN/PSV to AGND ………………… -0.3 to +6.0V VDD to AGND, VOUT to AGND………………… -0.3V to +6.0V Maximum Continuous Output Current …………………… 1A Operating Junction Temperature ……………… -40 to +125°C Thermal Resistance, Junction to Ambient(1) ………… 40°C/W Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES- (1) Calculated from package in still air, mounted to 3” x 4.5” , 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B (3) Due to parasitic board inductance, the transient LX pin voltage at the point of measurement may appear larger than that which exists on silicon. The device is designed to tolerate the short duration transient voltages that will appear on the LX pin due to the deadtime diode conduction, for inductor currents up to the current limit setting of the device. See application section for details.

Electrical Characteristics

Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C Parameter Symbol Conditions Min Typ Max Units Input Supplies VIN, VDD Input Voltage 3 5.5 V VDD UVLO Threshold Rising UVLO VTH 2.75 2.85 2.98 V VDD UVLO Hysteresis 100 200 mV VIN, VDD Supply Current EN/PSV= 0V 5 15 μAIOUT=0A, PSAVE, fSW=25kHz(1) 744 Forced Continuous Conduction Mode EN floating, IOUT=0A , Not Switching 1000 Controller FB On-Time Threshold 0.7425 0.75 0.7575 V Frequency Programming Range See RTON Calculation 200 1000 kHz FB Input Bias Current FB=VDD or 0V -1 +1 μA SC171

© 2010 Semtech Corporation Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units Timing On-Time Continuous Mode VIN=5V, VOUT=3V, RTON=66.7kΩ 0.9 1 1.1 μs Minimum On-Time(1) 80 ns Minimum Off-Time(1) 250 ns Soft start Soft start Time(1) Delay from PWM Switching to Output Regulation 850 μs Ultrasonic Power Save Zero-Crossing Detector Threshold LX - PGND 0 mV Ultrasonic Power Save Frequency 25 kHz Power Good Power Good Threshold Power Good Signal Threshold High 116 120 124 %VOUT Power Good Signal Threshold Low 86 90 93 PGOOD Delay Time(1) VDD=3V 1 ms VDD=5V 2 Noise Immunity Delay Time 5 µs Leakage 1 µA Power Good On-Resistance 10 20 Ω Fault Protection Output Under-Voltage Fault FB with Respect to REF,

8 Consecutive Clocks -30 -25 -20 %

Output Over-Voltage Fault FB with Respect to REF +16 +20 +24 % Smart PowerSave Protection Threshold FB with Respect to REF +7 +10 +13 % OV, UV Fault Noise Immunity Delay 5 μs Over-Temperature Shutdown OT Latched 150 °C Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C SC171

© 2010 Semtech Corporation Electrical Characteristics (continued) Note: (1) Typical value from EVB, not ATE tested. Parameter Symbol Conditions Min Typ Max Units Enable/Power Save Output Enabled 1 V Output Disabled 0.4 V EN/PSV Input Bias Current EN/PSV = VDD or 0V 0.5 8.0 μA Power Save Enabled 60 %VDD Forced Continuous Conduction Mode EN/PSV floating 39 41 44 %VDD Gate Drivers BST Switch On resistance 40 75 Ω Internal Power MOSFETs Current Limit Valley Current Limit, VDD=5V 1.5 2.2 A Valley Current Limit, VDD=3V 1 1.4 LX Leakage Current VIN=5.5V, LX=0V, High Side 1 10 µA Switch Resistance High Side 105 160 mΩ Low Side 85 130 Non-overlap time (1) 30 ns Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C SC171

© 2010 Semtech Corporation Pin Descriptions (MLPD-10) Pin # Pin Name Pin Function 1 BST Bootstrap pin. A capacitor is connected between BST to LX to develop the floating voltage for the high-side gate drive. 2 VIN Power input supply voltage. 3 LX Switching (Phase) node. 4 PGND Power ground. 5 PGOOD Open-drain Power Good indicator. High impedance indicates power is good. An external pull-up resistor is required. 6 FB Feedback input for switching regulator. Connect to an external resistor divider from the output to program the output voltage.

7 EN/PSV

Tri-state pin. Enable input for switching regulator. Pull EN/PSV high to enable the part with power save mode enabled. Connect EN/PSV to AGND to disable the switching regulator. Leave EN/PSV floating to enable the IC in forced continuous conduction mode. 8 TON On-time set input. Set the on-time by a series resistor to AGND. 9 AGND Analog Ground. 10 VDD Input power for internal control circuit. Needs 1mF decoupling capacitor from this pin to AGND. PAD Thermal pad for heatsinking purposes. Connect to ground plane using multiple vias. Not con- nected internally. SC171

© 2010 Semtech Corporation Block Diagram EN PGOOD VDD AGND FB TON PGND VDD LX VIN BST Gate Drive Control Zero-Cross Valley Current Limit R Control On-Time Generator Reference Soft Start VDD 10 7 5 1 SC171

© 2010 Semtech Corporation Typical Characteristics Efficiency vs Output Current 65.0 70.0 75.0 80.0 85.0 90.0 95.0 100.0 0 0.25 0.5 0.75 1 Output Current (A) Efficiency (%) Vin=5V, Vo=3.3V, LOUT: DS86C-B992AS-2R0N, COUT=22mFx2 RTON = 90.9kOhm Red: PSAVE Mode Blue: Forced Continuous PWM Mode Efficiency vs Output Current 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 0 0.25 0.5 0.75 1 Output Current (A) Efficiency (%) Vin=5V, Vo=1.2V, LOUT: DS86C-B992AS-2R0N COUT=22mF+0.1mF RTON = 24.9kOhm Red: PSAVE Mode Blue: Forced Continuous PWM Mode Efficiency vs Output Current 50.0 55.0 60.0 65.0 70.0 75.0 80.0 85.0 90.0 95.0 0 0.25 0.5 0.75 1 Output Current (A) Efficiency (%) Vo=1.2V, RTON = 24.9kOhm LOUT: DS86C-B992AS-2R0N COUT:22mF+0.1mF Forced Continuous Mode Red:Vin = 3.5V Green: Vin = 4.0V Blue: Vin = 5.0V Output Voltage vs Output Current 3.320 3.326 3.332 3.338 3.344 3.350 3.356 3.362 0 0.25 0.5 0.75 1 Output Current (A) Output Voltage (V) Vin=5V, Vo=3.3V, LOUT: DS86C-B992AS-2R0N COUT=22mFx2 RTON = 90.9kOhm Blue: Forced Continuous PWM Mode Red: PSAVE Mode Output Voltage vs Output Current 1.216 1.217 1.218 1.219 1.220 1.221 1.222 1.223 1.224 0 0.25 0.5 0.75 1 Output Current (A) Output Voltage (V) Vin=5V, Vo=1.21V, LOUT: DS86C-B992AS-2R0N COUT=22mF+0.1mF RTON = 24.9kOhm Red: PSAVE Mode Blue: Forced Continuous PWM Mode Output Voltage vs Output Current 1.210 1.213 1.215 1.218 1.220 1.223 1.225 0 0.25 0.5 0.75 1 Output Current (A) Output Voltage (V) Vo=1.21V, RTON =24.9kOhm COUT:22mF+0.1mF LOUT: DS86C-B992AS-2R0N, Forced Continuous Mode Black: Vin = 3.5V Black: Vin = 3.5V Red: Vin = 4V Blue: Vin = 5.0V SC171

© 2010 Semtech Corporation Typical Characteristics OCP Valley Threshold vs Temperature 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 -50 -25 0 25 50 75 100 125 Temperature (°C) OCP Valley Threshold (A) VDD=5.0V VDD=3.0V IVIN Input Current In Shutdown vs Temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -40 -15 10 35 60 85 110 135 Temperature (°C) IVIN Input Current In Shutdown ( µA) VIN=5V Blue: VLX=VIN Black: V LX=GND IBST Leakage Current vs Te mperature -0.0200 -0.0180 -0.0160 -0.0140 -0.0120 -0.0100 -40 -15 10 35 60 85 110 135 Temperature (°C) IBST Leakage Current ( µA) VIN=5V VBST=VIN Start up waveform ( VIN=5V, VOUT=1.2V, IOUT=1A, Channel 1: 0.5V/Div, Channel 4: 0.5A/Div, Time: 0.5ms/Div ) Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 0A to 1A, Forced Continuous Conduction Mode, LOUT=1µH, COUT=2x22µF, Channel 1: 50mV/Div, Channel 2:5V/Div,Channel 4: 0.5A/Div, Time:20µs/Div) Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 1A to 0A, Forced Continuous Conduction Mode, LOUT=1µH, COUT=2x22µF, Channel 1: 50mV/Div, Channel 2:5V/Div,Channel 4: 0.5A/Div, Time:20µs/Div) SC171

© 2010 Semtech Corporation FB Voltage vs Temperature 0.745 0.748 0.750 0.753 0.755 -40 -15 10 35 60 85 110 135 Temperature (°C) FB Voltage (V) Black:VDD=5.0V Red: VDD=3.0V Low Side Switch On-State Resistance vs Temperature 105 115 -40 -15 10 35 60 85 110 135 Temperature (°C) On-State Resistance (mΩ) Blue: VDD=3.0V Black: VDD=5.0V High Side Switch On-State Resistance vs Temperature 100 110 120 130 140 150 -40 -15 10 35 60 85 110 135 Temperature (°C) On-State Resistance (mΩ) Blue: VDD=3.0V Black: VDD=5.0V Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 0A to 1A, PSAVE Mode Enabled, LOUT=1µH,COUT=2x22µF,Channel 1: 50mV/Div, Channel 2:5V/Div, Channel 4: 0.5A/Div, Time:20µs/Div) Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 1A to 0A, PSAVE Mode Enabled, LOUT=1µH,COUT=2x22µF,Channel 1: 50mV/Div, Channel 2:5V/Div, Channel 4: 0.5A/Div, Time:20µs/Div) Typical Characteristics SC171

© 2010 Semtech Corporation Applications Information SC171 Synchronous Buck Converter The SC171 is a step down synchronous buck dc-dc regu - lator. The SC171 is capable of 1A operation at very high efficiency in a tiny 3x3-10 pin package. The programma - ble operating frequency range of 200kHz – 1MHz enables the user to optimize the solution for minimum board space and optimum efficiency. The buck regulator employs pseudo-fixed frequency adaptive on-time control. This control scheme allows fast transient response thereby lowering the size of the power components used in the system. Input Voltage Range The SC171 can operate with an input voltage ranging from 3V to 5.5V. Psuedo-fixed Frequency Adaptive On-time Control The PWM control method used by the SC171 is pseudo- fixed frequency, adaptive on-time, as shown in Figure 1. The ripple voltage generated at the output capacitor ESR is used as a PWM ramp signal. This ripple is used to trig - ger the on-time of the controller. The adaptive on-time is determined by an internal one- shot timer. When the one-shot is triggered by the out - put ripple, the device sends a single on-time pulse to the high-side MOSFET. The pulse period is determined by VOUT and VIN; the period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate V OUT for the present VIN condition and at the selected frequency. The advantages of adaptive on-time control are: Predictable operating frequency compared to other variable frequency methods. Reduced component count by eliminating the error amplifier and compensation compo - nents. Reduced component count by removing the need to sense and control inductor current. Fast transient response — the response time is controlled by a fast comparator instead of a typically slow error amplifier. Reduced output capacitance due to fast tran - sient response One-Shot Timer and Operating Frequency The one-shot timer operates as shown in Figure 2. The FB Comparator output goes high when V FB is less than the internal 750mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator, timing capacitor, and a low pass filter (LPF) which regenerates V OUT from LX. One comparator input is connected to the filtered LX voltage, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to V IN. When the capacitor voltage reaches V OUT, the on-time is completed and the high-side MOSFET turns off. This method automatically produces an on-time that is proportional to V OUT and inversely proportional to V IN. Under steady-state operation conditions, the switching frequency can be determined from the on-time by the following equation. L COUT VIN ESR VLX FB CIN VOUT TON VLX FB threshold VFB Figure 1 — PWM Control Method, VOUT Ripple INON OUT SW VT Vf ×= SC171

© 2010 Semtech Corporation Figure 7 — Valley Current Limit Setting the valley current limit to a value of I LIM results in a peak inductor current of ILIM plus the peak-to-peak ripple current. In this situation, the average (load) current through the inductor will be I LIM plus one half the peak- to-peak ripple current. Soft start of PWM Regulator Soft start is achieved in the PWM regulator by using an internal voltage ramp as the reference for the FB comparator. The voltage ramp is generated using an internal charge pump which drives the reference from zero to 750mV in ~1.8mV increments, using an internal ~500kHz oscillator. When the ramp voltage reaches 750mV, the ramp is ignored and the FB comparator switches over to a fixed 750mV threshold. During soft start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft start profile for a wide range of applications. Typical soft start ramp time is 0.85ms. During soft start the regulator turns off the low-side MOSFET on any cycle if the inductor current falls to zero. This prevents negative inductor current, allowing the device to start into a pre-biased output up to 90% of the targeted output. This soft start operation is implemented even if FCM is selected. FCM operation is allowed only after PGOOD is high. Applications Information (continued) Time IPEAK ILOAD ILIM Inductor Current Power Good Output The power good (PGOOD) output is an open-drain output which requires a pull-up resistor. When the output volt - age is 10% below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns to the nominal voltage. PGOOD is held low during soft start and activated approximately 1ms after V OUT reaches regula - tion. The total PGOOD delay is typically 2ms. PGOOD will transition low if the V FB pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh- old (900mV). PGOOD also pulls low if the EN/PSV pin is low when VDD is present. Output Over-Voltage Protection Over-Voltage Protection (OVP) becomes active as soon as the device is enabled. The threshold is set at 750mV + 20% (900mV). When V FB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/ PSV input is toggled or VDD is cycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When V FB falls to 75% of its nominal voltage (falls to 562.5mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to turn off the MOSFETs. The controller stays off until EN/PSV is toggled or VDD is cycled. VDD UVLO, and POR Under-Voltage Lock-Out (UVLO) circuitry inhibits switch- ing and tri-states the power FETs until VDD rises above 2.9V. An internal Power-On Reset (POR) occurs when VDD exceeds 2.9V, which resets the fault latch and soft start counter to begin the soft start cycle. The SC171 then begins a soft start cycle. The PWM will shut off if VDD falls below 2.7V. SC171

© 2010 Semtech Corporation Design Procedure When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (V INMAX) is the highest speci - fied input voltage. The minimum input voltage ( V INMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design. Nominal output voltage (V OUT) Static or DC output tolerance Transient response Maximum load current (I OUT) There are two values of load current to evaluate — con - tinuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design. VIN = 5V + 10% VOUT = 1.0V + 4% fSW = 800kHz Load = 1A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 800kHz which results from using components selected for optimum size and cost . A resistor (RTON) is used to program the on-time (indirectly setting the frequency) using the following equation un -

• •••
• ••• Applications Information (continued) der zero load condition. Since the fSW may increase by about 100kHz per Ampere, RTON should be programmed at 700kHz under zero load to achieve 800kHz at full load. Calculating RTON results in the following solution. RTON=19.1kW, we use RTON=19.1kW in real application. Inductor Selection In order to determine the inductance, the ripple cur - rent must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates di - rectly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for power- save operation. The switching will typically enter pow - er-save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 0.5A then power-save operation will typically start for loads less than 0.25A. If ripple current is set at 40% of maxi - mum load current, then power-save will start for loads less than 20% of maximum current. The inductor value is typically selected to provide a rip - ple current that is between 25% to 50% of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is (VIN - V OUT). The equation for determining inductance is shown next. RIPPLE ONOUTIN I T)V-(VL ×= SWINMAX OUT ON fV VT ⋅= SWFB OUT TON f100pF 1)V V(R ⋅⋅= SC171

© 2010 Semtech Corporation Applications Information (continued) Example In this example, the inductor ripple current is set equal to 50% of the maximum load current. Therefore ripple current will be 50% x 1A or 0.5A. To find the minimum inductance needed, use the V IN and T ON values that cor - respond to VINMAX. So a 2µH inductor is selected. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is con - trolled by the output ripple requirement and the DC tol - erance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak- to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ±4% under static conditions. The internal 750mV refer - ence tolerance is 1%. Assuming a 1% tolerance from the FB resistor divider, this allows 2% tolerance due to V OUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 40mV for a 1V out - put. The maximum ripple current of 0.511A creates a ripple H20.5A 227ns1V)-(5.5VL m=•= 227nskHz8005.5V 1VTON_VINMAX =⋅= 0.485AH2 277ns1V)-(4.5VI MINRIPPLE_VIN =m L T)V-(VI ONOUTIN RIPPLE voltage across the ESR. The maximum ESR value allowed is shown by the following equations. 0.51A mV40 I VESR RIPPLEMAX RIPPLE MAX == ESRMAX = 78.4 mΩ The output capacitance is chosen to meet transient re - quirements. A worst-case load release, from maximum load to no load at the exact moment when inductor cur - rent is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1µs), the output capacitor must absorb all the inductor’s stored energy. This will cause a peak voltage on the capacitor according to the following equation. Assuming a peak voltage VPEAK of 1.050V (50mV rise upon load release), and a 1A load release, the required capaci - tance is shown by the next equation. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750mV reference, the DL output is high and the low-side MOSFET is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the -di/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed ca - pacitance for a given dI LOAD/dt. Peak inductor current is shown by the next equation. OUT PEAK RIPPLEMAXOUT MIN )(V-)(V )I2 1(IL COUT ×+× F31(1.0V)-(1.05V) 0.511A)2 1(1AH2 COUT 22 MIN m= ×+×m 277ns800kHz4.5V 1VTON_VINMIN =×= SC171

© 2010 Semtech Corporation Applications Information (continued) Rate of change of load current is IMAX = maximum load release = 1A Note that C OUT is much smaller in this example, 11µF compared to 31µF based upon a worst-case load re - lease. To meet the two design criteria of minimum 11µF and maximum 78 m Ω ESR, select one capacitor rated at 22µF and 15mΩ ESR or less. It is recommended that an additional small capacitor be placed in parallel with COUT in order to filter high frequen- cy switching noise. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-puls - ing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely af- ter the minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect opera - tion. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10mVp-p, which may dictate the need to 0.6A dt dILOAD 1V)-(1.05V2 s10.6A 1A-1V 1.26AH2 1.26ACOUT m××m F11C OUT m= .26A10.511A2 1A1ILPK =×+= increase the ESR of the output capacitors. It is also im - perative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~ 10pF) capacitor across the upper feedback resis - tor, as shown in Figure 8. This capacitor should be left unpopulated unless it can be confirmed that double- pulsing exists. Adding the C TOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. VOUT To FB pin CTOP Figure 8 — Capacitor Coupling to FB Pin ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Re - quirements section. The best method for checking sta - bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. One simple way to solve this problem is to add trace re - sistance in the high current output path. A side effect of adding trace resistance is a decrease in load regulation. ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insuf - ficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging ) V-V(2 dtdI I -V IL IC OUTPK LOAD MAX OUT LPK LPKOUT SC171

© 2010 Semtech Corporation Applications Information (continued) and discharging during the switching cycle. For most ap- plications, the total output ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching fre- quency. The formula for minimum ESR is shown by the following equation. Using Ceramic Output Capacitors When applications use ceramic output capacitors, the ESR is normally too small to meet the previously stated ESR criteria. In these applications it is necessary to add a small signal injection network as shown in Figure 9. In this network RL and CL filter the LX switching waveform to generate an in-phase ripple voltage comparable to the ripple seen on higher ESR capacitors. C C is a coupling ca- pacitor used to AC couple the generated ripple onto the FB pin. Capacitor CFF is required for min COUT applications. This capacitor introduces a lead/lag into the control with the maximum phase placed at 1/2 f SW for added stability. VLX L RL CL CC COUT VIN CFF Figure 9 — Signal Injection Circuit The values of RL, CL, CC and CFF are dependent on the con- ditions of the specific application such as VIN, VOUT, fSW and IOUT. For switching frequencies ranging from 600kHz to 800kHz, calculations plus experimental test results show that the following combination of R L=2.5kW, C L=10nF, CC=68pF and CFF=39pF can be used for many output volt- ages and loads. SWOUT MIN fC2 3ESR ××π×= Output Voltage Dropout The output voltage adjustable range for continuous- conduction operation is limited by the fixed 320ns (typi - cal) minimum off-time. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The duty-factor limitation is shown by the next equation. )MAX(OFF)MIN(ON )MIN(ON TT TDUTY The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy — VOUT Controller Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static condi - tions it trips when the feedback pin is 750mV, +1%. The on-time pulse from the SC171 in the design example is calculated to give a pseudo-fixed frequency of 800kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Be - cause adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with V IN = 5 volts, then the measured DC output will be 25mV above the comparator trip point. If the rip - ple increases to 30mV with VIN = 5.5V, then the measured DC output will be 15mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation, it may be desirable to use passive droop. Take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output ca - pacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regula - tion limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. SC171

© 2010 Semtech Corporation Applications Information (continued) The use of 1% feedback resistors may result in up to an additional 1% error. If tighter DC accuracy is required, re - sistors with lower tolerances should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the power FET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to fall slightly with increasing input voltage. The switching frequency also varies with load current as a result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing en - ergy from VIN as losses increase). The on-time is essential- ly constant for a given VOUT and VIN combination, to offset the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency in - creases slightly with increasing load. Switching Node Voltage Spike Due to parasitic board inductance, the transient LX pin voltage at the point of measurement may appear larger than that which exists on silicon. With an input multilay - er ceramic capacitor of 10uF placed less than 3mm away from the PVIN pin, the device is designed and guaranteed to tolerate the short transient voltages, of maximum 20ns duration, that will appear on the LX pin due to the deadtime diode conduction, as long as the transient volt- age on PVIN is less than 6.0V. The time duration of the transient LX pin voltage is measured on the voltage por - tion which is either over 6.0V for positive voltage spike or under -1V for negative voltage spike. The LX voltage is measured from the LX pin to the PGND pin by using a probing loop which is as short as possible to minimize or eliminate the switching noise pick up. SC171

© 2010 Semtech Corporation Layout Guideline Since the SC171 has integrated switches, special consid - eration should be given to board layout. Let us use the schematic shown above as an example. The board level layout is illustrated in the following four layers. As shown on the top layer layout, U1 is the switching regulator SC171. C1 and C11 serve as the decoupling ca - pacitor for the buck converter power train. C11, with a value between 1nF and 10nF, is the high frequency filter- ing capacitor. It is recommended to put C1 and C11 as close as possible to the SC171 to get the best decoupling performance, with C11 closest. C1, with a value of 10uF, should be placed no more than 3mm away from the VIN pin. L1 is the output filtering inductor. C2, C3 and C4 are the output filtering capacitors. C5 is the boostrap capaci - tor. Pin 10 (VDD) is the input bias power for the internal circuits. It is recommended to get the power from VIN through an RC filtering network consisted of R1, C6 and C10. The value of R1 can be between 3.01W and 10W and the capacitance of C10 should be above 1 mF. C6, with a value of 1nF, is the high frequency filtering capacitor. The locations of C6 and C10 should be as close as possible to pins 9 and 10, with C6 closest, to get the best possible filtering result. R2 is the on-time programming resistor. R2 should be located as close as possible to pin 8 and it should return to analog ground. The EN/PSV pin is a tri- state pin. Pull EN/PSV high to enable the part with power save mode enabled. Connect EN/PSV to AGND to disable the switching regulator. Leave EN/PSV floating to enable the IC in forced continuous conduction mode. Since there are two integrated MOSFETs inside the SC171 that will dissipate a lot of power, to help spread the heat out of the IC more efficiently, there is a thermal pad un - derneath the SC171 serving as a heat sink. To enlarge the heat sinking area, a large copper plane under the thermal pad as shown on the top layer is recommended. On inner layer 2, a large analog ground plane (AGND) on the right hand side is connected to the thermal pad un - derneath the SC171 using vias. Thus the heat generated inside the SC171 can be spread through the vias to the 5 6 BST VIN LX PGND EN/PSV TON AGND VDD PGOOD FB PAD EN/PSV VIN+ VIN- VO+ VO- SC171 C10 C11 5 6 Schematic for layout illustration SC171

© 2010 Semtech Corporation inner layers to expand the heat sinking area. On the bottom layer, the resistor network composed of R3 and R4 determines the output voltage. C7 is the feed forward capacitor which helps to stabilize the circuit. R6 in series with C9 is connected to the LX pin (through the via) to the power ground. C8 is the coupling capacitor which injects the ramp signal generated on C9 to the FB pin of the SC171. R7 is the pull up resistor for the PGOOD pin. SC171

© 2010 Semtech Corporation PGND VO+ VO AGND AGND C11 C5 C6 R1 VO+ AGND VO 5 6 PGND LX VIN+ Inner Layer 1 Top LayerVIN+ EN/PSV C10 VIN VIN SC171

© 2010 Semtech Corporation VO+ AGND 5 6 PGND LX VIN+ VIN VO+ AGND VO R4C7 5 6 Bottom Layer Inner Layer 2 LX PGND VIN VO SC171

© 2010 Semtech Corporation Typical Application Circuits C18 68pF 15k 1uF/6.3V VOUT+ C19 10n 9.09k R5 2.49k 24.9k FB 10uF/6.3V BST VIN LX PGND EN/PSV TON AGND VDD PGOOD FB 10uF/6.3V VOUT- R4 100k C10 38p VIN- 22uF/6.3v 2.0uH 5.11Ohm VIN+ SC171 Enable FB C101 0.1uF/6.3V C501 0.1uF/6.3V Application Circuit: Buck Converter with 1.2V out and 0 to 1A load current (Vin= 5V) C18 68pF 15k 1uF/6.3V VOUT+ C19 10n 51.1k R5 10.5k 90.9k 10uF/6.3V BST VIN LX PGND EN/PSV TON AGND VDD PGOOD FB 10uF/6.3V VOUT- R4 100k C10 38p VIN- 22uF/6.3v 2.0uH 5.11Ohm VIN+ SC171 FB Enable FB 0.1uF/6.3V C101 0.1uF/6.3V C501 22uF/6.3v Application Circuit: Buck Converter with 3.3V out and 0 to 1A load current (Vin=5V) SC171

© 2010 Semtech Corporation Outline Drawing - MLPD-10 3x3 NOTES: CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.2. .003 .008 .010 .000 .031 (.008) 0.08 0.25 .012 0.20 .039 .002 0.00 0.80 0.30 0.05 1.00 (0.20) .004 0.10 0.50 BSC.020 BSC aaa C SEATING PLANE A bbb C A B B e C (LASER MARK) INDICATOR PIN 1 N MIN aaa bbb b e L N D A DIM MILLIMETERS NOM DIMENSIONS MAXNOM INCHES MIN MAX D E D/2 A E/2 bxN LxN SC171

© 2010 Semtech Corporation Land Pattern - MLPD-10 3x3 G Y K H .087 .055 2.20 1.40 .146 .020 .012 .031 3.70 0.30 0.80 0.50 (.114) .083 2.10 (2.90) THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FUNCTIONAL PERFORMANCE OF THE DEVICE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR INCHES DIMENSIONS G K H X Y P Z C DIM MILLIMETERS CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). X P Z(C) CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DIMENSIONS INCHES C (.112) FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: X Z Y K P H G .012 .033 .146 .079 .020 .059 .089 DIM (2.85) 0.30 0.85 3.70 2.00 0.50 1.50 2.25 MILLIMETERS X P G Y Z(C) H K SC171

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