SC1103 SEMTECH | Alldatasheet

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© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 BLOCK DIAGRAM Pentium is a registered trademark of Intel Corporation PIN CONFIGURATION Top View (SO-8)

DESCRIPTION

The SC1103 is a versatile, low-cost, voltage- mode PWM controller designed for use in single ended DC/DC power supply applications. A sim- ple, fixed-voltage buck regulator can be imple- mented using the SC1103 with a minimum of ex- ternal components. Internal level shift and drive circuitry eliminates the need for an expensive p- channel, high-side switch. The small device foot- print allows for compact circuit design. SC1103 features include a temperature compen- sated voltage reference, triangle wave oscillator, current limit comparator, frequency shift over- current protection, and an internally compensated error amplifier. Pulse by pulse current limiting is implemented by sensing the differential voltage across an external resistor, or an appropriately sized PC board trace. The SC1103 operates at a fixed frequency of 200kHz, providing an optimum compromise be- tween efficiency, external component size, and cost.

FEATURES

  • Low cost / small size
  • Switch mode efficiency (90%)
  • 1% reference voltage accuracy
  • Over current protection
  • 500mA output drive
  • 5V to 12V Input power source

APPLICATIONS

Pentium® P55 Core Supply

  • Low Cost Microprocessor Supplies
  • Peripheral Card Supplies
  • Industrial Power Supplies
  • High Density DC/DC Conversion TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

ORDERING INFORMATION

(1) PACKAGE TEMP RANGE (T J) SC1103CS SO-8 0° to 125°C Note: (1) Add suffix ‘TR’ for tape and reel.

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 Pin # Pin Name Pin Function 1V CC Device Input Voltage 2C s(-) Current Sense Input (Negative) 3C s(+) Current Sense Input (Positive) 4P GND Device Power Ground

5 DH High Side Driver Output

6 BST High Side Driver V BST (Boost)

7 FB Error Amplifier Input (-)

8 GND Small Signal Ground

Parameter Symbol Maximum Units Input Voltage V CC to GND -0.3 to 14 V Ground Differential P GND to GND ± 1 V Boost Input Voltage BST to GND -0.3 to +26 V Operating Temperature T A 0 to +70 °C Storage Temperature T S -45 to +125 °C Lead Temperature (Soldering) 10 seconds T L 300 °C Thermal Resistance, Junction to Ambient θ JA 165 °C/W Thermal Resistance, Junction to Case θ JC 40 °C/W PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 TEST CIRCUIT

ELECTRICAL CHARACTERISTICS

VCC = 11.50V to 12.50V; GND = PGND = 0V; VO = 3.3V; TA = 25°C; BST = 24+ 1V; Output current = 2A. Per test circuit, unless otherwise specified. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Reference V REF 1.238 1.250 1.263 V Over Temp 1.225 1.250 1.275 V Feedback Bias Current I FB 2.0 8.0 uA Quiescent Current I Q Current into VCC pin 5.0 8.0 mA Regulation Load REG LOAD IO = 1A to 10A 0.5 1.0 % Regulation Line REG LINE IO = 10A 0.5 % Current Limit Threshold CLT CS(+) to CS(-) 60 70 80 mV Oscillator Frequency OSC 180 200 220 kHz Oscillator Frequency Shift OFS V FB < VREF/2 50 kHz Max Duty Cycle d.c. 90 95 % DH Sink/Source Current I O VBST - VDH = 4.5V (VDH - VPGND = 2V) 500 mA UVLO Threshold V UVLO 3.8 V IRL3103S 2.7 MBRB1530CT 5.6uH 1500/6.3 C10 1500/6.3 C11 1500/6.3V 820/16V 820/16V 820/16V 0.1 124 *see noteC1 0.1 0.01 Vout(+)+12V GND 0.1 C12 0.1 0.01 Vout(-) VCC1 Cs(-)2 Cs(+)3 PGND4 DH 5 BST 6 FB 7 GND 8 SC1103 * NOTE: R6 = 124 x (Vout/1.25 - 1) rounded to nearest 1%value 0.1 + 20 to 24V

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 Fig. 3: VRIPPLE @ VIN = 12V, VO = 3.3V, IO = 10A Fig. 2: Load Regulation @ VO = 3.3V, VIN = 12V -10 Frequency (Hz) Gain (dB) -45 135 180 Phase (deg) Gain Phase Fig.1: Error Amplifier, Gain and Phase Fig. 6: Line Regulation @ VO = 3.3V, IO = 10AFig. 5: Efficiency @ VIN = 12V Fig. 4: Load Regulation @ VIN = 12V -0.020 -0.010 0.000 0.010 0.020 0.030 0.040 0.050 02468 1 0 Current (Amps) Voltage Change (V) Normalized to 0 at Io=2A. -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 02468 1 0 1 2 1 4 Output Current, (A) Load Regulation 1.8V 2.5V 3.3V 5.0V Vo= 40% 50% 60% 70% 80% 90% 100% 0 2 4 6 8 10 12 14 Output Current, (A) Efficiency 1.8V 2.5V 3.3V -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% Input Voltage, (V) Line Regulation

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1103 PWM controller. High currents switching at 200kHz are pre- sent in the application and their effect on ground plane voltage differentials must be understood and mini- mized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to con- strain ground currents to particular areas, for example the input capacitor and bottom Schottky ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Schottky (D1) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will reduce EMI, lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and mini- mize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, D1 and the output inductor should be a wide trace or cop- per region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The c onnec- tion between the output inductor and the sense resis- tor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnec- essary impedance will reduce efficiency. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1103 is best placed over an isolated ground plane area. GND and PGND should be returned to this isolated ground. This isolated ground area should be connected to the main ground by a trace that runs from the GND pin to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, D1 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, D1 loop. 6) Vcc for the SC1103 should be supplied from the VIN supply through a 10Ω resistor, the Vcc pin should Vout 12V 4uH 5mOhm Cout +Cin 0.1uF 2.32k 1.00kQ1 0.1uF 24V IN Heavy lines indicate high current paths. SC1103CS GND 8VCC1 CS(-)2 CS(+)3 PGND DH 5 BST FB 7 Rb Ra Fig. 7 Layout diagram for the SC1103

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 be decoupled directly to GND by a 0.1µF ceramic ca- pacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces run- ning back to CS(+) and CS(-) on the SC1103 should run parallel and close to each other. The 0.1µF capaci- tor should be mounted as close to the CS(+) and CS(-) pins as possible. 8) To minimize noise pickup at the sensitive FB pin, the feedback resistors should both be close to the SC1103 with the bottom resistor (Rb) returned to ground at the GND pin. Under Voltage Lockout The under voltage lockout circuit of the SC1103 as- sures that the high-side MOSFET driver outputs remain in the off state whenever the supply voltage drops be- low set parameters. Lockout occurs if V CC falls below 3.8V. Normal operation resumes once VCC rises above 3.8V. Fig. 8: 5V to 3.3V @ 8A TYPICAL APPLICATIONS IRL3103S 2.7 MBRB1530CT 5.6uH 1500/6.3 C10 1500/6.3 C11 1500/6.3V 1500/6.3V 1500/6.3V 0.1 124 205 0.1 0.01 +3.3V +5V GND 0.1 C12 0.1 0.012 GND VCC1 Cs(-)2 Cs(+)3 PGND4 DH 5 BST 6 FB 7 GND 8 SC1103 0.1 +12V

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 Fig. 9: 5V to 2.5V @ 4A with “flying capacitor” boost voltage. TYPICAL APPLICATIONS (cont.) Si4420DY 2.7R2 MBRD340 6.8uH 1500/6.3VC2 1500/6.3V 0.1 124 124 0.1 0.01 +2.5V+5V GND 0.1 0.012 GND VCC1 Cs(-)2 Cs(+)3 PGND4 DH 5 BST 6 FB 7 GND 8 SC1103 0.1 LL42 0.1 Fig. 10: 12V to 3.3V @ 10A with “flying capacitor” boost voltage. IRL3103S 2.7 MBRB1530CT 5.6uH 1500/6.3 C10 1500/6.3 C11 1500/6.3V 820/16V 820/16V 820/16V 0.1 124 205 0.1 0.01 Vout(+)+12V GND 0.1 C12 0.1 R50.01 Vout(-) VCC1 Cs(-)2 Cs(+)3 PGND4 DH 5 BST 6 FB 7 GND 8 SC1103 1.0 LL42 3.3V

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 OUTLINE DRAWING JEDEC REF: MS-012AA LAND PATTERN SO-8 ECN00-899