MPC5200B_10 FREESCALE | Alldatasheet
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Data Sheet: Technical Data Document Number: MPC5200BDS Rev. 4, 02/2010 © Freescale Semiconductor, Inc., 2008, 2010. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. TEPBGA–272 27 mm x 27 mm Key features are shown below.
- MPC603e series e300 core – Superscalar architecture – 760 MIPS at 400 MHz (–40 oC to +85 oC) – 16 KB Instruction cach e, 16 KB Data cache – Double precision FPU – Instruction and Data MMU – Standard and Critical interrupt capability
- SDRAM / DDR Memory Interface – Up to 133 MHz operation – SDRAM and DDR SDRAM support – 256 MB addressing range per CS, two CS available – 32-bit data bus – Built-in initialization and refresh
- Flexible multi-function External Bus Interface – Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices – 8 programmable Chip Selects – Non-multiplexed data access using 8-/16-/32-bit databus with up to 26-bit address – Short or Long Burst capable – Multiplexed data access us ing 8-/16-/32-bit databus with up to 25-bit address
- Peripheral Component Inte rconnect (PCI) Controller – Version 2.2 PCI compatibility – PCI initiator and target operation – 32-bit PCI Address/Data bus – 33 and 66 MHz operation – PCI arbitration function
- ATA Controller – Version 4 ATA compatible external interface—IDE Disk Drive connectivity
- BestComm DMA subsystem – Intelligent virtual DMA Controller – Dedicated DMA channels to control peripheral reception and transmission – Local memory (SRAM 16 KB)
- 6 Programmable Serial Controllers (PSC) – UART or RS232 interface – CODEC interface for Soft Modem, Master/Slave CODEC Mode, I 2S and AC97 – Full duplex SPI mode – IrDA mode from 2400 bps to 4 Mbps
- Fast Ethernet Controller (FEC) – Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE
802.3 MII, 10 Mbps 7-wire interface
- Universal Serial Bus Controller (USB) – USB Revision 1.1 Host – Open Host Controller Interface (OHCI) – Integrated USB Hub, with two ports.
- Two Inter-Integrated Circuit Interfaces (I 2C)
- Serial Peripheral Interface (SPI)
- Dual CAN 2.0 A/B Controller (MSCAN) – Implementation of version 2.0A/B CAN protocol – Standard and extended data frames
- J1850 Byte Data Link Controller (BDLC)
- J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125 kbps) serial data communications in automotive applications.
- Supports 4X mode, 41.6 kbps
- In-frame response (IFR) type s 0, 1, 2, and 3 supported
- Systems level features – Interrupt Controller supports four external interrupt request lines and 47 internal interrupt sources – GPIO/Timer functions Up to 56 total GPIO pins that support a variety of interrupt/WakeUp capabilities. Eight GPIO pins with timer capability supporting input capture, output compare, and pulse width modulation (PWM) functions – Real-time Clock with one-second resolution – Systems Protection (watch dog timer, bus monitor) – Individual control of functional block clock sources – Power management: Nap, Doze, Sleep, Deep Sleep modes – Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
- Test/Debug features – JTAG (IEEE 1149.1 test access port) – Common On-chip Processor (COP) debug port
- On-board PLL and clock generation MPC5200B Data Sheet
MPC5200B Data Sheet, Rev. 4 Freescale Semiconductor2 Table of Contents 1.3.14 I 3.2 System and CPU Core AVDD Power Supply Filtering. 65
3.3.1 Pull-down Resistor R equirements for TEST pins65
3.3.2 Pull-up Requirements for the PCI Control Lines 66
3.3.3 Pull-up/Pull-down Requirements for MEM_MDQS
3.3.4 .Pull-up/Pull-down Requirements for MEM_MDQS
Figure 1 shows a simplified MPC5200B block diagram. Figure 1. Simplified Block Diagram—MPC5200B
16 KB DMA
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1 Electrical and Thermal Characteristics
1.1 DC Electrical Characteristics
1.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC5200B DC Electrical characteristics. Table 1 gives the absolute maximum ratings.
1.1.2 Recommended Operating Conditions
Table 2 gives the recommended operating conditions. Table 1. Absolute Maximum Ratings (1) 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage. Table 2. Recommended Operating Conditions
1.1.3 DC Electrical Specifications
Table 3 gives the DC Electrical characteristics for the MPC5200B at recommended operating conditions (see Table 2). 2 Maximum e300 core operating frequency is 400 MHz. Table 3. DC Electrical Specifications Table 2. Recommended Operating Conditions (continued)
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1 Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. Table 4. Drive Capability of MPC5200B Output Pins Table 3. DC Electrical Specifications (continued)
1.1.4 Electrostatic Discharge
CC). Table 7 gives package thermal characteristics for this device.
1.1.5 Power Dissipation
MPC5200B processor must not exceed the value, which would cause the maximum junction temperature to be exceeded. Table 5. ESD and Latch-Up Protection Characteristics
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Table 6. Power Dissipation instructions in parallel with a continuous PCI transaction via BestComm. 2.5 V the IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3 V.
1.1.6 Thermal Characteristics
1.1.6.1 Heat Dissipation
appropriate if the board has low power dissipation and the components are well separated. Table 7. Thermal Resistance Data 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. measured on the top surface of the board near the package.
5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
MPC5200B Data Sheet, Rev. 4
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RθJA =R θJC+R θCA Eqn. 4 where: RθJA = junction to ambient thermal resistance (ºC/W) RθJC = junction to case thermal resistance (ºC/W) RθCA = case to ambient thermal resistance (ºC/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ =T T+( ΨJT × PD) Eqn. 5 where: TT = thermocouple temperature on top of package (ºC) ΨJT = thermal characterization parameter (ºC/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
1.2 Oscillator and PLL Electrical Characteristics
The MPC5200B System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent Real-Time Clock (RTC) system. The MPC5200B clock generation uses two phase locked loop (PLL) blocks.
- The system PLL (SYS_PLL) takes an ex ternal reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration.
- The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.
1.2.1 System Oscillator Electrical Characteristics
1.2.2 RTC Oscillator Electrical Characteristics
1.2.3 System PLL Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics Table 9. RTC Oscillator Electrical Characteristics Table 10. System PLL Specifications types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
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1.3 AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
1.3.1 AC Test Timing Conditions:
- TA = –40 to 85 oC
- Tj = –40 to 115 oC
- VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V
Table 11. e300 PLL Specifications
1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system
minimum operating frequencies in Table 12. types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
- AC Operating Frequency Data • USB
- Clock AC Specifications • SPI
- R e s e t s •M S C A N
- External Interrupts • I
- SDRAM • J1850
- P C I •P S C
- Local Plus Bus • GPIOs and Timers
- ATA • IEEE 1149.1 (JTAG) AC Specifications
- Ethernet
- Input conditions: All Inputs: tr, tf <= 1 ns
- Output Loading: All Outputs: 50 pF
1.3.2 AC Operating Frequency Data
Table 12 provides the operating frequency information for the MPC5200B.
1.3.3 Clock AC Specifications
Figure 2. Timing Diagram—SYS_XTAL_IN Table 12. Clock Frequencies Table 13. SYS_XTAL_IN Timing 2 SYS_XTAL_IN duty cycle is measured at VM.
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1.3.4 Resets
- PORRESET —Power on Reset
- H R E S E T—Hard Reset
- S R E S E T—Software Reset These signals are asynchronous I/O signals an d can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards its minimum pulse width equals the minimum given for HRESET related to the same reference clock. The tVDD_stable describes the time which is needed to get all power supplies stable. For tlock, refer to the Oscillator/PLL section of this specification for further details. For tup_osc, refer to the Oscillator/PLL section of this specification for further details. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles. NOTE As long as VDD is not stable the HRESET output is not stable. NOTE Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter to prevent them from getting into the chip. HRESET and SRESET must have a monotonous rise time. The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock.
Table 14. Reset Pulse Width Table 15. Reset Rise/Fall Timing
For additional information, see the MPC5200B User’ s Manual (MPC5200BUM).
1.3.4.1 Reset Configuration Word
contents of this register are locked immediately with the SYS_XTAL clock (see Figure 3). Figure 3. Reset Configuration Word Locking clock ratios and so extend the PLL locking process.
1.3.5 External Interrupts
- Four IRQ interrupts
- Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)
- Eight WakeUp interrupts (special GPIO pins) The propagation of these three kinds of interrupts to the core is shown in the following graphic: sample sample sample sample sample sample sample sample sample sample LOCK RST_CFG_WRD HRESET PORRESET SYS_XTAL 4096 clocks
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Figure 4. External Interrupt Scheme cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Table 16). 1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200B User’s Manual. Table 16. External Interrupt Latencies
8 GPIOs
8 GPIOs GPIO WakeUp
- PIs = Programmable Inputs
- Grouper and Encoder functions imply programmability in software
sources. Take care of interrupt prioritization which may increase the latencies. to exceed a minimum pulse width of more than one IP_CLK cycle. (MPC5200BUM) for further information. interrupt is not recognized at all. and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
1.3.6 SDRAM
1.3.6.1 Memory Interface Timing -Standard SDRAM Read Command
Table 17. Minimum Pulse Width for External Interrupts to be Recognized Table 18. Standard SDRAM Memory Read Timing
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Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
1.3.6.2 Memory Interface Timing -Standard SDRAM Write Command
Table 19. Standard SDRAM Write Timing
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
1.3.6.3 Memory Interface Timing-DDR SDRAM Read Command
is calculated automatically by hardware. Table 20. DDR SDRAM Memory Read Timing
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Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing
1.3.6.4 Memory Interface Timi ng-DDR SDRAM Write Command
Figure 8. DDR SDRAM Memory Write Timing
1.3.7 PCI
other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors. environments. Table 22 summarizes the clock specifications. Table 21. DDR SDRAM Memory Write Timing
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Figure 9. PCI CLK Waveform
- In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending
upon whether the clock frequency is above 33 MHz.
- Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown in Figure 9.
- The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
- See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive
to their Voh or Vol level within one Tcyc. Table 22. PCI CLK Specifications
66 MHz 33 MHz
Table 23. PCI Timing Parameters
0.3 Vcc
0.5 Vcc
0.6 Vcc
0.2 Vcc (minimum)
- Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
as shown in the PCI Local Bus Specification.
- REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have
a setup of 5 ns at 66 MHz. All other signals are bused.
- See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
1.3.8 Local Plus Bus
PCI CLK. The maximum bus frequency is 66 MHz.
- WS = Wait State
- DC = Dead Cycle
- LB = Long Burst
- DS = Data Size in Bytes PCIck = PCI clock period
- t IPBIck = IPBI clock period
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
1.3.8.1 Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
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- ACK can shorten the CS pulse width.
- In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment
as the CS. This can cause the address to change before CS is deasserted.
- ACK is input and can be used to shorten the CS pulse width.
- Only available in Large Flash and MOST Graphics mode.
- Only available in MOST Graphics mode.
- Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules. Table 24. Non-MUXed Mode Timing (continued)
Figure 11. Timing Diagram—Non-MUXed Mode
1.3.8.2 Burst Mode
Table 25. Burst Mode Timing
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- Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
1 ×2×( 3 2 /8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line. 1+ 10 + 32 = 43 => CS is asserted for 43 PCI cycles.
- ACK is output and indicates the burst.
- Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules. Figure 12. Timing Diagram—Burst Mode Table 25. Burst Mode Timing (continued)
1.3.8.3 MUXed Mode
- ACK can shorten the CS pulse width.
- ACK is input and can be used to shorten the CS pulse width.
- Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules. Table 26. MUXed Mode Timing
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Figure 13. Timing Diagram—MUXed Mode
1.3.9 ATA
nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ATA drive for different ATA protocols and their respective timing. See the MPC5200B User’ s Manual (MPC5200BUM). PIO and Multiword DMA modes.
- Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup time beyond that required by the ATA-4 specification.
- Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold time beyond that required by the ATA-4 specification. PCI CLK AD[24:0] (wr) CSx R/W ALE AD[30:28] (wr) AD[26:25] (wr) AD[31,27] (wr) Address[7:31] Bank[0:1] bits TSIZ[0:2] bits ACK Data Data tenureAddress tenure TS Data Data Data AD[31:0] (rd) Data t13 Address latch t11 t12 t10 OE t14 t15 t16
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
- The MPC5200B operating frequency (IP bus clock frequency)
- Internal MPC5200B bus latencies
- Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User’ s Manual (MPC5200B). NOTE All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
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Figure 14. PIO Mode Timing Table 28. Multiword DMA Timing Specifications
Figure 15. Multiword DMA Timing is towards the bottom of the page, irrespective of the electrical properties of the signal. Table 29. Ultra DMA Timing Specification next falling edge of STROBE. from STOP during a data-in burst.
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the other agent to respond with a signal before proceeding. t UI is an unlimited interlock that has no maximum time value. t MLI is a limited time-out that has a defined minimum. t LI is a limited time-out that has a defined maximum. HDMARDY during data out burst initiation. receives no more than one additional data word. are sent this long after negation of DMARDY. initiate pause after negating DMARDY. assertion of STOP , when sender terminates a burst. Table 29. Ultra DMA Timing Specification (continued)
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Figure 18. Timing Diagram—Host Paus ing an Ultra DMA Data In Burst Figure 19. Timing Diagram—Drive Termi nating Ultra DMA Data In Burst
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Figure 22. Timing Diagram—Sustai ned Ultra DMA Data Out Burst Figure 23. Timing Diagram—Drive Paus ing an Ultra DMA Data Out Burst
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Figure 26. Timing Diagram—ATA-ISOLATION
1.3.10 Ethernet
- Output Loading All Outputs: 25 pF
Figure 27. Ethernet Timing Diagram—MII Rx Signal Table 30. Timing Specification ata_isolation Table 31. MII Rx Signal Timing 1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
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Figure 30. Ethernet Timing Diagram—MII Serial Management
1.3.11 USB
Output timing is specified at a nominal 50 pF load. Table 34. MII Serial Management Channel Signal Timing register is changed during operation. See the MPC5200B User’s Manual (MPC5200BUM). Table 35. Timing Specifications—USB Output Line
1 USB Bit width (1)
1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
Figure 31. Timing Diagram—USB Output Line
1.3.12 SPI
Output timing is specified at a nominal 50 pF load. Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
1 Cycle time 4 1024 IP-Bus Cycle (1)
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
4 Output Data valid after Slave Select (SS
9 Sequential transfer delay 1 — IP-Bus Cycle
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Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Output timing is specified at a nominal 50 pF load. Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Output timing is specified at a nominal 50 pF load. Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
8 Sequential Transfer delay 1 — IP-Bus Cycle
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Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Output timing is specified at a nominal 50 pF load. Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
1.3.13 MSCAN
WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
1.3.14 I 2C
Table 40. I2C Input Timing Specifications—SCL and SDA
1 Start condition hold time 2 — IP-Bus Cycle (1)
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
6 Clock high time 4 — IP-Bus Cycle
8 Start condition setup time (for repeated start condition
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Output timing is specified at a nominal 50 pF load. Figure 36. Timing Diagram—I 2C Input/Output
1.3.15 J1850
See the MPC5200B User’ s Manual (MPC5200BUM). Table 41. I2C Output Timing Specifications—SCL and SDA position is affected by the prescale and division values programmed in IFDR. or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
1.3.16 PSC
1.3.16.1 Codec Mode (8-,16 -, 24-, and 32-bit)/I2S Mode
Output timing is specified at a nominal 50 pF load. Figure 37. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I 2S Master Mode Table 42. Timing Specifications—8-, 16-, 24-, and 32-bit CODEC / I 2S Master Mode
2 Clock duty cycle — 50 — % (1)
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Output timing is specified at a nominal 50 pF load. Figure 38. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I 2S Slave Mode Table 43. Timing Specifications — 8-, 16-, 24-, and 32-bit CODEC / I 2S Slave Mode
1.3.16.2 AC97 Mode
Output timing is specified at a nominal 50 pF load. Figure 39. Timing Diagram — AC97 Mode
1.3.16.3 IrDA Mode
Output timing is specified at a nominal 50 pF load. Table 44. Timing Specifications — AC97 Mode Table 45. Timing Specifications — IrDA Transmit Line
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Figure 40. Timing Diagram — IrDA Transmit Line
1.3.16.4 SPI Mode
Output timing is specified at a nominal 50 pF load. Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
9 Sequential Transfer delay, programable in the PSC CTUR / CTLR
Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Output timing is specified at a nominal 50 pF load. Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
6 Output data valid after SS
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Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Output timing is specified at a nominal 50 pF load. Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
8 Sequential Transfer delay, programable in the PSC CTUR / CTLR
Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Output timing is specified at a nominal 50 pF load. Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
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Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
1.3.17 GPIOs and Timers
1.3.17.1 General and Asynchronous Signals
a 133 MHz internal bus frequency. Figure 45 shows the GPIO Timing Diagram. Table 50 gives the timing specifications. Table 50. Asynchronous Signals
Figure 45. Timing Diagram—Asynchronous Signals
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Figure 46. Timing Diagram—JTAG Clock Input Figure 47. Timing Diagram—JTAG TRST Table 51. JTAG Timing Specification setup time to tck falling edge(1). 1 TRST is an asynchronous signal. The setup time is for test purposes only. 6 Input data setup time (2). 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 8 TCK to output data valid (3). 3 Non-test, other than TDO, signal output timing with respect to TCK. Numbers shown reference Table 51. Numbers shown reference Table 51.
Figure 48. Timing Diagram—JTAG Boundary Scan Figure 49. Timing Diagram—Test Access Port
2 Package Description
2.1 Package Parameters
- Package outline: 27 mm x 27 mm
- Interconnects: 2
- Pitch: 1.27 mm TCK INPUT DATA VALID OUTPUT DATA VALID DATA INPUTS DATA OUTPUTS DATA OUTPUTS 6 7 Numbers shown reference Table 51. TCK INPUT DATA VALID OUTPUT DATA VALID TDI, TMS TDO TDO 10 11 Numbers shown reference Table 51.
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2.2 Mechanical Dimensions
Figure 50. Mechanical Dimensions and Pinout Assignments for the MPC5200B, 272 TE-PBGA
- DIMENSIONS AND TOLERANCING PER ASME
- DIMENSIONS IN MILLIMETERS.
- DIMENSION IS MEASURED AT THE MAXIMUM
- PRIMARY DATUM A AND THE SEATING PLANE
2.3 Pinout Listings
See details in the MPC5200B User’ s Manual (MPC5200BUM). Table 52. MPC5200B Pinout Listing
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Table 52. MPC5200B Pinout Listing (continued)
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1 Schmitt
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3 System Design Information
3.1 Power Up/Down Sequencing
(PLL_A VDD), and Core VDD (VDD_CORE). Figure 51. Supply Voltage Sequencing the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage. by more than 0.5 V at any time, including during power-up. Note: Use 1 microsecond or slower rise time for all supplies.
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
3.1.1 Power Up Sequence
ESD protection clamp diodes. Use one microsecond or slower rise time for all supplies.
3.1.2 Power Down Sequence
for the fall times of the power supplies.
- Drop VDD_CORE/PLL_A VDD to 0 V .
- Drop VDD_IO/VDD_IO_MEM supplies.
3.2 System and CPU Core AVDD Power Supply Filtering
recommendation for the required filter circuit. Figure 52. Power Supply Filtering
3.3 Pull-up/Pull-down Resistor Requirements
The MPC5200B requires external pull-up or pull-down resistors on certain pins.
3.3.1 Pull-down Resistor Requirements for TEST pins
The MPC5200B requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1.
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3.3.2 Pull-up Requirements for the PCI Control Lines
Bus specification. This is also required for MOST/Graphics and Large Flash Mode. PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
3.3.3 Pull-up/Pull-down Requiremen ts for MEM_MDQS Pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode. The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
3.4 JTAG
executing test routines and for performing software development and debug functions.
3.4.1 JTAG_TRST
performance, the JTAG_TRST signal must be asserted during power-on reset.
3.4.1.1 JTAG_TRST and PORRESET
be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released. For more details refer to the Reset and JTAG Timing Specification. Figure 53. PORRESET vs. JTAG_TRST
3.4.1.2 Connecting JTAG_TRST
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
3.4.2.1 Boards Interfacing the JTAG Port via a COP Connector
shown reflects only the COP/BDM connector order. the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended. Table 53. COP/BDM Interface Signals output is really an input to the core.
15 TEST_SEL_0 ckstp_out — — I
13 HRESET hreset — 10k Pull-Up O
11 SRESET sreset — 10k Pull-Up O
9 JTAG_TMS tms 100k Pull-Up 10k Pull-Up O
7 JTAG_TCK tck 100k Pull-Up 10k Pull-Up O
2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core.
4 JTAG_TRST trst 100k Pull-Up 10k Pull-Up O
3 JTAG_TDI tdi 100k Pull-Up 10k Pull-Up O
internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
68 Freescale Semiconductor
board sources can drive PORRESET. Figure 54. COP Connector Diagram
3.4.2.2 Boards Without COP Connector
of the JTAG interface without COP connector.
Figure 55. JTAG_TRST Wiring for Boards without COP Connector
4 Ordering Information
Table 54. Ordering Information 1 Shipped in trays. Add “R2” suffix for Tape & Reel. 2 Commercial Qualified to < 250 PPM level. Industrial/Automotive Qualified to AEC-Q100. Automotive has Zero Defect flow. 3 Standard is halide-free with Pb solder balls.
70 Freescale Semiconductor
5 Document Revision History
Table 55 provides a revision history for this hardware specification. Table 55. Document Revision History
1 Clock Frequencies table: 466 MHz was changed to 400 MHz for the e300 Processor Core
2 Added description for PCI CLK Slew Rate for PCI CLK Specifications table. Added description for minimum rates in the DDR SDRAM Memory Write Timing table.
MPC5200B Data Sheet, Rev. 4 Freescale Semiconductor 71
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